JP2001332100A - Dynamic RAM - Google Patents

Abstract

(57) [Problem] To provide a dynamic RAM capable of evaluating the information retention characteristics of a memory cell with a simple configuration. SOLUTION: A memory array in which dynamic memory cells are arranged in a matrix at intersections of word lines and bit lines, and a plurality of memory cells connected to the selected word line are read out to one bit line. A dynamic RAM having a plurality of sense amplifiers for amplifying the stored information by using the precharge voltage of the other bit line as a reference voltage and rewriting the memory cell, with the precharge voltage of both bit lines as the center. A write voltage having the same polarity is written into a memory cell, and after a predetermined time, two memory cells to be evaluated are selected on one bit line, and one memory cell is selected on the other bit line for reference, and A test circuit for amplification by an amplifier is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (random access memory), and more particularly to a technique which is effective when applied to a technique for holding and evaluating information on memory cells.

[0002]

2. Description of the Related Art As a method for evaluating the information retention characteristics of a dynamic memory cell, a method as shown in FIG. 4 can be considered. For the cell of interest, a comparison cell is set on a bit line used as a reference for the cell of interest, and storage charges of less than the maximum signal amount and more than the minimum signal amount are written in the comparison cell, and each word line is simultaneously connected. This is to determine whether or not the storage information is read from the cell of interest as expected.

[0003]

In the above evaluation method,
In order to write a storage charge equal to or less than the maximum signal amount and equal to or greater than the minimum signal amount to the comparison cell, a power supply switching circuit that supplies a voltage corresponding to the sense amplifier unit is required, so that the circuit scale is large. Problems arise.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic type R which can evaluate the information retention characteristics of a memory cell with a simple configuration.
To provide AM. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. A memory array in which dynamic memory cells are arranged in a matrix at intersections of word lines and bit lines, and storage information read to one bit line from the plurality of memory cells connected to the selected word line To a dynamic RAM having a plurality of sense amplifiers for amplifying the precharge voltage of the other bit line as a reference voltage and rewriting the memory cell, and having the same polarity around the precharge voltage of both bit lines. The write voltage is written to the memory cells, and after a predetermined time, two memory cells to be evaluated are selected on one bit line, and one memory cell is selected for reference on the other bit line and amplified by the sense amplifier. Test circuit is provided.

[0006]

FIG. 5 is a schematic layout diagram showing one embodiment of a dynamic RAM (hereinafter referred to as DRAM) to which the present invention is applied. In the figure, the main part of each circuit block constituting the dynamic RAM to which the present invention is applied is shown so that it can be understood. Are formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. The central part 1 is divided into right and left parts with respect to the longitudinal direction of the semiconductor chip.
4 is provided with an input / output interface circuit including an address input circuit, a data input / output circuit, and a bonding pad row, and a power supply circuit including a booster circuit and a step-down circuit. A memory array control circuit (AC) 11 and a main word driver (MWD) 12 are arranged at portions on both sides of the central portion 14 that are in contact with the memory array. The memory array control circuit 11 includes a control circuit for driving a sub-word selection line and a sense amplifier, and a main amplifier. As described above, left and right with respect to the longitudinal direction of the semiconductor chip
A column decoder region (YDC) 13 is provided in the upper and lower central portions in the longitudinal direction in each of the four memory arrays divided into two vertically and two vertically.

As described above, in each memory array, the main word driver 12 generates a main word line selection signal extending so as to penetrate one corresponding memory array. The main word driver area 12
A sub-word selection line driver for sub-word selection is also provided, and extends in parallel with the main word line to form a sub-word selection line selection signal, as described later. The column decoder 13 forms a selection signal of a column selection line extended so as to penetrate one corresponding memory array.

Each of the above memory arrays is divided into a plurality of memory cell arrays (hereinafter, referred to as memory mats) 15. As shown in the enlarged view, the memory mat 15 includes a sense amplifier region 16 and a sub-word driver region 1.
7 and is formed. The sense amplifier region 16
The intersection of the sub-word driver area 17 is an intersection area (cross area) 18. The sense amplifier provided in the sense amplifier region 16 is formed by a CMOS latch circuit. Although not particularly limited, in this embodiment, a so-called one-intersection type or an open bit line type in which a signal of a complementary bit line extending right and left around a sense amplifier is amplified is used. And
The bit lines are arranged alternately with respect to the arrangement. As a result, the bit line provided in the memory mat is divided into halves and alternately divided into two sense amplifier rows sandwiching it.

One memory mat 15 shown as an enlarged view is not particularly limited, but has 512 sub-word lines (word lines) and 1024 complementary bit lines (or data lines) orthogonal thereto. You. In the one memory array, the memory mats 15 are normally 32 in the bit line direction in the bit line extension direction and 2 in the bit line direction for redundancy.
Are provided. Since the two memory mats for redundancy have half the number of memory cells in the end memory mat, the two end memory mats are treated as one memory mat or used for reference. You may. In this case, one memory mat is allocated for redundancy.

The memory mat 15 includes a sense amplifier 1
Since a pair of complementary bit lines are provided with the center at 6,
When viewed in the extending direction of the bit line, the bit line is substantially divided into 16 by the memory mat 15. The four memory mats 15 are provided in the direction in which the word lines extend. As a result, the sub-word lines are divided into four by the memory mats 15 in the extending direction of the word lines.

Since 1024 bit lines are provided in one memory mat 15 except for the end memory mat, about 4K memory cells are connected in the word line direction and 512 sub-word lines are provided. Memory cells of 512 × 32 = 16K are connected in the bit line direction. Thus, one memory array has 4K × 1
It has a storage capacity such as 6K = 64 Mbits, and 4 × 64 in the entire memory chip 10 by four memory arrays.
It has a storage capacity such as M = 256 Mbits.

FIG. 6 shows a DRAM to which the present invention is applied.
1 is a block diagram of one embodiment for explaining the memory mat of FIG. FIG. 6A shows two memory mats M provided in a hierarchical word line type DRAM as shown in FIG.
Circuits corresponding to AT0 and MAT1 are shown in FIG.
Indicates a layout corresponding to the symbol. FIG.
In (a), a memory cell MC including a MOSFET and a cell capacitor CS is connected to all intersections of a bit line BL and a sub-word line WL. The bit line BL is connected to a sense amplifier SA, and the word line WL is connected to a sub-word driver SWD.

In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. On the other hand, four sub-word lines are arranged in the direction of the complementary bit lines. As shown in FIG. 1, in order to select one sub-word line from the sub-word lines divided into two in the main word line direction and the four sub-word lines allocated to the complementary bit line direction, A sub-word selection driver is provided. The sub-word selection driver generates a selection signal for selecting one of the four sub-word selection lines extending in the arrangement direction of the sub-word drivers (sub-word driver row SWDA). Although not shown, the main word line MWL extends in parallel with the sub word line WL. Although not shown, the column selection line YS is arranged parallel to the extension direction of the bit BL so as to be orthogonal to the column selection line YS.

The above two memory mats MAT0 and MAT
1, the sense amplifiers SA of the sense amplifier array SAA provided between the two memory mats MAT0 and MAT1
Are connected to complementary bit lines extending to both sides of the bit line. These sense amplifiers SA correspond to the sense amplifier row SAA.
Is not particularly limited, but one for every two bit lines
Two sense amplifiers SA are arranged. Therefore, the sense amplifier array SAA provided between the memory mats MAT0 and MAT1 has one bit line BL as described above.
If there are 024, half of them, 512 sense amplifiers SA are provided.

Then, in the memory mat MAT0,
The remaining 512 bit lines are connected to the sense amplifiers SA provided in the sense amplifier row SAA on the opposite side of the memory mat MAT1. In the memory mat MAT1, the remaining 512 bit lines are connected to the memory mat MAT0.
Are connected to a sense amplifier SA provided in a sense amplifier row SAA provided on the opposite side to the above. With such a distributed arrangement on both sides of the sense amplifier SA in the bit line direction,
Since it is sufficient to form one sense amplifier alternately at both ends for two bit lines, the memory mat and the sense amplifier row can be densely arranged by adjusting the pitch of the sense amplifier SA and the bit line BL. Can be formed.

The same applies to the sub-word driver SWD. The 512 sub-word lines WL provided in the memory mat MAT0 are divided into 256 lines and connected to the 256 sub-word drivers SWD of the sub-word driver row SWDA arranged on both sides of the memory mat MAT0. In this embodiment, two sub-word lines WL are set as one set, and two sub-word drivers SWD are distributed and arranged. That is, two sub-word drivers are arranged on one end side (upper side in the drawing) of the memory mat MAT0, with one set of sub-word lines corresponding to two memory cells having a common connection portion with the bit line, and adjacent thereto. Assuming a similar set of two sub-word lines as one set,
Two sub-word drivers are arranged on the other end side (lower side in the figure) of memory mat MAT0.

Although not shown, the sub-word driver SWD is a sub-word driver array SWD in which the sub-word driver SWD is formed.
A selection signal for a sub-word line of a memory mat provided on both sides of A is formed. This makes it possible to efficiently disperse and arrange the sub-word drivers SWD corresponding to the sub-word lines formed in accordance with the arrangement pitch of the memory cells, and to perform the selecting operation of the sub-word lines WL at a high speed.

The above-described sub-word driver row SWD
A and a memory cell array (or memory mat) MAT0, MAT1 or the like surrounded by a sense amplifier array SAA at each intersection of a bit line BL and a sub-word line WL.
C is formed. In the memory mat MAT0 in which the memory cells MC are formed, as shown in FIG. 6B, the upper electrode (plate electrode) PL of the storage capacitor CS is connected to all the memory cells MAT0 and MAT1 in the memory mats MAT0 and MAT1.
C is formed in common to form a planar electrode. The power supply to the plate electrode PL is performed by connecting the sub-word driver row SWDA and the memory mat MA via a connection part PLCT from a power supply wiring VPLT wired in the extending direction of the bit line BL.
It is performed at the boundary between T0 and MAT1. In the figure, a storage node SN is a lower electrode of a storage capacitor CS, and indicates a connection portion with an address selection MOSFET.

In this embodiment, as shown in FIG. 6B, the memory mats MA on both sides of the sense amplifier array SAA are provided.
The above-described plate electrodes PL0 and PL1 formed on T0 and MAT1, respectively, are connected to each other by a wiring PLSA using the plate layer itself. Moreover, this wiring PLS
A is provided so as to penetrate the sense amplifier SAA so that the resistance between the two plate electrodes PL0 and PL1 is greatly reduced. Thereby, when the small signal read from the memory cell MC selected between the complementary bit lines BL of the memory mats MAT0 and MAT1 is amplified by the sense amplifier SA, the phases are opposite to each other, which are generated on the plate electrodes PL0 and PL1. Noise can be canceled at high speed, and the plate electrodes PL0 and P0
Noise generated in L1 can be greatly reduced.

Although not shown, only half of the bit lines are connected to the sense amplifiers in the end mat, so there is room for the bit line pitch. Therefore, the bit line of the end mat is halved in length and branched into two in the sense amplifier section, or folded at the far end so that two memory cells are connected to one word line. can do. When such an end mat is used for redundancy, the information retention characteristic of the memory cell is doubled, so that the probability of occurrence of information retention failure in the redundant memory cell is greatly reduced, and a highly reliable redundant memory is provided. A cell can be configured. This redundant memory cell can be effectively used in the evaluation of the information retention characteristics of the memory cell as described later.

FIG. 1 is a schematic circuit diagram for explaining one embodiment of a method for evaluating the information holding characteristic of a memory cell in a DRAM according to the present invention. In this embodiment, the end mat is valid. In the figure, the bit line arranged on the left side of the sense amplifier is an end mat arranged on the left side of the memory array as described above. Therefore, the bit line is formed by folding back at the middle part so that its length becomes half. In this configuration, the number of intersections between one word line and the folded bit line is two,
Two memory cells are simultaneously selected on a bit line by word line selection.

The bit line provided on the right side of the sense amplifier is a bit line forming a normal memory mat, and is linearly extended from the sense amplifier. Therefore, the number of intersections between the word line and the bit line provided in the normal memory mat is one, and only one memory cell is selected in the bit line by the word line selection.

In the DRAM of this embodiment, the attention cell of the bit line provided in the end mat at the time of the test operation has a high level such as VDL (or the ground potential VS of the circuit).
S (low level like S) is written, and the bit line comparison cell normally provided in the mat is also V
A high level such as DL (or a low level such as VSS) is written.

After a lapse of a predetermined time for evaluating the information holding characteristic, the word lines corresponding to the end mat and the normal mat are simultaneously selected. As a result, a read signal corresponding to the storage charge from the target cell and the comparison cell is obtained on the pair of bit lines connected to the sense amplifier. The sense amplifier is activated by turning on the MOSFETs Q1 and Q2 by the sense amplifier start signal and supplying the operating voltages VDL and VSS to the sense amplifier. Since the sense amplifier forms an amplified signal corresponding to the potential difference between the two bit lines, the sense amplifier outputs the amplified signal to determine the information holding ability of the cell of interest.

FIG. 2 is a schematic circuit diagram for explaining another embodiment of the method for evaluating the information holding characteristic of a memory cell in a DRAM according to the present invention. In this embodiment, although not particularly limited, it is directed to evaluation of a memory cell of a normal mat. In the figure, the bit lines arranged on the left and right sides of the sense amplifier extend linearly from the sense amplifier. Therefore, the number of intersections between the word line and the bit line provided in the normal memory mat is one, and one bit line is selected by the word line selection.
Only one memory cell will be selected.

In the DRAM of this embodiment, when the above-mentioned memory cell on the left side, for example, is evaluated during a test operation, two cells of interest on the left bit line are set to a high level such as VDL (or a circuit of the circuit). A low level such as the ground potential VSS is written, and a high level such as VDL (or a low level such as VSS) is written in the comparison cell of the bit line provided in the right mat as in the case of the target cell.

After a lapse of a predetermined time for evaluating the information holding characteristics, the word lines corresponding to the two mats are simultaneously selected. In this case, two word lines are simultaneously selected in the left mat. A pair of bit lines connected to the sense amplifier can obtain read signals corresponding to storage charges from two target cells and one comparison cell. The sense amplifier is activated by turning on the MOSFETs Q1 and Q2 by the sense amplifier start signal and supplying the operating voltages VDL and VSS to the sense amplifier. Since the sense amplifier forms an amplified signal corresponding to the potential difference between the two bit lines, the sense amplifier outputs the amplified signal to determine the information holding ability of the cell of interest.

FIG. 3 is a waveform chart for explaining the principle of evaluating the information holding characteristic of the memory cell in the DRAM shown in FIGS. 1 and 2. When the information holding characteristic of the memory cell is normal (normal), the signal amount read to the bit line on the cell of interest is set to a voltage Vsigmax that is twice as large as the precharge voltage of the bit line.
On the other hand, the signal amount read to the bit line on the comparison cell side is:
The precharge voltage of the bit line is set to a voltage Vsigref for one memory cell. Therefore, when the word lines of both bit lines are simultaneously selected as described above, the input signal Vsig = Vsigmax applied to the differential sense amplifier
−Vsigref, and the same data as the target cell is output. As a result, it is determined that the cell of interest has desired information holding characteristics.

When the information retention characteristic of the memory cell is defective (Cs loss cell), the amount of signal read out to the bit line on the cell of interest depends on the shortage of the capacitance value of the storage capacitor Cs or the large leak current. A high level read signal is obtained for the precharge voltage of
The voltage Vsigmin is less than twice as small. On the other hand, the signal amount read to the bit line on the comparison cell side is equal to the voltage Vsigr for one memory cell with respect to the precharge voltage of the bit line.
Like ef. Therefore, when the word lines of both bit lines are simultaneously selected as described above, the input signal applied to the differential sense amplifier becomes -Vsig = Vsigmax-Vsigref, and data opposite to the cell of interest is output. As a result, the cell of interest is determined to be a defective cell.

In the method of evaluating a memory cell according to this embodiment, it is not necessary to provide a power supply wiring for a test and a changeover switch in the sense amplifier section, and the circuit can be simplified.
The drive circuit for activating the sense amplifier needs to be incorporated in the memory array section arranged at high density.
A selection circuit for selecting a main input / output line and a local input / output line connected to a bit line via a column switch provided in a sense amplifier portion at a place where the drive circuit is formed, and the local bit line In the hierarchical word line method as described above, it is necessary to provide a circuit for amplifying a selection signal necessary for the operation of the sub-word driver, and there is no room in the element formation area. Reducing the number of power supply wirings and switching circuits as described above has a great advantage in the high-density arrangement of the memory array section.

The functions and effects obtained from the above embodiment are as follows. (1) A memory array in which dynamic memory cells are arranged in a matrix at intersections of word lines and bit lines, and a plurality of memory cells connected to the selected word line are read to one bit line. A dynamic RAM having a plurality of sense amplifiers for amplifying the stored information using the precharge voltage of the other bit line as a reference voltage and rewriting the memory cell with the same precharge voltage is used with the precharge voltage of both bit lines as the center. Writing the polarized write voltage into the memory cells, selecting two memory cells to be evaluated on one bit line after a predetermined time,
By providing a test circuit for selecting one memory cell for reference on the other bit line and amplifying it with the sense amplifier, it is possible to evaluate the information retention characteristics of the memory cell with a simple configuration. Can be

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the test circuit for evaluating the memory cell described above can be applied not only to a developed DRAM product but also to a mass-produced DRAM product. The word line may have a two-layer structure with a metal layer in addition to the hierarchical word line method as described above. The input / output interface of the dynamic RAM may be adapted to various types such as DDR SDRAM and SDRAM, or the dynamic RAM may be built in a digital integrated circuit. The present invention can also be applied to a so-called two-intersection or folded bit line type dynamic RAM in which a pair of bit lines are extended in parallel in addition to the one-intersection method.

[0034]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. A memory array in which dynamic memory cells are arranged in a matrix at intersections of word lines and bit lines, and storage information read to one bit line from the plurality of memory cells connected to the selected word line To a dynamic RAM having a plurality of sense amplifiers for amplifying the precharge voltage of the other bit line as a reference voltage and rewriting the memory cell, and having the same polarity around the precharge voltage of both bit lines. The write voltage is written to the memory cells, and after a predetermined time, two memory cells to be evaluated are selected on one bit line, and one memory cell is selected for reference on the other bit line and amplified by the sense amplifier. Of the test circuit, it is possible to evaluate the information retention characteristics of the memory cell with a simple configuration

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram for explaining an embodiment of a method for evaluating information retention characteristics of a memory cell in a DRAM according to the present invention.

FIG. 2 is a schematic circuit diagram for explaining another embodiment of the method for evaluating the information retention characteristics of a memory cell in a DRAM according to the present invention.

FIG. 3 is a waveform chart for explaining the principle of evaluating the information holding characteristic of a memory cell in the DRAM of FIGS. 1 and 2;

FIG. 4 is a schematic circuit diagram for explaining a method of evaluating information retention characteristics of a memory cell in a DRAM studied prior to the present invention.

FIG. 5 is a schematic layout diagram showing one embodiment of a DRAM to which the present invention is applied;

FIG. 6 is a configuration diagram of one embodiment for explaining a memory mat of a DRAM to which the present invention is applied;

[Explanation of symbols]

Q1 to Q2: MOSFET, 10: memory chip, 11
... Array control circuit, 12 ... Main word driver, 13
... column decoder, 15 ... memory mat (memory mat), 16 ... sense amplifier, 17 ... sub-word driver, 18 ... intersection area, SAA ... sense amplifier row, SWD
A: Sub-word driver row, MAT1, MAT2: Memory mat (memory mat), SA: Sense amplifier, SW
D: Sub-word driver, PL0, PL1: Plate electrode, PLSA: Wiring, MWL: Main word line, WL:
Sub word line, BL ... bit line.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Chiaki Dono 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Hiroki Fujisawa 6-chome, Shinmachi, Ome-shi, Tokyo F-term (reference) in Hitachi, Ltd. Device Development Center at 16 2 3G032 AA07 AC02 AE07 AE08 AG04 AH02 AK11 5B024 AA15 BA01 BA11 CA07 EA01 5L106 AA01 DD12 GG07

Claims (1)

[Claims] 1. A memory array in which dynamic memory cells are arranged in a matrix at intersections of word lines and bit lines, and a plurality of memory cells connected to the selected word line are read to one bit line. A plurality of sense amplifiers for amplifying the output storage information using the precharge voltage of the other bit line as a reference voltage and rewriting the memory cells, and a test circuit for evaluating the retention characteristics of the memory cells, The test circuit writes a write voltage having the same polarity around the precharge voltage of both bit lines to a memory cell, selects two memory cells to be evaluated on one bit line after a predetermined time, and selects the other memory cell. Characterized in that one memory cell is selected for reference on a bit line and amplified by the sense amplifier. Rack type RAM.