JPH01212157A - Multiple testing method - Google Patents

Abstract

PURPOSE:To carry out the device tests of respective processors in parallel by using multiplexingly a prescribed console connected to the prescribed processor with respective monitoring means and respectively independently executing respective teat programs while transmitting/receiving data needed for the test between the processor and console. CONSTITUTION:Respective monitoring means 4-1-4-5,... in respective processors 2-1-2-5,... use multiplexingly a prescribed console 5 connected to the prescribed processor 2, for example. While transmitting/receiving the data needed for the test, by carrying out respective test programs 3-1-3-5,..., the device tests of the respective processors 2-1-2-5,... are executed. Thus, the respective monitoring means 4-1-4-5,... can be used multiplexingly by using of one console and the device tests can be independently and parallelly carried out at every processor 2-1-2-5,....

Description

[Detailed Description of the Invention] [Summary] This invention relates to a device testing method for each processor in a signal processing system such as an electronic switching system consisting of a plurality of processors, which does not require ancillary equipment such as a console for each processor.
The purpose of this is to enable device testing to be performed independently and in parallel on each processor and to reduce test time. The processor has monitoring means for transmitting, receiving, and relaying data necessary for testing with other processors during idle time, and each monitor means multiplexes a predetermined console connected to a predetermined processor. , the device test of each processor is performed in parallel by executing each of the test programs independently while exchanging data necessary for the test with the console.

[Industrial application field]

The present invention relates to a device testing method for each processor in a signal processing system such as an electronic switching system including a plurality of processors.

[Conventional technology]

In order to improve the call processing capacity and increase the number of lines that can be accommodated in an electronic switching system, etc., it is effective to have a system configuration in which functions and processing are distributed.

FIG. 4 shows an overall configuration diagram of a function/processing distributed type electronic switching system comprising a plurality of processors. For example, each communication line L I NEO-L is connected to the exchange switch NW.
Line connection control device LCO to LC2 corresponding to INE2
are connected to accommodate each line. At this time, a calling signal exchanged between each communication line LINEO-LINE2,
An incoming call signal or a call control signal such as a dial pulse is processed by each line processor in each line connection control device LCO-LC2 and then processed by each line processor LPR2.
PRO-LPR2 is connected to the call processing processor CPRO via the bucket line 1 in the exchange switch NW, and
PRO performs call processing control for the entire exchange switch NW.

Then, such call processing processors are connected to CPRO to CP.
As shown in R2, by providing a plurality of units and performing call processing control in a distributed manner, the call processing capacity of the entire system is improved and the line capacity is improved.

At this time, the management processor MPR
By collectively controlling PRO to CPR2, comprehensive control of the entire system is performed.

FIG. 5 shows an example of the configuration of each processor in the system of FIG. 4 and a connection configuration between the processors.

Each line processor LPRO to LPR2, call processing processor CPRO to CPR2, and management processor MPR are
As shown in #O and #1, those with the same configuration are duplicated, and if a failure or the like occurs in either one, the other is configured to back up.

In FIG. 5, CC is a central processing unit and is the control center of each processor. MM is a main storage device that stores various control programs, control data, and the like. The CHC is a channel device, and controls connections between various input/output devices and the CC and MM. FM is an external storage device and operates as an auxiliary storage device for the main storage device MM.

Next, line processor LPRO and call processing processor CP
The RO is connected by the signal line control device SGC and the common signal line device C3H, which are connected to each channel device CHC separately for #0 and #1, and both the SGC and C3E connect the packet line 1, etc. in the exchange switch NW in Fig. 4. Controls the transmission and reception of signals transmitted through the network. Other line processors LPR1, LP
R2 and the call processing processor CPRO are connected in the same manner as above, and a line processor (not particularly shown) is similarly connected to the other call processing processors CPRI and CPR2.

Furthermore, a call processing processor CPRO and a management processor MP
R is connected by each channel-to-channel adapter OCA that is connected to each channel device CHC separately for #0 and #1, and controls the transmission and reception of signals transmitted between each central processing unit CC or each main memory device MM. Other call processing processors CPR1 and CPR2 and management processor MPR are also connected in the same manner as above.

Also, channel device CH of #0 of management processor MPR
A magnetic tape device MT is connected to C, and stores various control programs and the like. Similarly, a console VDU for various controls, which is a man-machine interface, is connected to the CHC.

For example, in an electronic switching system where functions and processing are distributed among multiple processors as described above, tax examinations (
After the equipment is delivered to the site and assembled as a system, if the replacement online software is to be tested to ensure proper operation (tests to ensure that the hardware is adequate), conventionally, for example, the # of MPR shown in Figure 5 has been used. 0 magnetic tape device MT
Load a device test program from #0 to the storage device MM, and the #0 CC executes the program to perform a device test for the entire MPR.
Under the control of PR CPROlLPROlLPRI,...
・A method was adopted in which equipment tests were conducted sequentially.

In addition, in cases where there is not enough time to conduct all tests in front of the customer, such as during an in-house test where the system is assembled and an acceptance test is conducted in the presence of the customer, each processor can be installed as shown in Figure 6. Tests were conducted by separating and independent processors and connecting them to a console VDU for input/output, which is a man-machine interface.

Note that each device marked with diagonal lines in FIG. 5 is a part that must operate normally at the minimum when each processor is started up, and the operation of this part is guaranteed to operate normally in advance. Not subject to testing.

[Problem to be solved by the invention]

However, as shown in FIG. 5, in electronic switching systems and the like in which functions and processing are distributed among multiple processors, the number of system components increases in proportion to the number of processors. When testing all devices, such as in a tax control test, there is a problem in that the test takes a long time in proportion to the increase in the number of devices to be tested.

On the other hand, in order to perform tests by connecting a console to each processor as shown in Figure 6, there are problems such as the need for as many consoles as the number of processors, and the need for an interface for the consoles. was.

In order to solve the above problems, the present invention makes it possible to perform device tests independently and in parallel on each processor without requiring an accompanying device such as a console for each processor, thereby shortening test time. With the goal.

[Means to solve the problem]

FIG. 1 is a functional block diagram of the present invention. The present invention
For example, a control system such as an electronic switching system is composed of a plurality of processors 2-1 to 2-5, etc., where the processor 2-1 is, for example, a management processor that controls the entire system, and the processor 2- 2.2-3 are a plurality of call processing processors that perform, for example, call processing control, and processors 2-4.2-5 are, for example, a plurality of line processors that perform line control.

Then, each of the processor sensors 2-1 to 2-5, . . . executes an independent test program 3-1 to 3-5, . It has monitor means 4-1 to 4-5, . . . for transmitting, receiving, and relaying data necessary for testing to and from the processor. That is, for example, in the processor 2-2, the monitor means 4-2 executes the test program 3-2. Then, during the free time during execution, commands necessary for the test are sent and received with, for example, the processor 2-1, and between, for example, the processors 2-4 and 2-1, and 2-5 and 2-1. Relays the sending and receiving of commands, etc. necessary for testing.

Here, each of the above test programs 3-1 to 3-5,...
The idle time during execution is, for example, the idle time when I/O is used, the idle time when dummy timing is executed by each test program, etc.

[For production]

By the above means, each processor 2-1 to 2-5,...
Each monitor means 4-1 to 4-5, . . . uses a predetermined console 5 connected to a predetermined processor, e.g. Each test program 3-1~ while exchanging data
By executing steps 3-5, . . . , each processor 2
-1 to 2-5, . . . carry out device tests.

For example, the monitor means 4- of the processor 2-4 or 2-5
4 or 4-5 is a monitor means 4-2 of the processor 2-2.
The test program 3-4 or 3-5 can be executed independently to perform device testing.

Due to the above operation, each processor 2-1 to 2-5,...
Each of the monitor means 4-1 to 4-5, . Device tests can be performed independently and in parallel for each of the processors 2-1 to 2-5, .

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail.

The present invention provides a multiprocessing function that allows a monitor program provided in each processor to execute a test program to transmit, receive, and relay data necessary for testing with other processors without changing the conventional system configuration. It is characterized by having the following. Therefore, the overall system configuration is the same as that shown in FIGS. 4 and 5 described above.

Next, FIG. 2 is a block diagram of an embodiment of the present invention.

It is roughly divided into a monitor 6 and a test program execution section 7, both of which are connected to the MPR, CPRO to CPR shown in FIG.
2, and each central processing unit CC of each #0 in LPRO to LPR2. Loaded into device MM.

In the monitor 6 shown in FIG. 2, the test program starting section 8
performs startup 14 on the test program 7, and also receives and receives an end notification 15 from the test program 7. Also, a call 16 is made to the I/O access unit 9, and conversely the I/O
The /O access unit 9 performs a return 17 to the test program starting unit 8.

The test program 7 calls 2 to the space/time control unit 12.
4, and also calls 18 to the I/O access unit 9.
I do. Conversely, the I/O access unit 9 performs a return 19 to the test program 7.

The interrupt analyzer/O accepts and accepts interrupts 20 from the outside, and conversely performs interrupt recovery 21. Also, based on interrupt 20, I/O
An interrupt notification 22 is sent to the access unit 9, and the queue control unit 1
1, an instruction 25 is given to connect the interrupt request to the queue for the interrupt 20, or an interruption 26 is given to the idle time control unit 12 and the communication request processing unit 13.

The I/O access unit 9 makes a call 2 to the idle time control unit 9.
Do step 3.

The free time control unit 12 issues a retrieval instruction 27 to the queue control unit 11 and executes an execution 28 to the communication request processing unit 13. Conversely, the communication request processing 13 is performed by the idle time control unit 1.
A termination notification 29 is given to 2.

The operation of the embodiment having the above configuration will be explained below using the operation timing chart of FIG.

Now, let us consider a case where the embodiment shown in FIG. 2 is executed by, for example, the central processing unit CC #0 of the CPRO shown in FIG.

First, the console VD connected to the MPR in Figure 5
In response to the command input from U, the test program starting unit 8 shown in FIG. 2 starts the test program 7 at tl in FIG.

Then, at t2 during this execution, the interrupt analyzer/O
When a communication request interrupt 20 is input from another processor, such as LPRO (FIG. 5), the interrupt analyzer/O
As shown at t3 in Figure (al), an instruction 25 is given to the queue control unit 11 to connect the input communication request to the queue, and as a result, the queue control unit 11 stacks the communication request in the queue ( 3(a) 30) After this operation, the test program 7 continues to be executed.

Next, at t4 in FIG. 3(a), the test program 7 uses the I/O to print out intermediate results.
A call 18 is made to the access unit 9, and based on this, T
, /'O access unit 9 accesses the printer, etc. (fifth
I/O activation 31 (not specifically shown in the figure) is performed.

As a result, the I/O usage time and space time becomes T1, and the I/O access unit 9 makes a call 23 to the idle time control unit 12 at t. In response to this, the space/time control unit 12 performs t,
Instructs the queue control unit 11 to take out 27
and stacks it in the queue (Figure 3(a) 30)
Then, at t, the communication request processing unit 13 is instructed to execute the communication request 28.
cormorant. As a result, the communication request processing unit 13 transfers communication data from, for example, the LPRO to the MPR during the I/O use spatio-temporal time T.
(Fig. 5).

At t8 in the middle of the above processing, an interrupt 20 due to the completion of the printout processing is sent to the interrupt analysis unit/O
, the communication request processing unit 13 is sent from the interrupt analysis unit/O.
, and an interruption 26 is performed on the idle time control unit 12. Subsequently, at t9, a connection instruction 25 is issued from the interrupt analysis unit/O to the queue control unit 11, whereby the queue control unit 11 performs the communication processing. The intermediate results are stacked in a queue (Fig. 3(a) 32). At the same time, the interrupt analysis unit/O sends an interrupt notification 22 to the I/O access unit 9, and after the I/O access unit 9 performs post-processing related to printout, etc., the test program 7 A return 19 is performed for.

After that, the test program 7 is executed again, and at t, a dummy timing T2 when the test program is executed.
(waiting time of the test program 7).As a result, the test program 7 makes a call 24 to the idle time control section 12, and control is transferred to the idle time control section 12 again. The free time control unit 12 issues a retrieval instruction 27 to the queue control unit 11 in the tls, and stores the stack in the queue (
3(a) 32) is retrieved, and then at t13, the communication request processing unit 1
3 to execute 28 from the point of interruption of the communication request. In response to this, at dummy timing Tt during test program execution, the communication request processing unit 13
The process of relaying the communication data from to the MPR (FIG. 5) is restarted.

Then, at t14 in FIG. 3(a), the communication request processing unit 1
When the communication processing in step 3 is completed, a termination notification 29 is given to the free time control unit 12, and control is returned to the free time control unit 12.

After that, at tls, the interrupt 20 of the end of dummy timing T2 during test program execution is input from the test program 7 to the interrupt analysis unit /O, and in response to this, the interrupt analysis unit 1O inputs the interrupt 20 to the test program 7 at to. In response, interrupt return 21 is performed and control returns to the test program 7.

And t'l? When the processing by the test program is completed, a completion notification 15 is sent to the test program starting section 8.
The test program starting section 8 notifies the console VDU (FIG. 5) of this fact, and the CPRO device test ends.

In the embodiment shown in FIG. 2, the test program starting section 8 may make a direct call 16 to the I/O access section 9 to print out test results and display commands. Free time can be used in exactly the same way as in the above case.

At this time, naturally, after the operation in the I/O access unit 9 is completed,
A return 17 is performed for the test program starting section 8.

As described above, in this embodiment, for example, while the monitor 6 (FIG. 2) of the CPRO (FIG. 5) executes the test program 7, the I/O usage spatio-temporal time T is calculated.

Or dummy timing 'rt when running test program
(Using Fig. 3(a)), the other PRO~LPR
2 and the console VDU connected to the MPR, for example, the process of sending test commands from the console VDU to other LPROs to LPR2, or the process of displaying intermediate test results on the console VDU. conduct. Therefore, the monitor 6 of other LPRO-LPR2 etc. also uses the console VDU multiplexed, for example, LPRON.
While simultaneously displaying the LPR2 test progress on the 3-split screen on the console VDU, you can also view your own test program 7.
can be executed.

The overall operation is shown in FIG. 3 (bl). That is, for example, the CPRO is executing the test program 7 (Fig. 2) under the control of the monitor 6 (Fig. 2) (Sl-32), and during the When idle time occurs (S3 → S4), monitor 6
For example, by the transmission process (S6') in LPR1,
The communication data transmitted to R (VDU) (FIG. 5) is received (S5-36). Subsequently, the monitor 6 performs a transmission process to transmit the received communication data to the MPR (S7-S8), and the communication data is received by the MPR through a reception process (S8').

Thereafter, the monitor 6 returns control to the test program 7 again (S9-3/O-311-312) and continues testing the CPRO device.

Subsequently, when empty time occurs again (S13-314),
For example, the monitor 6 performs transmission processing (S1
6') performs a reception process for the communication data sent to the LPRO (S15-316), and then performs a transmission process to send the received communication data to the LPRO (S17-318). Reception processing (8
18') receives the communication data. after that,
The monitor 6 returns control to the test program 7 again (S
19→S20→521).

As described above, communication data can be relayed between other processors by using the idle time T3 or T4 of the test program 7.

In the above embodiment, the console V shown in FIG.
The DU does not need to have one seat; for example, by connecting two consoles to the MPR and specifying the processor that executes the command when inputting commands from each console, it is possible to correspond to the processors controlled by each console. It is also possible to use each console as if it were directly connected to each processor. In this case as well, each console is used multiplexed by multiple processors in a time-sharing manner.

It is assumed that the interrupts used in the monitor are set in advance so that they are not masked for a long time.

〔Effect of the invention〕

According to the present invention, there is no need for ancillary equipment such as a console for each processor, and it is possible to perform device tests on each processor independently and in parallel while the entire system is assembled in an operational state. .

In this case, the communication data is relayed at various dummy timings in the test program or during the idle time that occurs when the monitor uses Ilo, so it has little effect on the execution of the test program in each processor and affects the overall device test. The required time is significantly reduced to 1/the number of processors compared to the conventional example in which the process is performed sequentially for each processor.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of the present invention; FIG. 2 is a configuration diagram of an embodiment of the present invention; FIG. FIG. 4 is an overall configuration diagram of an electronic switching system composed of a plurality of processors, FIG. 5 is a connection diagram between each processor, and FIG. 6 is a configuration diagram of a conventional example. 2-1 to 2- 5... Processor, 3-1 to 3-5... Test program, 4-1 to 4-
5...Monitoring means, 5...Console.

Claims (1)

[Claims] 1) In a signal processing system composed of a plurality of processors (2-1, 2-2, . . . ), an independent test program (3
-1, 3-2, . . .), and also transmits, receives, and relays data necessary for testing with other processors during idle time when each test program is executed.
-1, 4-2, . By independently executing the test programs (3-1, 3-2, . . . ) while exchanging data necessary for the test,
1, 2-2, . . . ) are performed in parallel. 2) The plurality of processors include a management processor that performs overall system control in the electronic switching system, a plurality of call processing processors that are connected to the management processor and perform call processing control, and a line control system that is connected to each of the call processing processors. 2. The multiplex test method according to claim 1, wherein the console is connected to the management processor. 3) The idle time during the execution of each test program is the I/O
3. The multiple test method according to claim 1, wherein the idle time is the idle time during use and the idle time when dummy timing is executed by each of the test programs.