JPH01212083A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To attain a stable automatic iris control without being influenced by the difference of the spot position of a screen or the like by disposing a comparison circuit and comparing a signal value at the last time for every one screen of an integrating signal obtained by integrating a video signal with a reference value set correspondingly to the quantity of the proper exposure of a solid-state image pickup element. CONSTITUTION:The comparison circuit 13 is provided with two comparators COM1, COM2 to which the integrating value from a RC integrating circuit 12 having a discharging transistor Q is inputted. Then, the result of comparing the scale in the comparators COM1, COM2 is recorded in flip flops FF1, FF2 in the final timing te of a field corresponding to a vertical blanking period V. Since the comparison circuit 13 compares the signal value at the final time for every one screen of the integrating signal obtained by integrating the video signal with the reference value set correspondingly to the quantity of the proper exposure of the solid-state image pickup element, the exposure can be automatically controlled based on a feed back signal according to the integrating signal corresponding to the brightness of all the screen.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device that performs automatic exposure control on a solid-state imaging device such as a COD.

(b) Conventional technology Exposure control in conventional imaging devices, such as television cameras, usually involves controlling a mechanical diaphragm mechanism inside the lens barrel using an iris control circuit, which is a factor in increasing costs.

For this reason, in solid-state imaging devices such as television cameras that use solid-state imaging devices, attempts have been made to perform electronic automatic exposure control (auto iris) by utilizing the driving principle of the solid-state imaging device.

For example, in Utility Model Application No. 61-139527, in a frame transfer type CCD solid-state image sensor, in the middle of the photoelectric conversion period of each vertical blanking period, an image that has been photoelectrically converted and accumulated in the light receiving area of this element is stored. Exposure control means is provided for transferring and discharging charges in a direction opposite to the transfer direction for reading image signals, and accumulating photoelectrically converted image charges only during the remaining photoelectric conversion period (effective photoelectric conversion period) for one screen. things are being proposed. Therefore, according to such an exposure control means, an optimum exposure state can be obtained by changing the timing of reverse charge transfer according to the brightness of the subject.

The basic configuration of a solid-state imaging device equipped with such an auto-iris function is shown in FIG.

In the figure, (S) indicates the light receiving area (1) and the accumulation area (
A frame transfer type CCD solid-state image sensor consisting of a horizontal register (3) and a light receiving area (1).
After transferring and accumulating the image charge obtained by photoelectric conversion in units of one screen (field unit) in each vertical blanking period to the storage area (2), the image charge is transferred to the horizontal register in units of one scanning line in each horizontal blanking period. (3) is output as an image signal. Then, this continuous image signal in field units is subjected to signal processing such as sample hold and amplification in a signal processing circuit (4), and can be outputted to an external device as a video signal.

The CCD solid-state image sensor (S) is driven by a clock, and the light receiving area (1) has a first transfer lock generation circuit (8) or a reverse transfer lock generation circuit (9).
) is selected by the clock selection circuit (15) and the four-phase clocks 4, 1 to φ, 4 obtained are supplied to the storage area (2).
are supplied with four-phase clocks φsI to φs4 from the second transfer lock generation circuit (10), and are further supplied with the horizontal register (
3) is supplied with a two-phase lock jn++4Mm from the horizontal transfer lock generation circuit (11).

In addition, each of these clock generation circuits (8), (9), (10
).

(11) is created based on the basic clock from the same oscillation circuit (5), and based on this basic clock, the horizontal blanking pulse generation circuit (6) creates a pulse indicating the horizontal blanking period, and Based on the blanking pulse, a vertical blanking pulse generation circuit (7) generates a pulse indicating a vertical blanking period. Then, this vertical blanking pulse is input to the first transfer lock generation circuit (8), which determines the generation timing of the first transfer lock to be sent out in a specific period for each vertical blanking, and also The ranking pulse is input to the reverse feed lock generation circuit (9), which determines the generation timing of the reverse feed lock to be sent during the horizontal period of each horizontal blanking.

(14) is a reverse feed lock supply timing generating means, in which a clock selection circuit (15) selects the clock of the reverse feed lock generation circuit (9) and
) is used to determine in which horizontal retrace period the reverse speed is to be driven. The timing determination method of this reverse feed lock supply timing generation means (14) is based on the horizontal blanking pulse of the horizontal blanking pulse generation circuit (6) and the vertical blanking pulse of the vertical blanking pulse generation circuit (7). , and further integrates the video signal (luminance signal) from the signal processing circuit (4) field by field and outputs the integrated value from the integrating circuit (12) to the comparing circuit (1).
In step 3), the timing is delayed in accordance with the feedback signal compared with a predetermined reference value, that is, the larger (brighter) the value of the video signal (luminance signal) is. Note that this comparison process is based on the output from the COD solid-state image sensor (S) (
It is also possible to perform the process directly on the image signal (image signal) as the image information.

A conventional configuration of such a comparison circuit (13) is shown in FIG. The circuit in the figure sets the integrated value from the RC integration circuit (12) consisting of a resistor R1 and a capacitor C1 to a reference voltage V of a resistor R2.
r and is provided with a comparator COM for this purpose. The output of this comparator COH is then applied to two flip-flops FFI at two different timings tl and t2 in the middle position of the vertical blanking period.
, is set to FF2.

Therefore, a total of 2 bits of data from these flip-flops FFI and FF2 becomes the above-mentioned feedback signal, and the reverse feed lock supply timing generating means (14
) to determine whether to advance or delay the reverse feed lock supply timing. Note that the transistor Q is provided to discharge the integral capacitor C1 for each field, that is, for each vertical blanking period.

According to such a conventional comparison circuit (13), when there is a bright spot W at the bottom of the screen as shown in FIG.
As shown in FIG. 9, the output of the video signal Y(t) increases in the latter half of the vertical blanking period V, and its integral value J
The curve (a) of Y(t)dt rises. Also, the 10th
When there is a bright spot W at the top of the screen as shown in the figure, the output of the video signal Y(t) increases in the first half of the vertical blanking period V as shown in FIG. 11, and its integral value JY( t) The curve (b) of dt will rise.

Therefore, as shown in FIG. 12 in which these integral value curves are superimposed, the history of the integral value JY(t)dt differs because the spot W position is different even though the brightness of the entire screen is the same. As a result, the comparator C at timing tl and t2
Since the output value from the OM differs in both cases, there was a fear that the feedback signals set to the flip-flops FFI and FF2 would show opposite results.

(c) Problems to be Solved by the Invention The present invention is as described above, and includes a comparison circuit that obtains a feedback signal that corresponds to the brightness of the entire screen without being affected by differences in spot positions on the screen. The purpose of the present invention is to provide a solid-state imaging device that can perform the following steps.

(d) Means to solve the problem The first solid-state imaging device of the present invention has the following configuration.

(1) A solid-state image sensor that photoelectrically converts the image it receives at predetermined time intervals to obtain continuous image information on a screen-by-screen basis; (2) Integrates zero-image information obtained by the solid-state image sensor on a screen-by-screen basis. an integrating circuit; 0) a comparison circuit (4) that compares the signal value of the integral signal obtained from the integrating circuit at the final point in time for each screen with a reference value set in accordance with the appropriate exposure amount of the solid-state image sensor; Automatic exposure control means for variably setting an effective photoelectric conversion period of the solid-state image sensor for each predetermined time based on a comparison result of the comparison circuit.

Furthermore, the second solid-state imaging device of the present invention has the following configuration.

(1) A solid-state image sensor that photoelectrically converts the image it receives at predetermined time intervals to obtain continuous image information on a screen-by-screen basis; (2) An integral that integrates the image information obtained by the solid-state image sensor on a screen-by-screen basis. (3) a signal value at the final point in time for each screen of the integral signal obtained from the integrating circuit and a first reference value and its lower limit value set in correspondence with the upper limit value of the appropriate exposure amount of the solid-state image sensor; By comparing with the second standard value set corresponding to
An exposure limit signal is output when the value of the integral signal is greater than the first reference value, an exposure fixing signal is output when the value of the integral signal is smaller than the first reference value and larger than the second reference value, and the exposure fixing signal is output when the value of the integral signal is smaller than the second reference value. A comparison circuit that outputs an exposure promotion signal at certain times, (4)
Based on the comparison result of the comparison circuit, the effective photoelectric conversion period of the solid-state image sensor is controlled to expand or contract at predetermined time intervals, and when the exposure limit signal is received, the effective photoelectric conversion period at this time is shortened by a specific time. The automatic exposure control means fixes the effective photoelectric conversion period at this time when the exposure fixing signal is received, and extends the effective photoelectric conversion period at this time by a specific time when the exposure promotion signal is received.

(E) Function According to the solid-state imaging device of the present invention, the comparison circuit is set in accordance with the signal value at the final point in each screen of the integrated signal obtained by refining the video signal and the appropriate exposure amount of the solid-state imaging device. Since it is compared with a reference value, exposure control can be automatically performed based on a feedback signal that follows an integral signal corresponding to the brightness of the entire screen.

(f) Example The solid-state imaging device of the present invention has the same basic configuration as, for example, the solid-state imaging device shown in FIG. (13
).

FIG. 1 shows a comparison circuit (13) used in the solid-state imaging device of the present invention.
), the comparator circuit (13) in the same figure has a discharging transistor Q as in FIG.
) are provided with two comparators COMI and C0M2 to which the integral value JY(t)dt is input. This first
The other input of the comparator CQMI is connected to the voltage dividing point of a resistor R2 that can variably set the first reference voltage Vrl corresponding to the upper limit of proper exposure, and the other input of the second comparator C0M2 is connected is a resistor R that can be variably set to a second reference voltage Vr2 (lower than Vrl) corresponding to the lower limit of proper exposure.
3 voltage dividing points are connected. The results of the magnitude comparison by these comparators COMI and C0M2 are stored in the flip-flops FFI° and FF2'' at the final timing tQ of the field corresponding to the vertical blanking period V.

Therefore, the flip-props FFI" and FF2" both have the final timing t of the vertical blanking period V when the histories (a) and (b) of both integral values in FIG. 12 finally match.
At step e, as shown in FIG. 2, the result of comparing the integral value JY(t)dt with the reference values Vrl and Vr2 is stored and output. This flip-flop FF1".

If the output of FF2'' is 2-bit data [xi, x2], for example, specifically, [0,0] is JY(t)dt≧Vrl.

[1,0] is Vrl > f Y(t)dt≧Vr2
゜[1,1] will result in Vr2 > f Y(t)dt.

In the solid-state imaging device of the present invention, these three types of 2-bit data [0,0], [1,0], and [1,1] are used as "exposure limit signal" and "exposure fixed signal" respectively. Based on these signals, the reverse feed lock supply timing generating means (14) in FIG. In step 1), the effective photoelectric conversion period for each frame period is expanded or contracted.

Such a reverse feed lock supply timing generating means (14
), as shown in FIG. 3, there is a decoder (141) that decodes 2-bit data, and a
Bit up/down counter (142).

The upper 5 bits are 32 in steps of 8 from θ to 256.
It consists of a step counter (143) that can count times, and a comparator (144) that detects coincidence of the output values of both counters (142) and (143).

Therefore, according to this circuit (14), the comparison circuit (1
The input signal [xi, x2] from 3) is the “exposure limit signal,
When , the decoder (141) inputs the up/down counter (1
42), and this value is counted up by 1. Conversely, when the exposure promotion signal is present, the decoder (141) inputs a down signal to the up/down counter (142), and this value counts down by 1. Furthermore, a 1W output fixed signal.

In this case, no signal is output and the up/down counter (14
2) will continue to be held.

In this way, the up/down counter (142) stores the step number (increases or decreases depending on the amount of light n) when the photoelectric conversion period T in the vertical blanking period V is divided into 32 steps. On the other hand, the step counter (143)
is reset by the vertical blanking pulse Pv, and the horizontal blanking pulse ph is reset over the subsequent photoelectric conversion period T.
While counting from 0 to 31 every 8, when this value reaches the set value of the up/down counter (142), at this timing the comparator (144) converts the reverse feed lock supply timing pulse pb to the clock selection circuit. (IS).

Therefore, as shown in FIG. 4, the clock selection circuit (15) supplies the reverse feed lock≠b to the storage area (2) of the CCD solid-state image sensor (S) only when the above timing pulse pb is generated. As a result, during the period Te (referred to as the effective photoelectric conversion period) from the end of the reverse speed drive of the storage area (2) to the start of the forward direction transfer drive due to the first transfer lock≠f, image charges are actually generated. Photoelectric conversion of the charges used is performed.

If the amount of photoelectric conversion during the effective photoelectric conversion period Te is too large, resulting in overexposure as shown in the curve (c) in FIG. 2, the supply timing of reverse feed lock≠b in FIG.
There will be a delay of one step [T/32] in the direction of E,
[1
The effective photoelectric conversion period Te continues to be shortened at a constant speed at a rate of step/1 vertical blanking period. On the other hand, in the case of insufficient exposure as shown in the curve (C) in Fig. 2, the supply timing of the reverse feed lock φb in Fig. 4 is changed by 1 in the direction of 0PEN.
The effective photoelectric conversion period Te is accelerated by a step [T/32], and the effective photoelectric conversion period Te continues to be extended at a constant speed at a rate of [1 step/1 vertical blanking period] until proper exposure is achieved.

When the exposure falls within the proper exposure range as shown by the curve (E) in Figure 2, the supply timing of the reverse feed lock in Figure 4 does not change as long as it stays within this range, and the effective photoelectric conversion period Te increases. It becomes a fixed state.

The reverse feed lock supply timing generating means (14) that performs automatic exposure control as described above not only expands and contracts the effective photoelectric conversion period Te, but also changes the period T within the appropriate exposure range.
Since e is fixed, it is possible to eliminate flickering on the playback screen when the period Te is alternately extended and shortened. Furthermore, since the expansion/contraction operation changes sequentially with respect to the target at regular intervals, deterioration of the image quality of the reproduced screen due to sudden changes in exposure can be suppressed. Further, the step amount of this exposure change can be freely changed by independently setting the step widths for both lengthening and shortening of the effective photoelectric conversion period Te.

In the embodiment of the device of the present invention described in detail above, as shown in FIG.
The reference voltage Vr of both comparators COMI, C0M2
1 and Vr2 can be individually variably set, but as shown in FIG. 5, a single reference value Vr.

It is also possible to use a circuit device that allows for variable setting of only the number of points and improves operability. In other words, the circuit shown in the same figure calculates the integral value JY of the video signal.
(t) Voltage values Yl and Y2 of two levels, high and low, which are proportional to the exposure amount obtained by dividing the power supply voltage according to dt using a transistor Q r and a series connection of resistors R4, R5, and R6, are divided into a single voltage value Yl and Y2. It is compared with a reference value Vro, and similarly to the circuit of FIG. 1, three types of signals are output: "exposure limit signal,""exposure fixing signal," and "exposure promotion signal."

No. 1 above. In any of the comparison circuits shown in Fig. 5, when converting the circuit into an IC, the range of the above-mentioned appropriate exposure amount can be easily changed by simply changing the value of the external resistor.
As in the conventional circuit shown in FIG. 7, the judgment timing t1. t
The benefits are greater than those that cannot be changed.

Furthermore, in the device according to the embodiment of the present invention detailed above, CC
Although the example is given in which unnecessary charges are removed by reverse speed driving of the light receiving area (1) of the D solid-state image sensor, the present invention is not limited to this, and for example, the unnecessary charges may be removed to the drain deep in the substrate at - degrees. It may be a configuration. Therefore, in the present invention, it is of course possible to employ an interline type CCD solid-state image sensor or a MOS type solid-state image sensor in addition to the frame transfer type CCD solid-state image sensor.

(G) Effects of the Invention As is clear from the above description, the solid-state imaging device of the present invention has the following effects:
A comparison circuit for determining overexposure or underexposure compares the signal value at the final point in time for each screen of the integrated signal obtained by integrating the video signal with a reference value set corresponding to the appropriate exposure amount of the solid-state image sensor. Because of this configuration, a feedback signal corresponding to the brightness of the entire screen can be obtained from this comparison circuit.

Therefore, according to the present invention, stable auto-iris control is possible without being affected by differences in spot positions on the screen.

[Brief explanation of the drawing]

1 and 5 are block diagrams of different specific examples of comparison circuits used in the solid-state imaging device of the present invention, and FIGS. 2, 4, and 9
11 and 12 are signal diagrams on the time axis, FIG. 3 is a circuit configuration diagram of the reverse feed lock supply timing generating means used in the device of the present invention, and FIG. 6 is a basic configuration of the solid-state imaging device. FIG. 7 is a circuit diagram showing a comparison circuit of the conventional device, and FIGS. 8 and 10 are schematic diagrams of the imaging screen. (1)...Light receiving area, (2)...Storage area, (
3)...Horizontal register, (4)...Signal processing circuit,
(8), (9), <10), (11)...Clock generation circuit, (12)...Integrator circuit, (13)...
Comparison circuit, (14)... Reverse feed lock supply timing generation means, (15)... Clock selection circuit.

Claims (2)

[Claims] (1) A solid-state image sensor that photoelectrically converts a received image at predetermined time intervals to obtain continuous image information on a screen-by-screen basis; an integrating circuit that integrates the image information obtained by the solid-state image sensor on a screen-by-screen basis; A comparison circuit that compares the signal value at the final point of each screen of the integral signal obtained from the integration circuit with a reference value set corresponding to the appropriate exposure amount of the solid-state image sensor, and a comparison result of the comparison circuit. A solid-state imaging device comprising automatic exposure control means for variably setting an effective photoelectric conversion period of the solid-state imaging device for each predetermined time based on the solid-state imaging device. (2) A solid-state image sensor that photoelectrically converts a received light image at predetermined time intervals to obtain continuous image information on a screen-by-screen basis; an integrating circuit that integrates image information obtained by the solid-state image sensor on a screen-by-screen basis; A first reference value is set corresponding to the signal value at the final point of each screen of the integral signal obtained from the integrating circuit and an upper limit value of the appropriate exposure amount of the solid-state image sensor, and a first reference value is set corresponding to the lower limit value thereof. By comparing the integrated signal value with the second reference value, an exposure limit signal is output when the value of the integral signal is larger than the first reference value, and an exposure limit signal is output when the value of the integrated signal is smaller than the first reference value and larger than the second reference value. a comparison circuit that outputs a fixed signal and outputs an exposure promotion signal when the signal is smaller than a second reference value; and one that controls expansion and contraction of the effective photoelectric conversion period of the solid-state image sensor every predetermined time based on the comparison result of the comparison circuit. When the exposure limit signal is received, the effective photoelectric conversion period at this time is shortened by a specific time, and when the exposure fixing signal is received, the effective photoelectric conversion period at this time is fixed, and the exposure promotion signal is received. A solid-state imaging device comprising an automatic exposure control means for extending an effective photoelectric conversion period by a specific time when a photoelectric conversion period occurs.