JPH01198194A - Video signal processor - Google Patents

Abstract

PURPOSE:To smooth the change of data in a vertical direction between fields, and to reduce a jitter between the fields to occur at the time of one field by providing an arithmetic circuit and a control circuit to perform line interpolation, and interpolating data by the memory of one field and the memory space of 1H and the line interpolation. CONSTITUTION:A first luminance signal and color difference signal data of a horizontal scanning period are written in a field memory 5, and simultaneously, are written in a line memory 10 as well. The other luminance signal and color difference signal data of the horizontal scanning period are written in the field memory 5. Each of the luminance signal and color difference signal data of the horizontal scanning period to be read out of the field memory 5 and the luminance signal and color difference signal data of the horizontal scanning period to be read out of the line memory 10 are halved by dividers 11, 12. These respective halved data are supplied to an adder 13, and by averaging the data of 2H, an interval is interpolated. Thus, the change of the data in the vertical direction can be smoothed between the fields by less number of blocks, and simultaneously, the jitter occurring in the vertical direction can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device using field memory, line memory, and line interpolation.

2. Description of the Related Art In recent years, image display devices that use general-purpose or video memory and digitally process video signals have come into use.

A conventional video signal processing device will be explained below. Third
The figure is a block diagram of a conventional video signal processing device.

First, the composite video signal inputted from the composite video signal input terminal 1 is processed by the demodulator 2 into a luminance signal and a color difference signal R-Y.
It is demodulated into B-Y. The demodulator 2 demodulates the luminance signal, color difference signals R-Y, B-Y, and 3-digit parallel output signals, which are time-divided by the switch 3 and output as serial data A.
/D converter 4°. In the A/D converter 4, data obtained by digitally converting the luminance signal 9 and the color difference signals R-Y and B-Y is written into the memory 5 according to a command from the control circuit 6, and read out according to a command from the control circuit 6. The data read from the memory 5 is converted into an analog signal by the D/A converter 7, converted into a composite video signal by the modulator 8, and outputted from the composite video signal output terminal 9.

Here, the memory space when data is written to the memo 1 to 5 has the configuration shown in FIGS. 4 and 5. In FIG. 4, one field is read out at the expense of vertical resolution. In this case, the memory space is sufficient for one field, but since the two fields undergoing interlaced scanning are the same signal, the vertical resolution is halved. Furthermore, vertical jitter occurs due to the movement of the vertical center of gravity for 1/2 horizontal scanning period (hereinafter, horizontal scanning period is referred to as H) for each field. However, in FIG. 5, since the memory space is for two fields, no deterioration in vertical resolution occurs due to interlaced scanning. Furthermore, since the vertical jitter component is also corrected field by field, it is improved, but the memory space is required twice as much as in the case of FIG. 4.

Problems to be Solved by the Invention In the conventional memory space configuration described above, in the case of FIG.
Although the memory space is small, the vertical resolution is halved, and in the case of FIG. 5, the vertical resolution is improved but the memory space is large.

The present invention solves the above problem by providing a memory space for storing IH luminance signal and color difference signal data in the memory space shown in FIG. It is an object of the present invention to provide a video signal processing device that can smooth changes in data in the direction and reduce jitter occurring in the vertical direction. In order to achieve the object, the video signal processing device of the present invention has the following features: - A memory space necessary for storing the luminance signal and color difference signal data in the vertical scanning period, and the luminance signal and color difference signal data of the IH. It consists of a memory space necessary to store color difference signal data, an arithmetic circuit that performs line interpolation, and a control circuit that controls these.

Effect: With this configuration, it is possible to have data for two fields by interpolating data with the L field memory space, the IH memory space, and line interpolation, making it possible to perform pseudo-interlaced scanning. This is shown in Figure 4.

Unlike the case where the same signal is read out, there is a correlation between the data in the first field and the data in the second field, so the change in data in the vertical direction becomes smooth between fields. Furthermore, by determining each of the two fields as an odd or even field, 1
It is possible to reduce jitter between fields that occurs when fields are combined.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a video signal processing device according to an embodiment of the present invention. The operation of the video signal processing device of this embodiment will be described below.

First, the luminance signal and color difference signal data for the first horizontal scanning period in the write start field are written to the field memory 5 and simultaneously to the line memory 10. The remaining horizontal scanning period luminance signals, nine color difference signals, and evening signals are written into the field memory 5. Here, field memory 5
When writing to line memory 10 and line memory 10 simultaneously,
The address increment frequency for both memories is the same. Furthermore, the television screen has 2 fields and 1 field.
Of the screen that constitutes the screen, only one field's worth of data (luminance signal, two color difference signals) is written into the field memory 5. Therefore, when interlacing images, it is necessary to correct the data of fields not written in the field memory 5 from the data written in the same field memory 5. Here, in the present invention, a line interpolation method is used as a correction method. This is a method of interpolating the data between adjacent 2H data by taking the average of each data.

In the present invention, the luminance signal and two color difference signal data of the horizontal scanning period read from the field memory 5 and the luminance signal and two color difference signal data of the horizontal scanning period read from the line memory 10 are each halved by the dividers 11 and 12. Note that the data read from the line memory is data before IH than the data from the field memory. Then, each of the halved data is added to the adder 13. In this way, by averaging the 2H data, gaps are compensated for. Here, in order to average 2H, it is necessary to perform an IH delay, and in the present invention, the IH delay is performed using the line memory 10 as described below.

In order to use the line interpolation method, data is read from the field memory 5 and the line memory 10, respectively. At this time, the data read from the field memory 5 is
At the same time as being transferred to the divider 11, the same address as the address read from the line memory 10 is written into the line memory 10. In this way, field memory 5
By sequentially writing the read data from the field memory 5 to the line memory 10, when the IH data read from the field memory 5 is completed, all of the IH read data, luminance signal, 9 color difference signals from the field memory 5 are written to the line memory 10. complete. In this way, by storing the IH data in the line memory 10, the IH is delayed.

Next, the case where the screen is interlaced will be explained.

Fields supplemented by the line interpolation method and fields without complementation (fields based on data directly read from the field memory 5) are switched by a switch 14 for each field to form an interlaced screen. FIG. 5 displays data that contributes to screen display when interlaced scanning is performed.

The solid line portion in FIG. 5 is a screen formed by data written in the field memory 5. Furthermore, the portion indicated by the broken line is a screen formed from data supplemented by line interpolation. Interlaced display is performed by reading these two screen data alternately.

Next, other embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a block diagram of a video signal processing device according to a second embodiment of the present invention. In Figure 2,
16 is an adder that adds data from the field memory 5 and data from the line memory 10; 17 is a divider that halves the output result from the adder 16; 5 is a field memory; 10 is a line memory; 14 is a Switch, 7 is D/A
The converter and 15 are control circuits, which have the same configuration as in the first embodiment.

Using line interpolation is a method of averaging 2H data. There are two methods for this, one is to divide and then add, and the other is to add and then divide. The second embodiment uses the latter.

In this embodiment, an analog component method is used in which the composite video signal is analog-demodulated into a luminance signal and color difference signals R-Y, B-Y, and then A/D converted. Luminance signal 2 as digital signal after D conversion
Color difference signal R-Y.

Digital component method for demodulating B-Y Effects of the invention According to the invention, by providing memory space for 1 field of video signal and memory space for 18 video signals, vertical data can be distributed between fields with a smaller number of blocks. It is possible to realize a video signal processing device that can smooth changes and reduce jitter that occurs in the vertical direction.

[Brief explanation of the drawing]

FIGS. 1 and 2 show the first embodiment of the present invention. FIG. 3 is a block diagram of a video signal processing device in each of the second embodiments, FIG. 3 is a block diagram of a conventional video signal processing device, and FIGS. 4 and 5 are layout diagrams of each memory space. 5...Field memory, 6...Control circuit, 7...D/A converter, 10...
Line memory, 11゜12...Divider, 13.
...Adder. Name of agent: Patent attorney Toshio Nakao and one other person Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] Digitally processed luminance signal and color difference signal input; field memory for storing data during one vertical scanning period; line memory for storing luminance signal and color difference signal data for one horizontal scanning line; a divider that halves read data, a divider that halves read data from the line memory, an adder that adds each data from the divider, and the field memory and line memory, respectively; A video signal processing device consisting of a control circuit for controlling.