JPH01194393A - multilayer wiring board - Google Patents
multilayer wiring boardInfo
- Publication number
- JPH01194393A JPH01194393A JP16674088A JP16674088A JPH01194393A JP H01194393 A JPH01194393 A JP H01194393A JP 16674088 A JP16674088 A JP 16674088A JP 16674088 A JP16674088 A JP 16674088A JP H01194393 A JPH01194393 A JP H01194393A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- signal
- conductor
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 description 12
- 239000010408 film Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002470 thermal conductor Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分釘〕
本発明は、薄膜、厚ys混成高密度多層配線基板に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Nail] The present invention relates to a thin film, thick ys mixed high-density multilayer wiring board.
計算機等の高速化のためには、その論理素子である半導
体回路内での信号遅れを小さくするとともに、それらを
結びつける配線基板上での信号遅れ(伝搬遅延時間)を
小さくすることも必要である。最近の半導体技術の進歩
により、前者の遅れは後者のそれに匹敵するまでになり
ている。配線基板上での信号遅れを小さくするには、素
子間の距*1−短くする、すなわち高密度実装基板なう
ことになるが、このような高密度実装基板は次のような
要件を満たす必要がある。In order to increase the speed of computers, etc., it is necessary to reduce the signal delay in the semiconductor circuits that are the logic elements, and also to reduce the signal delay (propagation delay time) on the wiring board that connects them. . Due to recent advances in semiconductor technology, the delay in the former is now comparable to that in the latter. In order to reduce signal delay on a wiring board, the distance between elements *1 must be shortened, in other words, a high-density mounting board is required. Such a high-density mounting board satisfies the following requirements. There is a need.
0) 高f度配m<精細パターン)が可能。0) High f-degree pattern < fine pattern) is possible.
(2) 熱伝導性が良いこと。(2) Good thermal conductivity.
(3) 導体抵抗が低いこと。(3) Low conductor resistance.
(4) 所望の特性インピーダンスZ、(一般には5
oΩ)を得られるように、絶縁層厚さが比較的自由に指
定し得ること。(4) Desired characteristic impedance Z, (generally 5
The thickness of the insulating layer can be specified relatively freely so as to obtain 0Ω).
などである。etc.
しかし、このような要件をすべて同時に満たすことは、
困難である。例えば、フォトエツチング等でパターン形
成する従来の薄膜技術では、高密度配線は可能であるが
、配脈か細くなるために当熱導体抵抗が高くなる。導体
抵抗が高いと、信号d g、r7x(−R−t/2Z、
)で減衰し、スレッシ璽−ルド・レベルを越えないこ
とになる。ここでRは単位長当りの配線抵抗値、tは配
線長である。この抵抗値を低くするには、配線巾を広く
したり、配線の厚みを増す方法があるが、いづれも次の
ような難点がある。配線巾を広げると、同じ量の配線を
収容するために、より多層となると同時に、一定の特性
インピーダンスを得るために、絶縁j−を厚くする必要
がある。このように膜を厚くすることは薄膜技術では、
歩留りft落す方向である。又、配線そのものの厚みを
増すのも、エツチングの困難さを増し、次の絶縁層表面
の平坦度を悪くする。However, satisfying all of these requirements at the same time is
Have difficulty. For example, with conventional thin film technology in which patterns are formed by photoetching or the like, high-density wiring is possible, but because the wiring becomes thinner, the thermal conductor resistance increases. If the conductor resistance is high, the signals d g, r7x (-R-t/2Z,
) and will not exceed the threshold level. Here, R is the wiring resistance value per unit length, and t is the wiring length. In order to lower this resistance value, there are methods of widening the wiring width and increasing the thickness of the wiring, but each method has the following drawbacks. Increasing the wiring width requires more layers to accommodate the same amount of wiring, and at the same time, it is necessary to thicken the insulation j- to obtain a constant characteristic impedance. Increasing the thickness of the film in this way is achieved through thin film technology.
This is the direction in which the yield will decrease by ft. Furthermore, increasing the thickness of the wiring itself also increases the difficulty of etching and impairs the flatness of the surface of the next insulating layer.
次に厚膜技術では、膜厚を大きくし、一定の特性インピ
ーダンスを確保することは容易であるが、−層当シの配
線収容量が小さいため、きわめて多層となり焼成時の歩
留り低下等の欠点となる。Next, with thick film technology, it is easy to increase the film thickness and ensure a constant characteristic impedance, but - because the wiring capacity per layer is small, it becomes extremely multi-layered, resulting in disadvantages such as a decrease in yield during firing. becomes.
本発明の目的は、上記した従来技術の欠点をなくシ、伝
送特性を考慮した高密度多層基板を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and provide a high-density multilayer board that takes transmission characteristics into consideration.
本発明では、上記目的を達成するために、厚膜・薄膜混
成の基板を用い、薄膜での信号配線長の最大値が、厚膜
での信号配線長の最大値より小さくなるようにしている
。In order to achieve the above object, the present invention uses a thick film/thin film mixed substrate, and the maximum value of the signal wiring length in the thin film is made smaller than the maximum value of the signal wiring length in the thick film. .
第1因は、ある配線基板における配線長さの分布である
。これから配線長さは一様に分布するのではなく、長い
配線は極めて少ないことがわかる。The first factor is the distribution of wiring lengths on a certain wiring board. It can be seen from this that the wiring lengths are not uniformly distributed, and that there are very few long wirings.
又、一般にフォトエツチング等の光学的処理では形成す
るような精細配線においては、配線抵抗は厚膜抵抗にく
らべて、きわめて大きい。例えば、巾20JFA、厚さ
2j1yLの薄膜の銅配線では、その配線抵抗は、5Q
10n以上であシ、巾100JIFK厚さ10層mlD
厚膜タングステン配線の抵抗は、1Q/Cm以下になる
。すでに記したように、信号は−xp(−R−1/2・
Z。〕で減衰するため、上記の例では薄膜では、厚膜の
115の長さしか配線できない。本考案では以上述べた
事実が有効に利用されている。Furthermore, in fine wiring formed by optical processing such as photoetching, the wiring resistance is generally much higher than that of thick film resistors. For example, in a thin film copper wiring with a width of 20JFA and a thickness of 2j1yL, the wiring resistance is 5Q.
10n or more, width 100JIFK thickness 10layers mlD
The resistance of the thick film tungsten wiring becomes 1Q/Cm or less. As already noted, the signal is −xp(−R−1/2·
Z. ], so in the above example, the thin film can only be wired as long as 115 of the thick film. In the present invention, the above-mentioned facts are effectively utilized.
以下、図を用いて、本発明を具体的に説明する。 Hereinafter, the present invention will be specifically explained using the drawings.
第2図は、本発明の一実施例で、多層基板の断面図を示
すものである。1は約500μ厚のアルミナ・セラミク
ス、2はタングステン導体による電源層、3はタングス
テン導体による信号配線で通常X層、y層の対になって
いる。4はガラス、(ボリイ之ド)等による約10μm
厚の薄膜絶縁層、5は信号配線であり、アルミ、銅など
の薄膜導体層からなり、3と同様、通常X層、y層の対
となりている。3の配l#戊巾1001”でピッチは4
50 srN 、配線 4抵抗は1(VCmである。5
の配線は、巾2(1++mでピッチj ’177178
.配線抵抗は% 5Q/ctytである。今、配線での
減衰を70%まで許容すると、各々での最大配線長は、
3で約56:rl’L、 5では約7綿 となる。した
がって第1図において7 (rllJJ、下の配線を5
の層で。FIG. 2 shows a cross-sectional view of a multilayer board according to an embodiment of the present invention. Reference numeral 1 is made of alumina ceramics with a thickness of approximately 500 μm, 2 is a power supply layer made of a tungsten conductor, and 3 is a signal wiring made of a tungsten conductor, which is usually a pair of X and Y layers. 4 is approximately 10 μm made of glass, (bolioid), etc.
The thick thin film insulating layer 5 is a signal wiring, which is made of a thin film conductor layer such as aluminum or copper, and like 3, it is usually a pair of an X layer and a y layer. The pitch of 3 is 1001" and the pitch is 4.
50 srN, wiring 4 resistance is 1 (VCm.5
The wiring has a width of 2 (1++ m and a pitch of j '177178
.. The wiring resistance is %5Q/ctyt. Now, if we allow up to 70% attenuation in the wiring, the maximum wiring length for each is
3 will be about 56:rl'L, and 5 will be about 7 cotton. Therefore, in Figure 1, 7 (rllJJ, the lower wiring is 5
With layers of.
それ以上の配線″’(Sの層に配線すればよいことにな
る。もちろん、7cm以下の配+Ii!1lt−3の層
で行なってもよい。第1図の例では、総配線長さの、7
7%を5の層で配線することになる。It is sufficient to route wiring in a layer of 7 cm or less (Ii!1lt-3). ,7
7% will be wired in 5 layers.
これを、すべて、3の層で実現しようと、−層当りの配
線密度が小さいため、合計10層の信号配線層を必要と
することになる。逆に、すべてを5の層で実現すること
は、信号減衰の条件から不可能であることは明らかであ
る。Even if all of this were to be achieved with three layers, a total of 10 signal wiring layers would be required because the wiring density per layer is low. On the other hand, it is clear that it is impossible to realize all of this with five layers due to the condition of signal attenuation.
以上、述べた如く、本発明によれば、薄膜による高集化
と厚膜による低抵抗配線による高密度多層基板が高歩留
りと伝送特性を保持したまま得られることになる。As described above, according to the present invention, it is possible to obtain a high-density multilayer substrate with high integration using a thin film and low resistance wiring using a thick film while maintaining high yield and transmission characteristics.
1:アルミナセラミックへ 2.5:タングステン導体、 4:薄膜絶縁層、 5:薄膜導体層。 1: To alumina ceramic 2.5: Tungsten conductor, 4: thin film insulating layer, 5: Thin film conductor layer.
Claims (1)
れ形成された厚膜導体配線を有するセラミック基板上に
、さらに絶縁層、導体配線層を交互に形成する多層配線
基板において、信号用導体配線は光学的方法により形成
され、また光学的方法により形成された該信号用導体配
線の最大長さは、前記セラミック基板表面あるいは内部
に設けられた信号用厚膜配線導体の最大長さより短いこ
とを特徴とする多層配線基板。1. In a multilayer wiring board in which an insulating layer and a conductor wiring layer are alternately formed on a ceramic substrate having thick film conductor wiring co-fired with the substrate material on the surface or inside, the signal conductor wiring is optically The maximum length of the signal conductor wiring formed by the optical method is shorter than the maximum length of the signal thick film wiring conductor provided on or inside the ceramic substrate. Multilayer wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16674088A JPH01194393A (en) | 1988-07-06 | 1988-07-06 | multilayer wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16674088A JPH01194393A (en) | 1988-07-06 | 1988-07-06 | multilayer wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01194393A true JPH01194393A (en) | 1989-08-04 |
Family
ID=15836873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16674088A Pending JPH01194393A (en) | 1988-07-06 | 1988-07-06 | multilayer wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01194393A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7373627B2 (en) | 1999-06-25 | 2008-05-13 | Kabushiki Kaisha Toshiba | Method of designing wiring structure of semiconductor device and wiring structure designed accordingly |
-
1988
- 1988-07-06 JP JP16674088A patent/JPH01194393A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7373627B2 (en) | 1999-06-25 | 2008-05-13 | Kabushiki Kaisha Toshiba | Method of designing wiring structure of semiconductor device and wiring structure designed accordingly |
US7823114B2 (en) | 1999-06-25 | 2010-10-26 | Kabushiki Kaisha Toshiba | Method of designing wiring structure of semiconductor device and wiring structure designed accordingly |
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