JPH01189222A - Signal delaying circuit - Google Patents

Abstract

PURPOSE:To cause a design change to be efficient by preparing the number of stages of an inverter circuit on a layout in consideration for the accuracy of the design and the dispersion of a process parameter, etc., beforehand, and correcting a mask to connect the output of the inverter circuit and an external wiring. CONSTITUTION:The title circuit is composed of plural inverter circuits 3 to be connected in series, and the position of an opening 1 for a connection on the wiring to obtain an output signal 5 in an initial design is made into an electric connecting point. On the other hand, when, in a real device, the delaying quantity of the output signal 5 to an input signal 4 is measured, a value is made larger than a designed value and that the design change is needed is known, it is sufficient that a mask for a contact is corrected so as to be made into the optimum correction position of the opening for the connection for obtaining a delay time DELTAt on the design, for example, the opening for the connection indicated by 2. Respective inverter circuits in the signal delaying circuit composed of plural inverter circuits do not necessarily need to use equal circuits, equal transistors, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal delay circuit in a semiconductor integrated circuit device.

Conventional technology Fig. 3 shows a configuration in which a signal delay circuit for normal rotation of a certain input waveform is configured with an inverter circuit. This figure shows a delay circuit that was initially designed for this purpose.

The initial design value of the delay time Δt for the delayed signal a0 of the input waveform a is actually Δt when the delay time is measured after being manufactured as a device, and is often different from the target setting value Δt in the initial design. arise.

There are many possible reasons why the value at the initial design stage differs from the actual value measured after device manufacturing, but one of the main reasons is
One problem is the accuracy of estimating delay time through simulation during design. Another problem is variations or shifts in process parameters during actual device manufacturing. In the former case, usually sufficient parameter fitting
By doing this to improve accuracy, no problem will occur, but if this occurs, it will require design changes, and the mask will need to be modified to add or delete an inverter circuit to the mask that has already been created. This causes mask modification of all layers.

On the other hand, there is often a problem that deviations from the above-mentioned initial design values also occur when fluctuations or changes occur due to variations in process parameters during actual device manufacturing. This is an unavoidable problem even if circuit simulation is performed with sufficient accuracy at the initial design stage, and some countermeasure must be taken. In this case as well, it often happens that a mask that has already been created must be modified in order to modify the circuit. When such a situation occurs, conventionally, the method shown in Figure 3 (
As shown in b), if the delay time of the actual device is large, it is necessary to reduce the delay time by reducing the number of stages in the inverter circuit; As shown in FIG. 3(C), the circuit is modified to increase the delay time by adding the number of inverter circuit stages, and the design values are optimized. These circuit modifications require mask modifications, and modifications are required for almost all layers.

As mentioned above, if the value of the actual device deviates from the initial design value of the circuit delay value due to various reasons, circuit modification is required, which results in modifications such as adding or deleting an inverter circuit. . Therefore, since mask modification involves changing the Tr level, it is necessary to modify almost all layers.

Problem to be Solved by the Invention When a circuit change occurs in a signal delay circuit in a semiconductor integrated circuit device, it is possible to add or delete transistors, etc., and thereby increase the number of layers close to almost all of the layers in the already created mask. Since correction is required, there is a major problem in that the cost associated with mask correction is about the same as the original cost of the mask, even though several stages of inverter circuits are changed. In addition, since the number of layers for mask correction is large, it takes about the same amount of time as the processing time for mask creation for all layers, which is a very big problem from the point of view of design efficiency.

The present invention realizes significant cost reduction by significantly reducing the number of masks that require modification due to changes in the number of stages in an inverter circuit, and improves design efficiency by significantly shortening processing time. It is.

Means for Solving the Problems The present invention makes it possible to modify almost all levels of the mask by adding or deleting the number of inverter circuit stages when the design is changed in order to obtain the delay time of the initial design in the signal delay circuit of a semiconductor integrated circuit device. The number of stages of the -1tL inverter circuit is already prepared on the layout to eliminate variations in design accuracy and variations in process parameters, etc., without having to perform By creating a layout structure that allows the desired delay time to be obtained by modifying the mask, the number of mask layers that must be modified due to mask modification can be minimized by using only a layer. be.

The present invention uses the above-mentioned means to perform an initial design without requiring the conventional method of adding or deleting inverter circuits to perform symmetry correction across almost all layers in order to obtain a desired delay time. By modifying the contact mask by providing an opening (contact) for connection to the output of the inverter circuit that provides an output signal with the desired delay time, this can be achieved with only a small number of modified masks. .

Example FIG. 1 shows an equivalent circuit showing a first embodiment of the present invention.

FIG. 1 shows an initial design and a modified circuit diagram of a signal delay circuit. Delay time Δt for normal rotation signal with the same phase as input signal 4
This is a signal delay circuit whose purpose is to obtain an output signal of The position of the connection opening 1 becomes the electrical connection point. On the other hand, when the amount of delay of this output signal 5 with respect to the input signal 4 was measured in an actual device, it was found that the value was larger than the designed value, so it was found that a design change was required.

Therefore, the position where the connection opening was optimized and corrected in order to obtain the delay time Δt in the design is the connection opening shown in 2 in Figure 1, and the desired correction is made by correction of the contact mask. I was able to accomplish this. According to the present invention, the above-mentioned design changes are possible by providing a layout structure that can be realized by simply changing the position of the connection opening of the signal wiring in order to change the amount of delay in advance and obtain the expected phase waveform. It can be done. However, it can be seen that modification of the chip manufacturing mask due to a design change can be achieved by modifying only the mask related to the connection opening, and in cases where the number of connections is small, only the mask layer is sufficient.

A plurality of connected inverter circuits 3 shown in FIG.
It goes without saying that it may be realized by another logic circuit that logically functions as an inverter circuit. Further, the connection opening means a contact in a mask for manufacturing a device, but is not particularly limited to this as long as it corresponds to an electrical connection point in terms of logic or circuits.

FIG. 2 shows an embodiment of the tube 2 of the present invention. In this case, a signal delay circuit using a two-layer AL (aluminum)-layer PS (polysilicon) process is constructed by an inverter circuit.

21 is the second layer AL (AA), 22 is the first layer Ar, (A
I,).

24 is a diffusion layer (OD), 25 is a first layer contact (CW)
), 26-27C are second layer contacts (Cx). This second embodiment shows a specific layout structure with a logical configuration similar to the first embodiment. Reference numeral 26 in the figure indicates the opening 1 for connecting the output of the inverter to the output wiring, and indicates the position of the opening in the initial design.

However, as explained in the first embodiment, the delay time after manufacturing the actual device increased, so the design was changed and the aperture position where the optimal delay time could be obtained was changed to 2.
7 opening 1'. Therefore, as shown above, the mask modification for changing the delay time simply eliminates the opening 1 determined in the initial design in the contact mask (CX) and creates a new opening 1'. I can see that it can be achieved.

In this second embodiment, an example of a process technology for two-layer AL/-layer PS was shown, but a process using -layer AL/-layer PS, -layer AI, double-layer PS, polycide, and silicide is also described. There is no particular limitation on the use of any other process technology, such as technology or three-dimensional process technology. Further, each inverter circuit in a signal delay circuit configured with a plurality of inverter circuits does not necessarily need to use the same circuit, the same transistor, or the like.

Effects of the Invention As described above, according to the present invention, when changing the amount of delay in a signal delay circuit, there is no need to make a large change in the mask due to the addition or deletion of a transistor, etc., or to make many mask corrections, which is the least possible. In some cases, only one contact mask needs to be modified. Therefore, firstly, it is possible to significantly reduce the number of man-hours involved in changing masks, and it is possible to realize extremely efficient and time-saving design changes. Second, because the number of mask corrections required for design changes is small, design costs can be significantly reduced. Third
In addition, it is possible to efficiently and flexibly respond to changes in process parameters or the need for design changes such as improvement of simulation accuracy in design.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram including an initial design of a signal delay circuit and connection openings after modification, illustrating an embodiment of a tube 1 of the present invention, and FIG. 2 is a circuit diagram of a signal delay circuit illustrating an embodiment of a tube 2 of the present invention. The layout diagram, FIG. 3, is a circuit diagram of a conventional signal delay circuit. 1.2... Connection opening, 3... Inverter circuit, 4... Input signal, 5... Output signal. Name of agent: Patent attorney Toshio Nakao and 1 other person 6 pages
-n.

Claims (1)

[Claims] A semiconductor integrated circuit device has a plurality of inverter circuits connected in series, and any one output among the plurality of outputs of the inverter circuit can be selected only by selectively installing a connection opening that is an electrical connection point. Characteristic signal delay circuit.