JPH0384951A - Layout design of integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a layout design method which can set the propagation time of a signal within a prescribed limit and which is suitable for automatization by a method wherein, regarding a signal propagation route into which a macrocell for delay is inserted before a layout pattern is generated, a pattern of a macrocell is replaced with a pattern of other macrocells for delay after the pattern is generated. CONSTITUTION:Elements 5 for delay are inserted between discrete latches 3 and a buffer 2 directly before them, and a layout pattern is generated. A whole layout pattern is generated by using an automatic arrangement interconnection program; after that, the signal propagation delay time in a route leading to the discrete latches 3 from a clock signal input terminal 1 is computed from the layout pattern. Then, while the delay time of a route whose propagation delay time of a chock signal is longest is used as a reference, a difference between the reference delay time and the delay time in the route is found regarding the elements 5 for delay included in routes other than that; the time to which the delay time of a pattern of the elements for delay is added is found. A pattern whose delay time is longest within a range not exceeding the time is found and replaced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention aims to suppress the difference between the maximum value and the minimum value of signal propagation delay time in a plurality of signal propagation meridians in an integrated circuit to a desired value or less. The present invention relates to a layout design method for integrated circuits that makes it possible to design the layout of an integrated circuit.

[Prior art J] In a synchronous circuit controlled by a clock signal, variations in the delay time until the clock signal propagates to the clock terminal of each element (hereinafter referred to as clock skew) affect the operating speed of the entire circuit. Therefore, in designing circuits that require high-speed operation, it is necessary to reduce clock skew.

The propagation delay time of a signal is the sum of the delay time in the elements included in the signal propagation path and the delay time in the wiring between the elements, whereas the former has a unique value for each element. The latter depends on the wiring layout pattern, so when designing the layout of an integrated circuit where it is necessary to suppress the risk skew to below a limit value, it is necessary to consider the variation in delay time while designing the clock signal line. The wiring pattern must be determined.

Conventionally, the following methods have been used in layout design of semiconductor integrated circuits where clock skew must be kept below a limit value.

One method is to manually modify the results of automatic placement and routing by a computer. FIG. 4 is an example showing a portion of the layout and wiring results of the gate array.

The clock signal input to the clock signal input terminal 9 is I
The signal is distributed through 10 buffers 10 and several stages of buffers 11, and is supplied to the clock signal input terminal 13 of each latch 12. At this time, the signal propagation delay time from the clock signal input terminal 9 to each latch to the clock signal input terminal 13 is determined from the delay time at each buffer 11 and the wiring route pattern between each element.

If the skew in each latch 12'1 exceeds the allowable value, use the empty area and change the wiring meridian by changing the position of the element as shown in A, or change the wiring as shown in B. By directly changing the route, manual correction is performed so that the clock skew is below the allowable value.

Another method is to provide a part of the wiring pattern of the clock signal line on the chip in advance and press the button. Fifth
The figure shows an example. The area on the semiconductor substrate 14 is divided into four blocks 15, and the clock signal input terminal 1 is divided into four blocks 15.
The wiring pattern 18 of the micro clock signal line is arranged so that the delay time for the clock signal supplied to the block 6 to reach the clock signal distribution circuit 17 in each block 15 is equal.
Place it on the chip in advance. Layout design is performed for such a chip. As a result, the clock
Since the skew is equal to the variation in the propagation delay time of the clock signal within each block 12, it is smaller than when designing the layout without providing a wiring pattern for the clock signal line in advance.

[Problem to be Solved by the Invention 1] Among the conventional methods, the method of performing manual correction after automatic placement and wiring has the drawback of increasing the design period and design cost.

In addition, in the other method, in which a part of the wiring pattern for the clock signal line is provided on the chip in advance, the fixed pattern is always provided on the chip, so area is wasted in cases where there are only a small number of latches. It has the disadvantage of becoming

The present invention has been made to solve the above-mentioned problems, and aims to provide a layout design method that makes it possible to keep the signal propagation delay time within predetermined limits and is suitable for automation. purpose.

[Means to solve the problem]

The integrated circuit layout design method according to the present invention requires that a plurality of signal propagation paths be avoided, and that the difference between the maximum and minimum signal propagation delay times in each path be within an allowable range. A layout design method for an integrated circuit that includes one or more signal propagation paths.
The step of preparing a plurality of macro cells with delay functions that have the same size and input/output terminal positions and different delay times, and one of the delay macro cells is described in the inter-element connection information of the circuit. A step of inserting into the connection relationship between the terminal terminal of all the paths included in the above signal propagation path group and the terminal immediately before it, and as a result, generating a layout pattern according to the changed inter-element connection information. step, determining the signal propagation delay time on each route from the layout pattern, determining a reference route for each signal propagation route group, and determining the reference route for each of the other routes in the group. The step of calculating the difference in signal propagation delay time between the , the delay macros 7 to 1 are included.
and replacing the delay macrocell pattern with another delay macrocell pattern having a delay time including a correction value for the route.

[Effect]

According to the present invention, before a layout pattern is generated, a layout pattern e is generated for a signal propagation path in which a delay macro cell is inserted in the inter-element connection information, and after that, a pattern of the delay macro cell is created using the same pattern prepared in advance. By replacing the pattern with another delay macro cell pattern that has input/output terminals in the same size and position, the signal propagation delay time can be changed without changing the layout pattern of other signal lines after the layout pattern is generated. I can do it. Therefore,
It is also easy to adjust the difference in delay time of signal propagation paths in which delay macro cells are inserted.

[Embodiment J] Hereinafter, as an embodiment of the present invention, an automatic layout design algorithm for a gate array that makes it possible to keep the clock skew within a certain limit will be described with reference to the drawings.

FIGS. 1 and 2) are part of an example of a logic diagram of a circuit to be designed, and only show a clock signal propagation path.

The clock signal is input to the clock signal input terminal l, distributed using several stages of buffers 2, and supplied to the clock signal input terminal 4 of each latch 3. At this time, the propagation delay time of the clock signal to each latch is as follows. , is expressed as the sum of the delay time in the buffer and the propagation delay time in the wiring route, but variations occur in the delay time due to differences in the wiring pattern up to each latch 3.

For such a circuit, the logic diagram is changed as shown in FIG. 1(b), and a delay element 5 is inserted between each latch 3 and the buffer 2 immediately preceding it. A layout pattern is generated based on such a logical diagram.

As delay elements, cells as shown in FIGS. 2(a) to (ff) are prepared. These circuits are constructed by arranging several elements (OR circuits 6 in this case) having a fixed delay time in series, and have the same size, the position of the input terminal 7, and the position of the output terminal 8. However, in the logic diagram, it is assumed that only one type of delay element is prepared, and the cell pattern shown in FIG. 2 is generated.

After the entire layout pattern is generated using an automatic placement and wiring program, the signal propagation delay time in the path from the clock signal input terminal 1 to each latch 3 is calculated from the layout pattern.

Next, using the delay time of the path with the longest propagation delay time of the clock signal as a reference, for each of the delay elements 5 included in the other paths, the reference delay time and the delay time on that path are calculated. Find the difference between them and apply the pattern of the delay element (
Find the time including the delay time in a). Figure 2 (a) shows the pattern with the longest delay time within the range that does not exceed that time.
~ (f') and replace it with (a).

Through the above processing, the clock skew can be reduced to less than the difference in delay time of each delay element pattern.

A flowchart of the entire process is shown in FIG.

Note that the delay element does not have to be a series of elements with a fixed delay time, but it is sufficient as long as they have different delay times and have the same size and input/output terminal positions.
There is also a method of using elements that have the same logic but different characteristics, such as driving ability, that affect signal propagation delay time. For example, Figure 2
Similar to (b).

Even when an R element is used, the load driving ability can be changed by making the oR element WII or each transistor a plurality of transistors whose source, gate, and drain terminals are connected to each other. By preparing multiple cells with different numbers of transistors connected in parallel, the same single stage. The R element can also be used as a delay element because cells with different delay times can be formed.

【Effect of the invention〕

As described above, according to the present invention, the layout design of an integrated circuit that requires the variation in signal propagation delay time to be kept below a certain limit can be achieved by changing the connection information between elements and by changing the layout pattern. This can be achieved by simply adding the processes of calculating the delay time from and replacing the cell layout pattern to the conventional layout design process. Therefore, it can be applied to automatic layout design without increasing the design period or cost.

[Brief explanation of drawings]

FIG. 1 is a logic diagram showing an embodiment of the present invention, FIG. 2 is a diagram schematically showing an example of an internal circuit of a delay element, and FIG. 3 is a flowchart for automatic layout design of a gate array. Figure 4 is a diagram for explaining a method for manually correcting the placement and wiring results, which is one of the conventional methods. FIG. 2 is a diagram showing an example of a wiring pattern used in a method of writing a part of the wiring pattern on a chip in advance. In the figure, 1 is a clock signal input terminal, 2 is a buffer, 3 is a latch, 4 is a latch clock terminal, 5 is a delay element,
6 constitutes a delay element. R circuit, 7 is the input terminal of the delay element, 8 is the output terminal of the delay element, 9 is the clock signal input terminal, IO is the I10 buffer, 11 is the buffer,
12 is a latch, 13 is a clock terminal of the latch, 14 is a substrate of a semiconductor integrated circuit, 15 is a block of divided placement and wiring area, 16 is a clock input terminal, 17 is a clock signal distribution circuit, and 18 is a clock provided in advance. This is the wiring pattern of the signal line. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A signal that includes a plurality of signal propagation paths as elements and requires that the difference between the maximum value and the minimum value of the signal propagation delay time in each signal propagation path be within a desired value. In the layout design of an integrated circuit that includes one or more propagation path groups, prepare in advance a plurality of delay macro cells that function as delay elements, have the same size and input/output terminal positions, and each have different delay times. For all elements of the signal propagation path in the stage and inter-element connection information of the integrated circuit, disconnect the connection relationship between the terminal corresponding to the end point of the path and other terminals in the path connected to it. and changing inter-element connection information by inserting the delay macrocell in between; generating layout pattern information based on the changed inter-element connection information; and from the generated layout pattern information, calculating a signal propagation delay time in each signal propagation path in the group of signal propagation paths; For each signal propagation path, the difference in signal propagation delay time from the reference signal propagation path is calculated, and a correction value is calculated to make the difference less than a desired value. Each macro cell has a delay time corresponding to the sum of the delay time of the delay macro cell and the correction value of the signal propagation delay time for the signal propagation path that includes the delay macro cell calculated in the previous step. A method for designing a layout of an integrated circuit, comprising the steps of exchanging with another delay macrocell and changing layout pattern information.