JPH01188042A - Frame synchronizing system and equipment - Google Patents

Abstract

PURPOSE:To make an asynchronous consecutive time zero substantially by constituting the equipment by a hunting means retrieving a frame synchronizing pattern and a frame signal supply means applying synchronizing control based on the internal state of the hunting means at the discrimination of out of syn chronism. CONSTITUTION:Suppose that a coincidence pulse going to appear in an output signal (a) at a time B in the synchronizing state is delayed till a time C, then a frame pulse appears in output signals (b), (c) at the time B, '0' appears in the output signal (d) and '1' appears in output signals (e), (f). The internal value of a synchronization protection counter 107 is expressed as n=1 and a clock control gate 108 is closed. Then a frame counter 110 starts hunting, a frame pattern detection circuit 103 detects a frame synchronizing pattern at a time C to open the clock control gate 108. This is equivalent to that the frame counter 110 ensures the frame synchronization and then a frame pulse appears in the output signals a, c succeedingly in the same phase.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization system, and particularly to a frame synchronization system used in digital transmission systems such as backbone transmission systems, public networks, and subscriber systems.

[Conventional technology]

In time-division multiplexed digital transmission systems, frame synchronization is being considered as a method to ensure and maintain frame synchronization.

FIG. 5 is a circuit block diagram showing an example of a conventional frame synchronization method used in the digital transmission system. The figure shows a synchronous mining circuit using the reset method.
1 is a data input line, 302 is a clock input line, 303 is a frame pattern detection circuit, 304 is a coincidence gate, 30
5 is a mismatch gate, 307 is a synchronization protection counter, 308
is a clock control gate, and 310 is a frame counter. Here, it is assumed that the clock signal input from the clock input line 302 and the data signal input from the data input line 301 have the same repetition period and ensure pit synchronization. Regarding this technology, see "Practical use of @400M multiplex converter" published by Kohei Otake et al. in Research and Practical Application Report, Vol. 25, No. 1, 1976, or
A study on the design method of a one-frame synchronization protection circuit published by Rikio Maruta in the Journal of the Institute of Electronics and Communication Engineers in 1978.”
It is described in.

Frame pattern detection circuit 303 is data input M301
Detects the frame synchronization pattern supplied from
The results are sent to match gate 304 and mismatch gate 305. The frame counter 310 counts the black and red signals inputted from the black and white input lines 302 via the black and white control gates 308, and outputs frame pulses in synchronization with the frame synchronization pattern. Additionally, this frame pulse is provided to match gate 304 and mismatch gate 305. The synchronization protection counter 307 is a counter for maintaining the synchronization state even if an error occurs in the frame pattern despite the synchronization state, and is usually implemented as a previous protection counter.

The figure shows an example where the number of forward protection stages is N = 3), with consecutive 3
It is determined that an out-of-synchronization state has occurred for the first time when no matching frame pattern is detected between frames. The output of the coincidence gate 304 becomes a reset signal for the internal state of the synchronization protection counter 307, and the mismatch gate 305 becomes a clock input signal of the synchronization protection counter 307. The clock control gate 308 supplies a clock signal input from the clock input line 302 to the frame counter 310 .

In the following, the synchronous state and the asynchronous state will be explained in this order.

In the synchronous state, the output of the coincidence gate 304 is a frame pulse, and the output of the mismatch gate 305 is "0".

The synchronization protection counter 307 is reset every frame period, and its output becomes 10". At this time, since the clock control gate 308 is open, the clock and clock signals input from the clock input line 302 are The signal is supplied as is to the frame counter 310.Frame counter 3
10 generates a frame pulse according to this input clock signal and confirms that frame synchronization is maintained.

On the other hand, in the asynchronous state, even if the 7-frame pattern detection circuit 303 detects a frame pulse, the coincidence gate 303
4 becomes "0", and a frame pulse is output from the mismatch gate 305.

When frame pulses are supplied from the mismatch gate 305 three times in succession, the output of the synchronization protection counter 307 becomes "1" and the clock control gate 308 is closed. Therefore, the clock signal from the clock input line 302 is no longer supplied to the frame counter 310ζ. This closed state of the clock control gate 308 continues until the frame pattern detection circuit 303 detects a frame synchronization pattern.

In other words, it becomes a state in which the frame synchronization pattern is not included. When the frame pattern detection circuit 303 detects a frame synchronization pattern and its output becomes ``1'',
Subsequently, the output of the coincidence gate 304 becomes high, and the internal state of the synchronization protection counter 307 is reset. At the same time, the clock control gate 308 becomes open, and the clock signal is again supplied to the frame counter 310ζ to ensure frame synchronization.

In the manner described above, it is possible to confirm that frame synchronization is maintained and to detect a pattern for frame synchronization.

[Problem that the invention seeks to solve]

In the conventional frame synchronization method shown in FIG. 5, hunting for a frame synchronization pattern is started only after the synchronization protection counter counts up, and in the worst case, hunting for one frame length is required. For this reason, in a high-speed or long-frame transmission system, a large amount of information is lost, and a method for recovering synchronization faster is required.

An object of the present invention is to provide a frame synchronization method that solves these problems and can reduce the asynchronous duration to substantially zero.

[Means for solving problems]

The frame synchronization method of the first invention is a time division multiplexing digital transmission system in which a frame synchronization pattern is superimposed, and includes a hunting means for searching for the frame synchronization pattern, and a frame synchronization method based on the internal state of the hunting means when determining out-of-synchronization. It is characterized by comprising frame signal supply means that performs synchronization control.

Further, the frame synchronization device of the second invention includes a frame pattern detection circuit that detects a frame synchronization pattern from a received signal, a first frame counter for synchronization hunting that counts a received clock, and a first frame counter that counts the received clock. a second frame counter that generates a frame signal;
a first gate that receives a frame signal output from the second frame counter and a frame synchronization signal output from the frame pattern detection circuit and outputs a coincidence signal when both signals are in phase; a second gate that receives a signal and outputs a first mismatch signal when the two signals have different phases; a frame signal output from the first frame counter; and a frame synchronization signal output from the frame pattern detection circuit. a third gate that outputs a second mismatch signal when the phases of both signals are different; and a third gate that is initialized by the match signal and counts the number of the first mismatch signals; a synchronization counter that supplies an out-of-synchronization signal to the second frame counter when the numerical value exceeds a predetermined number; and a synchronization counter that controls the counting operation of the first frame counter while the second mismatch signal is being supplied. The second frame counter stores the counted value of the first frame counter when the out-of-synchronization signal is applied.

〔Example〕

Next, the present invention will be explained with reference to FIGS. 1 to 4.

FIG. 1 is a block diagram showing an embodiment of the frame synchronization method and device of the present invention, FIG. 2 is a time chart showing the timing of each part signal in FIG. gl of the frame pattern detection circuit in the figure, %2
FIG. 2 is a circuit diagram showing an example.

In Figure 1, a * b e C+ d @ e
@f * g * h, the alphabetical characters i indicate the signal positions of the timing waveforms with the same names in FIG. 2, 101 is the data input line, 102 is the clock input line, 103 is the frame pattern detection circuit, 104 is the coincidence gate, 105.106
is a mismatch gate, 107 is a synchronization protection counter, 108 is a clock control gate, and 109 and 110 are frame counters. Here, it is assumed that the clock signal input from the clock input line 102 and the data signal input from the data input line 101 have the same repetition period and bit synchronization is ensured.

The frame pattern detection circuit 103 is connected to the data input line 101
Detects the frame synchronization pattern supplied from
The result is 11 sentence gate 104 and mismatch gate 105.
, 106. The frame counter 109 counts the clock signal input from the clock input 4102 and outputs a frame pulse in synchronization with a frame synchronization pattern. Furthermore, this frame pulse is supplied to the first gate 104 and the non-coincidence gate 105. ! Further, the frame counter 110 counts the clock signal inputted from the clock generator 102 via the clock control game 108, and outputs a frame pulse in synchronization with the frame synchronization pattern. Furthermore, this frame pulse is
is supplied to As described later, the frame counter 10
A frame counter 9 is used for maintaining synchronization, and a frame counter 110 is used as a hunting counter. The synchronization protection counter 107 is a forward protection counter, and in FIG. 4, the forward protection stage 0N=3. The output of the synchronization protection counter 107 becomes the input of the frame counter 109, and according to this control signal, the frame counter 109 changes to frame counter 1.
Load the count value of 10. The output of the coincidence gate 104 becomes a reset signal for the internal state of the synchronization protection counter 107, and the output of the mismatch gate 105 becomes a clock input signal of the synchronization protection counter 107. Clock control gate 108 supplies a clock signal input from clock input line 102 to frame counter 110 .

In the timing chart of FIG. 2, a is the output signal of the frame pattern detection circuit 103, b is the output signal of the frame counter 109, C is the output signal of the frame counter 110, d is the output signal of the match gate 104, and e is the mismatch gate. 105, f is the output signal of the mismatch gate 106, g is the output signal of the synchronization protection counter 107, h is the output signal of the clock control gate 108, and i is the input signal of the clock input line 102. It shows.

In FIG. 2, it is assumed that time A is the start time of this timing chart, and frame synchronization is ensured at this time A. In other words, the frame counter 109,
The frame pulse output from 110 and the frame synchronization pattern appear in the same phase, the frame pulse is output as the output signal d, and the synchronization protection counter 107 is reset (internal value n=0). Also, the output signal eef+g at this time
is ``0'', the clock control gate 108 is in an open state, and a clock signal is supplied to the frame counter 110.

Next, suppose that an asynchronous state occurs at time B due to some factor. In other words, it is assumed that a coincidence pulse should appear in the output signal a at time B in a synchronous state, but is delayed until time C. At this time, a frame pulse appears at time B in the output signals S and C, "0" appears in the output signal d, and "1" appears in the output signals e and f. At the same time, the internal value of the synchronization protection counter 107 is n. =1, the clock control gate 108 is closed.As a result, the frame counter 109 continues to be supplied with the clock signal i, but the frame counter 110 is no longer supplied with the clock signal 1.In other words, the frame counter 109 continues to be supplied with the clock signal i. The counter 109 continues to hold its current state (synchronization protection state), but the frame counter 110 starts hunting.Time C
The frame pattern detection circuit 103 detects a frame synchronization pattern and opens the clock control game 108. This corresponds to the frame counter 110 securing frame synchronization, and frame pulses will appear in the same phase in the output signals a and C thereafter. The frame counter 109 maintains the state before time A until the frame clock signal is continuously supplied to the synchronization protection counter 107 three times and the internal value becomes n=3. And the internal value is n=
3 (time D), the count value of the frame counter 110 is loaded into the frame counter 109, and synchronization is promptly ensured.

FIG. 3 shows a frame pattern detection circuit for a frame in which an 8-bit frame synchronization pattern is continuously (intensively) inserted into the data signal input from the data input line 101 (shown in FIG. 1), and FIG. is the data manpower g1
This is an example of the configuration of a frame pattern detection circuit for a frame in which an 8-bit frame synchronization pattern is dispersed and inserted at 1-bit intervals into a data signal input from 01. In FIGS. 3 and 4, 401 and 501 are data input lines, 402 and 502 are clock input lines, and 40
3 is an 8-bit shift register, 503 is a 1 frame length (IX8 bits) shift register, 4111 to 411
g, 5111 to 5118 are exclusive OR (EX-OR
) gates, 4121-4122° 5121-5122 are OR gates, 413, 513 are NOR gates, 4141
~414g and 514*~514g are frame synchronization pattern setting terminals, and 415 and 515 are frame synchronization pattern detection signal terminals. In FIG. 3, each bit output of the 8-bit shift register 403 is output from EX to OR gate 4.
It becomes the input signal of 4118 to 111. Register of shift register 403 for each bit set by frame synchronization pattern setting terminals 4141 to 4148! When the patterns match, the frame synchronization pattern detection signal terminal 4151 outputs I", and the frame synchronization pattern 7 is detected. In addition, in FIG. 4, the frame length shift register 503 outputs I". EX-OR gate 511 for each bit
This becomes the input signal for s-511s.

When each bit set by frame synchronization pattern setting terminals 5141 to 5148 matches the value supplied from shift register 503, 11" is output to frame synchronization pattern detection signal terminal 515, and a frame synchronization pattern is detected. be done.

〔Effect of the invention〕

As explained above, the present invention does not depend on the frame structure of the input digital signal (centralized arrangement/distributed arrangement of frame synchronization patterns), but has a structure that simultaneously includes a synchronization holding counter and a hunting counter. As a result, synchronization can be quickly ensured as soon as the asynchronous state is determined, and as a result, the asynchronous duration time can be reduced to substantially zero. The frame synchronization method of the present invention relates to a timing method in a digital transmission system, and is expected to be applied to digital transmission systems with even higher speeds and larger capacities in the future. IC and LSI can be easily achieved by using the integration technology.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the frame synchronization method and device of the present invention, FIG. 2 is a time chart showing the timing of each part signal in FIG. 1, and FIGS. 3 and 4 are the same as in FIG. The first part of the frame pattern detection circuit. FIG. 5 is a circuit diagram showing a second example, and FIG. 5 is a circuit block diagram showing an example of a conventional frame synchronization method. 101... Data input line, 1o2... Clock input line, 103... Frame pattern detection circuit, 104... Matching), 105, 106
...Discordance gate, 107 ... Synchronous protection counter, 108 ... Clock control gate,
109.110...Frame counter, 301
. . . Data input line, 302 . . . Sentry clock input line, 3o3 . . . frame pattern detection circuit, 30
4... Match gate, 305... Mismatch gate, 307... Synchronous protection counter, 308
・・・・・・Tahi ivy control gate, 31°・・・・・・
Frame counter, 401, 501---Data input line, 402.502...Clock input line, 4
03...8-bit shift register, 5o3.
...1 frame length shift register %4111~
4111° to 5111 5118... Exclusive OR (EX-OR) gate, 4121 to 4122, 512
1S5122...OR gate, 413,513
・Old...NOR gate, 414 lS414 g +
5141-5148... Frame synchronization pattern setting terminal, 415, 515... Frame synchronization pattern detection signal terminal. Agent Patent Attorney Susumu Uchihara d-o (J'O [F] + 6
〉Ward C (Fig. 3 Struggle Signal Child Fig. 4) 1 Mi Doi Blind No. Funushima Prefecture

Claims (2)

[Claims] (1) In a time division multiplex digital transmission system in which a frame synchronization pattern is superimposed, a hunting means for searching for the frame synchronization pattern and a frame signal supply for performing synchronization control based on the internal state of the hunting means when determining out-of-synchronization. A frame synchronization method characterized by comprising means. (2) A frame pattern detection circuit that detects a frame synchronization pattern from a received signal, a first frame counter for synchronization hunting that counts received clocks, and a second frame that counts the received clocks and generates a frame signal. a counter; a first gate that receives a frame signal output from the second frame counter and a frame synchronization signal output from the frame pattern detection circuit and outputs a coincidence signal when both signals are in phase; a second gate which receives both of the above signals and outputs a first mismatch signal when the phases of the two signals are different; and a frame signal output from the first frame counter and the frame pattern detection circuit. a third gate that receives a frame synchronization signal and outputs a second mismatch signal when the phases of both signals are different; and a third gate that is initialized by the match signal and counts the number of the first mismatch signals; When the numerical value exceeds a predetermined number, an out-of-synchronization signal is sent to the second
and a fourth gate that stops the counting operation of the first frame counter while the second discrepancy signal is supplied, and the second frame counter A frame synchronization device, characterized in that a count value of the first frame counter is stored when the out-of-synchronization signal is applied.