JPH01184158A - Character processing circuit - Google Patents

Abstract

PURPOSE:To shorten a stand-by time by effectively using an LSI for character processing and to increase the processing speed of character data, by doubly providing a character data buffer and an image data buffer and changing over both of them by a change-over means before use. CONSTITUTION:Two character data buffers 11A, 11B are provided on an input side and a change-over switch 17 is provided between both buffers. Two image data buffers 14A, 14B are also provided on an output side and a change-over switch 18 is provided between both buffers. The change-over switches 17, 18 respectively have two switches SW1, SW2 and two switches SW3, SW4 and the change-over switch 18 changes over contacts P1, P2 and contacts P3, P4 respectively. Character data D is alternately written in either one of the character data buffers 11A, 11B from a CPU bus 5 in predetermined timing by the change-over switch 17. After the finish of writing, the written character data D is read on a character processing LSI and the processed character data D' prepared by data processing is alternately written in either one of the image data buffers 14A, 14B in predetermined timing by the change-over switch 18. After finish of writing, the written processed character data D' is transmitted to an image bus 16.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION (Industrial Field of Application) The present invention relates to a character processing circuit used in a printing device such as a phototypesetting device or a laser typesetting device.

(Prior Art) Conventionally, character processing circuits have been widely used in printing devices such as phototypesetting devices and laser typesetting devices.

FIG. 3 shows a general block configuration of such a character processing circuit. In other words, the character processing circuit has CP on the input side.
It has a U bus 15 and an image bus 16 on the output side. Then, the character data MD sent from the CPU bus 15 is written via the changeover switch IO and is read out from the character data buffer 11 for temporary storage. The processed character data MD is processed to create processed character data MD.
It is equipped with a character processing LSI 12 for creating character data MD', and an image data buffer 14 for writing and temporarily storing processed character data MD' through a changeover switch 1.3. The changeover switches 10 and 13 are electronic analog switches (mechanical switches such as reed switches are also acceptable), and both are controlled by a control means (not shown) such as a CPU. Contact point P10. pH and PI3. It has PI3.

When the contact of the changeover switch 10 is <Plo as shown in the figure, the character data MD is fetched from the CPU bus 15 and written to the character data buffer 11, and when the writing is completed, the contact of the changeover switch 10 is is changed to pH, and the written character data MD is transferred to the character processing LSI 1.
2. Character processing LSI 12
The character processing data MD' is transferred to the image data buffer 14.
When writing to , the control means switches the changeover switch 13 contact P
12, and when writing is completed, switch 1
By switching the contact 3 to PI3 as shown in the figure, the written processed character data MD' is transferred to the image bus 16.

The operation of this configuration will be described with reference to the data timing charts shown in FIGS. 4(A) to 4(E).

Character data MDIO to MDn are sequentially transferred to the CPU bus 15 at the timing shown in FIG.
When switching to , character data MDIO is written to the character data buffer 11 at the □ timing shown in FIG. When writing of character data MDIO is completed (time TI
), the contact of the changeover switch lO is switched from PIO to pH, and the changeover switch lO is switched from the character data buffer 11 to the changeover switch lO.
The character data M is sent via O at the timing shown in (C) in the same figure.
DIO is input to the character processing LSI 12 and data is processed. In addition, the changeover switch 13 is set at the processing start time TI.
is switched to contact P12, and the character processing LSI
Processed character data MD created by data processing in step 12
IO' is written into the image data buffer 14 via the switching means 13 at the timing shown in FIG. When writing of processed character data MDIO° is completed (time T2
), the contact of the changeover switch 13 is switched to PI3, and the processed character data MO is transferred from the image data buffer 14 through the changeover switch 13 at the timing shown in FIG.
IO' is transferred to the image bus 16. Hereinafter, the character data MDII, MD12s=, MDn are also processed in the same manner as described above, and the processed character data MDI 1°, MD
12', -, MDn' are output from the image bus 16.

- (Problem to be solved by the invention) However, as shown in FIG. 4(C), the character processing circuit described above has the drawback that the waiting time of the character processing LSI 12 is long, and therefore it is difficult to speed up character data processing. The problem was that it was difficult.

This invention was made from the above-mentioned circumstances,
SUMMARY OF THE INVENTION An object of the present invention is to provide a character processing circuit that takes less time to process character data and can handle higher speeds.

Structure of the invention; (Means for solving evaluation i) □ This invention inputs character data via a CPU bus,
The above object of the present invention relates to a character processing circuit that processes data in a character data processing means and then outputs processed character data via an image bus. a first and second character data buffer for storing and switching writing of the character data to the first or second character data buffer and switching reading to the character data processing means;
switching means, first and second image data buffers for temporarily storing the processed character data, and writing of the processed character data into the first or second image data buffer. This is achieved by providing a second switching means for switching the image bus and switching the readout to the image bus, and a control means for controlling switching between the first and second switching means.

(Function) In the character processing circuit of the present invention, character data is written from the CPU bus into either the first or second character data buffer alternately at a predetermined timing by the first switching means, and the writing of character data is performed. When finished, the first or second
reads the character data written in the character data buffer to the character data processing means (character processing LSI),
Writing the processed character data created by data processing by the character data processing means into either the first or second image data buffer alternately at a predetermined timing by the second switching means, and writing the character processing data. When the processing is completed, the processed character data written in the first or second image data buffer is transferred to the image bus, thereby increasing the speed of character data processing.

(Embodiment) FIG. 1 shows an example of a block configuration of a character processing circuit of the present invention in correspondence with FIG. 3.

This character processing circuit has two character data buffers IIA and IIB on the input end, and two image data buffers +4A and 14B on the output side, and between character data buffer II and IIB. A changeover switch 17 is provided between the image data buffers 14A and 14B, and a changeover switch 18 is provided between the image data buffers 14A and 14B. The changeover switches 17 and 18 are both electronic analog switches (or mechanical switches), and the changeover switch 17 is two switches SWI that can change over contacts P1 and P2, respectively.

SW2, and the changeover switch 18 includes two switches SW3.SW2 that can switch contacts P3 and P4, respectively. It has SW4.

In such a configuration, its operation is shown in FIGS.
G) This will be explained with reference to the timing chart of the data shown in FIG.

Character data Di to Dn as shown in FIG. 2(A) are continuously transferred to the CPU bus 15. First, at time TO, switch SW1 of the selector switch 17 is set to contact P1, and switch SW2 is set to contact P1. When the contact point P2 is switched, the character data D1 is written to the character data buffer II at the timing shown in CB) in the same figure. When writing of the character data D1 is completed (time T1), switch SWI of the changeover switch 17 is set to contact P2, and switch SW2 is set to contact P2.
Switch to 1. As a result, the next character data D is sent from the CPU bus 15 at timing time T1 shown in FIG.
2 is written to the character data buffer IIB, and
As shown in FIG. 3D, the character data Di written in the character data buffer IIA is transferred to the character processing LSI 12 via the changeover switch 17 and processed. At this time, switch SW3 of changeover switch 18 is switched to contact P3, and switch SW4 is switched to contact P4. Processed character data D1' created by data processing by the character processing LSI 12 is transferred to the switch SW of the changeover switch 18.
3 to the image data buffer 14A at the timing shown in FIG. Furthermore, at this timing time Tl, as shown in FIG.
12 and processed. Processed character data D1°
When writing to the image data buffer 14A is completed (time T2), the switch SW3 of the changeover switch 18 is switched to the contact P4, and the switch SW4 is switched to the contact P4.
3, and the processed character data D1' is transferred from the image data buffer 14A to the image bus 16 via the changeover switch 18 at the timing shown in FIG.

Also, at this timing time T2, as shown in FIG. 148. When writing of the processed character data D2° into the image data buffer 14B is completed (time T3), the changeover switches 17 and 18 are switched, and the image data is transferred from the image data buffer 14B via the changeover switch 18 (see FIG. The processed character data D2° is transferred to the image bus 16 at timing time T3 shown in G).

Below, character data D3. D4. ..., Dn are also stored and processed in the same manner as described above, and the processed character data D3°, D4°, ..., Dn' are transferred to the image bus 16.

Therefore, character data Di, D2 . .
It can be transferred continuously as in G).

Note that in the above example, the image data buffers 14A, 1
Although the processed character data D° is written to 4B by switching alternately for each character processing, it is also possible to switch only the character data buffers IIA and IIB using the changeover switch 17 to perform character processing. .

In addition, the processed character data D" is stored in the image data buffer 14.
After writing to image buffer 14A and 14B for the number of times,
, 111B may be switched by the changeover switch 18 so that they are simultaneously read out from the image bus 16.

Effect of the invention.

In the character processing circuit of the present invention, the buffer for character data and the buffer for image data are provided in duplicate, and these are switched and used by the switching means, so that the character processing LSI can be effectively used and This has the effect of reducing time and speeding up character data processing.

FIG. 1 is a diagram showing an example of the block configuration of the character processing circuit of the present invention, FIG. 2 is a timing chart showing an example of its operation, FIG. 3 is a diagram showing the block configuration of a conventional character processing circuit, and FIG. is the timing chart.

10.13. ．． 17, 18... changeover switch, 11.
IIA, 11B...Character data buffer, 12...
・Character processing LSI, 14°148, 14B...Buffer for image data.

Applicant's agent: Yu Yasugata 3 Procedural amendment ■, Case indication 1988 Patent Application No. 8051 2, Invention title character part 3! ! Relationship with Circuit 3 Amendment Case Patent Applicant (520) Fuji Photo Film Co., Ltd. 4, Agent Town West Building 5F, 14-15 Nishi-Shinjuku-chome, Shinjuku-ku, Tokyo Telephone (348) 77057877 Patent Attorney Yasugata Contents of Yuzo 6th Amendment (1) Specification, page 9, lines 12 to 16, “Also,
This timing time... is read out and processed. ” to be deleted.

(2) In the same article, page 11, line 7, "also," is amended to "that is,".

(3) Similarly, on page 11, line 8, the phrase "number of times" is corrected to "several times."

(4) Figure 4 attached to this application is amended as shown in the attached sheet.

Claims (1)

[Claims] 1. In a character processing circuit that inputs character data via a CPU bus, processes the data in a character data processing means, and then outputs the processed character data via an image bus, the character data is Switching the writing of the character data to the first and second character data buffers for input and temporary storage and the first or second character data buffer, and to the character data processing means. first and second image data buffers for temporarily storing the processed character data; and first and second image data buffers for temporarily storing the processed character data; The apparatus is characterized by comprising a second switching means for switching writing of processed character data and switching reading to the image bus, and a control means for controlling switching between the first and second switching means. Character processing circuit.