JPH0255821B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vector data processing device that transfers element data between vector registers.

(Prior art) A conventional vector data processing device is disclosed in U.S. Patent No.
4128880 can be referred to. Referring to FIG. 2, according to this publication, vector registers 10 and 11, read/write address registers 20 and 21, element data input selection circuit 30,
It consists of an element data output selection circuit 40 and an arithmetic unit 50.

Each of the vector registers 10 and 11 holds a plurality of element data, and usually a plurality of vector registers are provided. Read/write address registers 20 and 21 designate the location of element data held in vector registers 10 and 11, are cleared to "0" in initial setting, and have a +1 count function.

When performing partial vector operations on element data held in one vector register,
It is necessary to transfer part of the element data held in this vector register to another vector register.

For this purpose, a method is used to transfer element data between a vector register and a main memory using a store/load instruction, or a method is used to transfer element data using a shift instruction.

In the former method, the element data held in the vector register 10 is sequentially stored in the main memory by a specified vector length by a store instruction.
A portion of the stored element data is loaded into the vector register 11. First, the read/write address register 20 is initialized to "0" in response to designation of the transfer source vector register 10 and the vector length to be transferred in a store instruction.
In response to this initialization, vector register 10
Location 0 of the element data held in is output to the element data output selection circuit 40, and as the read/write address register 20 counts up, the element data are sequentially output. Element data output selection circuit 40
The outputs of vector register 10 provided through are sequentially transferred to main memory.

Next, the load start address of the element data necessary for partial vector operation in the load instruction,
Element data is sequentially loaded from the main memory to the vector register 11 according to instructions from the read/write address register 21 in response to the load destination vector register 11 and vector length designation. In the latter method, the elements held in the vector register 10 Data is changed to 1 by shift command
The data is shifted word by word and transferred to the vector register 11.

When a shift command specifies the vector register 10 that holds the element data to be shifted, the vector register 11 that transfers the shift result, the shift amount, and the vector length, the data is stored in the vector register 10 as the read/write address register 20 counts up. The element data stored in the element data output selection circuit 40 is sequentially outputted from location 0 to the element data output selection circuit 40. The output of the vector register 10 provided via the element data output selection circuit 40 is sent to the arithmetic unit 50. The arithmetic unit 50 performs a shift operation in response to the output of the element data output selection circuit 40 and the shift amount specified by the command.

The shift amount is usually specified as a one word shift to the right. By shifting the element data to the right by one word and outputting it, the output of the arithmetic unit 50 is sent to the vector register 11 via the element data input selection circuit 30.
Transported in word-shifted format.

The read/write address register 21 also has a +1 count function and sequentially specifies the location of element data output from the element data input selection circuit 30.

By repeating this shift operation, the predetermined element data transfer is completed.

Therefore, both methods require a main memory or an arithmetic unit, resulting in low element data transfer performance, and have the disadvantage that subsequent instructions compete when they require the main memory or arithmetic unit.

(Object of the Invention) An object of the present invention is to transfer element data between vector storage means at high speed by directly transferring element data from an arbitrary start address of a first vector storage means to a second vector storage means. An object of the present invention is to provide a vector data processing device that can perform vector data processing.

(Structure of the Invention) A vector data processing device of the present invention comprises: a first vector storage means for holding ordered element data; an address setting means for setting an arbitrary read start address of the first vector storage means; and means for transferring the element data sequentially read from the address set by the address setting means to the second vector storage means.

(Embodiments of the Invention) Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes vector registers 100 and 101, read address registers 110 and 111, write address registers 120 and 121, read address selection circuits 130 and 131, and write address selection circuits 140 and 141. , and an element data input selection circuit 200.

The operation of this embodiment is as follows.

A plurality of vector registers, two vector registers 100 and 101 in this embodiment, each hold a plurality of ordered element data, and each holds a plurality of ordered element data, such as a calculation result output from an arithmetic unit or a load output from the main memory. Store data. When performing a partial vector operation on element data held in one vector register, it is necessary to transfer part of the element data held in this vector register to another vector register.

The transfer source vector register holding the calculation result output from the arithmetic unit or the load data output from the main memory is transferred to the vector register 10.
0, and when the transfer destination register to which part of the element data stored in the vector register 100 is transferred is the vector register 101,
The number of the source vector register 100 and the number of the destination vector register 101 are specified by the instruction. The read start address to the transfer source vector register 100 is input to the read address selection circuit 130 as an instruction or instruction accompanying information, but if it is not specified by an instruction, it is set to "0".
is input.

Furthermore, the write start address to the transfer destination vector register is similarly input to the write address selection circuit 141 as a command or instruction accompanying information, but if it is not specified by a command, "0" is input. Note that the setting paths for these start addresses are not shown.

On the other hand, if the instruction is such that the source vector register number specifies vector register 101 and the destination vector register number specifies vector register 100, the read start address of the source vector register is the instruction or instruction accompanying information. is input to the read address selection circuit 131 as follows. The write start address of the transfer destination vector register is similarly input to the write address selection circuit 140 as an instruction or instruction accompanying information. In these cases as well, "0" is input if it is not specified by the instruction. Note that these start address setting paths are also not shown. The maximum element data length that can be held in vector registers 100 and 101 is 64 each, and 32 elements are stored from vector register 100 to vector register 101.
When transferring element data, first set the vector length to "32". The transfer source vector register number is set to vector register 1 by the instruction.
00, the destination vector register number is designated as vector register 101, and the read start address of vector register 100 is designated as "32". The read start address specified by the instruction is input to the read address selection circuit 130, selected and set as “32” in the read address register 110.
The value of is stored. At the same time, since the write start address is not specified by the instruction, "0" is input to the write address selection circuit 141. This is selected and the write address register 121 is initialized to "0". Vector register 100 outputs element data at a location specified by read address register 110 to element data input selection circuit 200 . The read address register 110 has a +1 count function to sequentially read element data, and the next location is location 32, then location 33, and then location 3.
It counts as 4. The vector register 10 is added to the counted location by the specified vector length.
Element data held within 0 is read out and output to element data input selection circuit 200. The element data input selection circuit 200 selects and instructs the element data read from the vector register 100 to be input to the vector register 101.

On the other hand, the vector register 101 writes to the location specified by the write address register 121.
Writing of element data is started when the first element data is output from the element data input selection circuit 200. The write address register 121 and the read address register 110
To write element data sequentially in the same way as +
It has a 1 count function, and the next location after location 0 is counted as location 1, and the next location is counted as location 2. Element data input selection circuit 2 is added to the counted location for the specified vector length.
Element data output from 00 is written. This operation ends when the number of transferred element data reaches "32", that is, when it becomes equal to the vector length designation.

When the read start address of the transfer source vector register is defined as m, if a value of 64-(m-1) or more is specified by the vector length specification, the following will occur. That is, read address register 110
has a function of specifying location 0 as the next location when the location in the vector register 100 reaches "63" and sequentially counting by the number of vector lengths specified.

In another instruction, specify the source vector register number as vector register 100, the destination vector register number as vector register 101, and set the write start address of vector register 101 to "32".
Suppose we specify Since the read start address is not specified by the instruction, "0" is input to the read address selection circuit 130, and this is selected and the read address register 110 is initialized to "0". The write start address specified by the instruction is input to the write address selection circuit 141, and is selected and set to “32” in the write address register 121.
The value of is stored.

Read address register 110 has a +1 count function. In response to the address from this register 110, element data is sequentially read from location 0 of the vector register 100,
It is output to the element data input selection circuit 200. The write address register also has a +1 count function, and the element data input selection circuit 2
Writing starts when the first element data from 00, that is, the element data read from location 0 of the vector register 100, is output. This operation ends when the number of transferred element data reaches "32", that is, when it becomes equal to the vector length designation. Also, when the write start address of the transfer destination is m, 64-(m
-1) If a value above is specified by the vector length specification, the write address register 121 will return to location 0 when the location of the vector register 101 reaches "63", and will sequentially write the number of vector length specifications. It has a function to count only

Furthermore, in another instruction, the source vector register number is specified as vector register 100, the destination vector register number is specified as vector register 101,
Assume that the read start address of the vector register 100 is specified as "32", and the write start address of the vector register 101 is specified as "32". Since both the read start address and the write start address are specified by the instruction, the read address selection circuit 130
Start address “32” is input to write address selection circuit 141 and selected, and stored in read address register 110 and write address register 121. Since the read address register 110 has a +1 count function, the location 32 of the vector register 100
The vector data is sequentially read from the element data input selection circuit 200 and output to the element data input selection circuit 200. The write address register 121 also has a +1 count function, and sequentially writes the element data output from the element data input selection circuit 200 from the location 32 of the vector register 101. This operation ends when the number of transferred element data reaches "32", that is, when it becomes equal to the vector length designation. Also, read start address and write start address are m and n, respectively.
If the vector length designation is greater than 64-(m-1), the contents of the read address register return from 63 to 0 and continue counting. If the vector length designation is greater than 64-(n-1), the contents of the write address register return from 63 to 0 and continue counting.

In this embodiment, the number of vector registers is two, but the present invention is not limited to two, and the element data transfer source is the vector register 100, and the transfer destination is the vector register 101. It is not limited to , and can be arbitrarily specified by a command.

(Effects of the Invention) The present invention includes a means for setting an arbitrary read start address of the first vector storage means and a means for transferring element data between the vector storage means. This has the advantage that it can be realized at high speed from any starting address.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG.
The figure shows a conventional example. 10, 11, 100, 101... Vector register, 20, 21... Read/write address register, 30, 200... Element data input selection circuit, 40... Element data output selection circuit, 50... Arithmetic unit, 110 , 111... Read address register, 120, 121... Write address register, 130, 131... Read address selection circuit, 140, 141... Write address selection circuit.

Claims (1)

[Scope of Claims] 1. A first vector storage means for holding ordered element data, an address setting means for setting an arbitrary read start address of the first vector storage means, and a method set by the address setting means. 1. A vector data processing apparatus, comprising: a transfer means for sequentially transferring element data read from a given address to a second vector storage means.