JPH01162236U - - Google Patents
Info
- Publication number
- JPH01162236U JPH01162236U JP5548788U JP5548788U JPH01162236U JP H01162236 U JPH01162236 U JP H01162236U JP 5548788 U JP5548788 U JP 5548788U JP 5548788 U JP5548788 U JP 5548788U JP H01162236 U JPH01162236 U JP H01162236U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- semiconductor component
- semiconductor
- metallized layer
- conductive pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 5
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
図面はいずれも本考案の実施例を示し、第１図
は第１の実施例の平面図、第２図および第３図は
夫々その断面図、第４図は第２の実施例の平面図
、第５図及び第６図は夫々その断面図、第７図は
第３の実施例の平面図、第８図はその断面図であ
る。
１，２，３，９……メタライズ層、４……ＦＥ
Ｔチツプ、５……凹所、６……ソルダ、７……ボ
ンデイングワイヤ、８……素子容器。
The drawings all show embodiments of the present invention; FIG. 1 is a plan view of the first embodiment, FIGS. 2 and 3 are sectional views thereof, and FIG. 4 is a plan view of the second embodiment. , FIG. 5 and FIG. 6 are respectively sectional views thereof, FIG. 7 is a plan view of the third embodiment, and FIG. 8 is a sectional view thereof. 1, 2, 3, 9...metalized layer, 4...FE
T-chip, 5... recess, 6... solder, 7... bonding wire, 8... element container.
Claims (1)
前記凹所内底部にメタライズ層が形成されており
、前記メタライズ層上に半導体チツプがソルダに
て固着されている半導体部品。 ２ 凹所は、導電パターン中に形成されている請
求項１記載の半導体部品。 ３ 導電パターンはドレイン用、ゲート用および
ソース用に夫々分離して形成されており、各導電
パターンは夫々半導体素子にボンデイングワイヤ
にて接続されている請求項１又は請求項２記載の
半導体部品。[Claims for Utility Model Registration] 1. An insulating device container in which a recess is formed.
A semiconductor component, wherein a metallized layer is formed on the inner bottom of the recess, and a semiconductor chip is fixed on the metallized layer with solder. 2. The semiconductor component according to claim 1, wherein the recess is formed in the conductive pattern. 3. The semiconductor component according to claim 1 or claim 2, wherein the conductive patterns are formed separately for a drain, a gate, and a source, respectively, and each conductive pattern is connected to the semiconductor element by a bonding wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5548788U JPH01162236U (en) | 1988-04-25 | 1988-04-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5548788U JPH01162236U (en) | 1988-04-25 | 1988-04-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01162236U true JPH01162236U (en) | 1989-11-10 |
Family
ID=31281389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5548788U Pending JPH01162236U (en) | 1988-04-25 | 1988-04-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01162236U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003023843A1 (en) * | 2001-09-05 | 2003-03-20 | Renesas Thechnology Corp. | Semiconductor device, its manufacturing method, and radio communication device |
-
1988
- 1988-04-25 JP JP5548788U patent/JPH01162236U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003023843A1 (en) * | 2001-09-05 | 2003-03-20 | Renesas Thechnology Corp. | Semiconductor device, its manufacturing method, and radio communication device |