JPH01157571A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides AI for semiconductor devices! , or Affi-3i
This invention relates to a method of conducting electrical connection between a metal wiring such as a diffusion layer, a substrate, etc., and a diffusion layer or a substrate.

In the conventional MOSTr, Af! , or Affi-
The conduction between the metal wiring such as 3i and the diffusion layer or the substrate is achieved by bringing the diffusion layer 3 and the metal wiring 7 into direct contact and by low-temperature heat treatment, as shown in Fig. 1, through the eutectic formation of the metal and the semiconductor substrate. It has continuity. In this method, the difference in level from the surface of the diffusion layer 3 to the top of the field oxide film 2, particularly to the top of the POLY-3j6 on the field oxide film 2, is very large and may lead to disconnection. Also the second
As shown in the figure, due to misalignment in the so-called photo-etching process, the contact hole for establishing conduction between the diffusion layer 3 and the metal wiring 7 is misaligned, and the metal wiring 7 and the substrate 1 are directly connected. This may lead to short circuits and leaks.

The present invention is intended to compensate for the above-mentioned drawbacks, and includes a PO between the diffusion layer 3 and the metal wiring 7 shown in FIG.
The LY-3i is interposed to establish conduction between the two. Using Figures 3 to 7 to make it easier to understand,
The case of channel MOSTr will be explained as an example. Third
The figure shows a gate oxide film 103 formed using a general silicon gate MOSTr manufacturing method.
1 is a Si substrate, and 102 is a field oxide film.

Here, as shown in FIG. 4, a hole is made in a portion where a contact hole will be formed later using a photoetching technique, and POLY-3i 104 is formed on the entire surface. Furthermore, as shown in Fig. 5, a PO
At the same time as forming the LY-3i gate and wiring, photoetching is used to leave the POLY-3i. Next, as shown in FIG. 6, a diffusion layer 105 is formed by diffusion or ion implantation, a glabellar insulating film 106 is formed as shown in FIG. 7, and contact holes are made using photoetching. .

A metal wiring 107 such as the like is applied.

In the structure shown in FIG. 7 formed in this manner, there is no problem at all with the conduction between the metal wiring 107 and the diffusion layer 105, and furthermore, the level difference through which the metal wiring passes is clearly reduced, and as mentioned above, the alignment during photoetching is There is no possibility of short circuits due to misalignment, etc. Furthermore, by using this method, even if the diffusion layer 105 is shallow, the metal wiring 107 may react excessively with the Si of the diffusion layer in the contact hole, causing a short circuit with the underlying substrate. can suppress the phenomenon.

In addition, conduction from the diffusion layer or substrate can be
By using this structure in a semiconductor device that uses wiring in a self-aligned manner, the degree of freedom in metal wiring can be increased by establishing conduction between the metal wiring such as A/2 and the POLY-3i wiring at this self-aligned portion. and increase the degree of integration.

-For example, it is no longer necessary to take a dimensional margin due to alignment accuracy in the photo-etching process in the area where the metal wiring and POLY-3i wiring were conventionally connected on the field insulating film. The degree of integration increases.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a conventional structure, FIG. 2 is an explanatory diagram of problems in the conventional method, and FIGS. 3 to 7 are explanatory diagrams of a semiconductor device and its manufacturing method of the present invention. 1.101...Semiconductor substrate 2.102...Field insulating film 103...Gate oxide film 104...
...POLY-3t3.105...Diffusion layer 4...Gate POLY-3
i5.106...Interlayer insulating film 6......POL on field
Y-3t7.107...Metal wiring Figure 1 1\4 ~ Figure 2 C Figure 7 Figure 1 procedural amendment (voluntary) December 15, 1988 Director General of the Patent Office Yoshi 1) Moon Takeshi 1 , Indication of the case 1986 Patent Application No. 291521 2 Name of the invention Method for manufacturing semiconductor devices 3 Person making the amendment Relationship to the case Applicant Seiko Epson, 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo (236) Co., Ltd. Specification (Claims 2 Brief Description of Drawings) Procedural Amendment 1. The scope of claims is amended as shown in the attached sheet. 2. On page 5, lines 8-9 of the specification, the phrase "of a semiconductor device and its manufacturing method" is amended to read "of a manufacturing method and a semiconductor device manufactured by the manufacturing method of the present invention."that's all

Claims (1)

[Claims] In a method for manufacturing a MOS type transistor including a source, drain, gate, and field insulating film formed on a semiconductor substrate, a step of forming a gate insulating film on a semiconductor substrate having an element isolation region, and a step of forming a gate insulating film on a region where a contact hole is to be formed. a step of opening the contact hole in the gate insulating film; a step of forming a polycrystalline silicon film on the entire surface of the semiconductor substrate after the step; etching polycrystalline silicon to form the gate electrode and at the same time form the source and drain. a step of forming polycrystalline silicon across the region and the element isolation region by etching, a step of forming source and drain diffusion layers by a diffusion method or an ion implantation method after the step, and a step of forming the semiconductor substrate after the step. a step of forming an interlayer insulating film on the entire surface, a step of opening a contact hole spanning at least the polycrystalline silicon formed on the source and the drain by etching the interlayer insulating film, and forming a metal wiring after the step. A method for manufacturing a semiconductor device, characterized in that: