JPH01152731A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01152731A JPH01152731A JP62314608A JP31460887A JPH01152731A JP H01152731 A JPH01152731 A JP H01152731A JP 62314608 A JP62314608 A JP 62314608A JP 31460887 A JP31460887 A JP 31460887A JP H01152731 A JPH01152731 A JP H01152731A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor substrate
- exposed
- covering
- wax
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Weting (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分膏〕
この発明は、薄く、かつ厚メッキ層が選択的に形成され
た半導体基板を有する半導体装置の製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having a semiconductor substrate on which a thin and thick plating layer is selectively formed.
一般に高出力の半導体装置においては、その放熱特性の
いかんが重要な問題となっている。そして、放熱を良好
にずろための対策の1つとして半導体基板をごく薄いも
のとなし、それにfL属放熱体を被着することが知られ
ている。。Generally, in high-output semiconductor devices, the issue of their heat dissipation characteristics is an important issue. It is known that one of the measures for achieving good heat dissipation is to make the semiconductor substrate very thin and to cover it with an fL heat dissipator. .
ところが、半導体基板をt々くすると放熱体の影響を受
け、半導体基板に大きな反りが生じ、個々の半導体装置
(以Fチ・ツブという)への分離が難しくなって(る。However, when the semiconductor substrate is heated up, it is affected by the heat dissipation body, causing large warpage in the semiconductor substrate, making it difficult to separate it into individual semiconductor devices (hereinafter referred to as chips).
第2図は上記した半導体基板に反りが生じた状態を表す
要部側面図であって、薄い半導体装置11に金属放熱体
12を選択的に破着し1=ものである。図示のように、
半導体基板11は、この半導体基板11と金属放熱体1
2の熱膨張係数の差に応した反りが生してしまう。この
ような半導体基板11を個々のチップに分離する方法と
しては、スクライブあるいはグイノング・ソーで分離す
る方法があるが、いずれの場合もr1j膜化された半導
体基板11の取扱いが極めてNIL<、処理時に半導体
基板11の割れやクラック等が生じ、チ・ツブ収率を低
下させろ大きな要因となっている。1なお、13ば素子
形成領域、14ば導電層である。。FIG. 2 is a side view of a main part showing a state in which the above-described semiconductor substrate is warped, in which a metal heat sink 12 is selectively broken to a thin semiconductor device 11. As shown,
The semiconductor substrate 11 is composed of this semiconductor substrate 11 and the metal heat sink 1.
Warpage occurs in response to the difference in thermal expansion coefficients between the two. As a method of separating such a semiconductor substrate 11 into individual chips, there is a method of separating the semiconductor substrate 11 into individual chips by using a scribe or a Guinong saw, but in either case, handling of the semiconductor substrate 11 formed into an r1j film is extremely difficult. Occasionally, cracks or cracks occur in the semiconductor substrate 11, which is a major factor in reducing the chip yield. 1, numeral 13 is an element forming region, and numeral 14 is a conductive layer. .
これを解決するため第3図に示すように、ウェハプロセ
ス段階でエツチングカットによりチップ分離を行う方法
が提案された1、この方法は第3図(n)に示すように
、ガラス板26上にワ・ソクス層25te介して倒置形
で貼り付けられた半導体基(反21を幼11り化し、半
導体基板21表面上に形成さねた素子形成領域23(こ
対向する位置に選択的に放熱体22を形成し、次いで、
第3図(b)に示すように、放熱体22をマスクとし、
半導体基板21を表向からエツチングにより分離するも
のである7、なお、24は導電層である。To solve this problem, a method has been proposed in which chips are separated by etching at the wafer process stage, as shown in FIG. A semiconductor substrate 21 is attached in an inverted manner through a wax layer 25te, and an element forming region 23 is formed on the surface of the semiconductor substrate 21. 22 and then
As shown in FIG. 3(b), the heat sink 22 is used as a mask,
The semiconductor substrate 21 is separated from the surface by etching 7, where 24 is a conductive layer.
17かしながら、この方法においては、半導体基板21
の’f4膜化時に生じる半導体基板21曲内のばらつき
がエツチング時のサイドエツチング旦のばらつきを生む
原因となるため、薄膜化時の半導体基板21の不均一性
がチップ分雌形状を悪化させ、歩留りを低下させる等の
要因となっている。17 However, in this method, the semiconductor substrate 21
The variation within the semiconductor substrate 21 that occurs when forming the 'f4 film causes the variation in side etching during etching, so the non-uniformity of the semiconductor substrate 21 during thinning deteriorates the female shape of the chip. This is a factor that reduces yield.
この発明(よ、上記のような問題点を解消するためにな
されたもので、放熱体が被着さオ゛1、薄膜化された半
導体基板のチップ分離を高精度で実現できる半導体装置
の製造方法を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it is aimed at manufacturing a semiconductor device that can realize chip separation of a thin semiconductor substrate with high accuracy by attaching a heat dissipating body. The purpose is to obtain a method.
この発明に係る半導体装置の製造方法は、半導体基板表
面に形成された複数の素子形成領域をそれぞれ第1の被
覆層で覆う工程、第1の被覆層をマスクとして半導体基
板に所定の深さの分離溝を形成する工程2分離溝を含む
半導体基板の全曲にソックス層を形成し、このワックス
層を介して倒置形でガラス板に貼り付ける工程、半導体
基板をワ・ソクス層表面が露出するまでエツチングして
薄1戊化する工程、i置換化した半導体基板の露出しな
ワ・ソクス層を含む全面に導電層を形成する工程。A method for manufacturing a semiconductor device according to the present invention includes the step of covering each of a plurality of element formation regions formed on the surface of a semiconductor substrate with a first coating layer, and using the first coating layer as a mask to cover the semiconductor substrate with a predetermined depth. Step 2 of forming separation grooves: Forming a sock layer on the entire surface of the semiconductor substrate, including the separation grooves, and pasting the semiconductor substrate upside down on a glass plate through this wax layer, until the surface of the wax layer is exposed. A step of etching to make a thin layer, and a step of forming a conductive layer on the entire surface of the i-substituted semiconductor substrate, including the exposed wax layer.
半導体基板の薄膜化により露出したワックスj−上の4
電層の一部I!覆う第2の被覆層を形成する工程、第2
の被覆層をマスクとして導電層の露出部に選択的に厚メ
・フキ層を形成する工程、厚メッキ層をマスクとし、第
2の被覆層および導電jごを除去した後、ガラス板から
剥離すると同時にワックス層および第1の被覆層を除去
し、チップ分離を行う工程を含むものである。4 on the wax j- exposed due to thinning of the semiconductor substrate
Part of the electric layer I! forming a second covering layer;
A step of selectively forming a thick plating layer on the exposed parts of the conductive layer using the second coating layer as a mask.After removing the second coating layer and the conductive layer using the thick plating layer as a mask, peeling it off from the glass plate. At the same time, the wax layer and the first coating layer are removed, and the chips are separated.
この発明においては、半導体基板表面の素子形成領域を
覆う第1の彼PiiT層の外周部に所定の深さの分離溝
を形成し、この分離溝を含む全面にワックス層を形成し
、こ0)ワ・ノクス層を介してガラス基板上に貼り付け
た後、半導体基板表面側をワ・ソクス層表面が露出する
までエツチングした後、チップ分離を行うので、平坦性
の良い半導体基板表面に形成された分離溝の面内均一性
が良好なことから、ぞれにより分離されたチップ形状も
ばらつきが少なく制御性の良いものとなる。In this invention, a separation groove of a predetermined depth is formed in the outer periphery of the first HPIiT layer that covers the element formation region on the surface of the semiconductor substrate, and a wax layer is formed on the entire surface including the separation groove. ) After pasting on the glass substrate through the WANOX layer, the surface side of the semiconductor substrate is etched until the WANOX layer surface is exposed, and then the chips are separated, so the semiconductor substrate surface has good flatness. Since the in-plane uniformity of the separated separation grooves is good, the shape of the separated chips also has little variation and has good controllability.
〔実施例]
第1図(n)〜(h)はこの発明の半導体装置の製造方
法の一実施例の主要工程を示す断面図である。[Embodiment] FIGS. 1(n) to 1(h) are cross-sectional views showing the main steps of an embodiment of the method for manufacturing a semiconductor device of the present invention.
まず、第1図(a)に示すように、半導体基板1上に形
成された素子形成領域2を覆い、その外周の半導体基板
1の一部を露出させた第1の被覆層3、例えばし・ンス
ト層のパターンを形成する。次に、第1のil[l15
3をマスクとして第1図(b)に示すように、例えばウ
ェットエツチング方法により、底部基板厚が最終基板厚
と同程度となるような深さ(例えば30u+n)の分離
溝4を形成する。First, as shown in FIG. 1(a), a first covering layer 3 is formed, which covers an element formation region 2 formed on a semiconductor substrate 1 and exposes a part of the semiconductor substrate 1 on the outer periphery.・Form the pattern of the strike layer. Next, the first il[l15
As shown in FIG. 1B, using 3 as a mask, a separation groove 4 having a depth (for example, 30u+n) such that the bottom substrate thickness is approximately the same as the final substrate thickness is formed by, for example, a wet etching method.
しかる後、第1図(c)に示すように、素子形成領域2
上の第1の被ffJda上から分離maにわたりワック
ス層5を形成し、このワックス層5を介してガラス板6
に倒置形で貼り付けろ。続いて、第1図(d)に示すよ
うに、半導体基板1の一面から、例又はラッピング、エ
ッチレグ等に上りワックス層5表面が完全にシ3出する
まで半導体基数1を薄膜化する、。After that, as shown in FIG. 1(c), the element formation region 2 is
A wax layer 5 is formed over the first target ffJda over the separation ma, and a glass plate 6 is formed through this wax layer 5.
Paste it upside down. Subsequently, as shown in FIG. 1(d), the semiconductor substrate 1 is thinned from one surface of the semiconductor substrate 1 by lapping, etching, etc. until the surface of the wax layer 5 is completely exposed.
これにより、半導体基板1(、を個々のチ、ノブに分S
tされた形となる。次いで、第1図(Q)に示すように
、半導体基板1の裏面から薄膜化により露出しなワ・ソ
クス層5表面を含む全面に、後工程で形成する厚、メッ
キ層9の形成に必要な、例えばTi/Au等からなる導
電層7を形成する。This divides the semiconductor substrate 1 into individual chips and knobs.
It has a t-shape. Next, as shown in FIG. 1 (Q), the thickness required for forming the plating layer 9 to be formed in a later process is applied to the entire surface of the semiconductor substrate 1 including the surface of the wax layer 5 which is not exposed due to thinning from the back surface of the semiconductor substrate 1. For example, a conductive layer 7 made of Ti/Au or the like is formed.
続いて、第1図(f)に示すように、素子形成領域2外
周に相当するワックス層5上の導電層7の一部に第2の
被覆層8、例えばL・レスト層のバクーンを形成するっ
次いで、第1図(g)に示すように、第2の被覆lid
8をマスクとして導電jd7を介(7て選択的に放熱
体としての厚メッキIfi 9を形成する。。Subsequently, as shown in FIG. 1(f), a second coating layer 8, for example, a back layer of an L-rest layer is formed on a part of the conductive layer 7 on the wax layer 5 corresponding to the outer periphery of the element forming area 2. Then, as shown in FIG. 1(g), a second covering lid is applied.
Using 8 as a mask, a thick plating Ifi 9 is selectively formed as a heat sink via a conductive layer 7.
その後、厚メッキ層9をマスクとして、第2の被覆jご
8と導電層7を順次除去し、最後にガラ2ス板6より剥
離し、ワックス層5と第1の被覆層3を除去し、第1図
(h)に示すような構造を得ろ。Then, using the thick plating layer 9 as a mask, the second coating 8 and the conductive layer 7 are sequentially removed, and finally the glass plate 6 is peeled off, and the wax layer 5 and the first coating layer 3 are removed. , obtain a structure as shown in Figure 1(h).
上記のようなこの発明においては、チップ分離を半導体
基板1の一表面側から行うため、分離溝4の精度ならび
に制御性が向上することにより、分離されたチップの形
状のばらつきが低it或され、チ・ツブ収率の向上が達
成できる。In the present invention as described above, since the chips are separated from one surface side of the semiconductor substrate 1, the accuracy and controllability of the separation grooves 4 are improved, so that variations in the shape of separated chips can be reduced to low IT. , an improvement in the yield of chives and whelks can be achieved.
なお、上記実施例では分#溝4の形成をウエリトエッヂ
ング法で行う場合を示したが、ドラ、イエノチノグ法、
ダインング・ソー法等であっても差支えない。In the above embodiment, the groove 4 is formed by the Uerito edging method, but it is also possible to use the Dra, Ienochinog,
There is no problem with the ding-and-saw method, etc.
[発明の効果〕
この発明(ま以上説明したとおり、半導体基板表面に形
成された複数の素子形成領域をそれぞれ第1の?!!!
覆層で覆う工程、第1の被覆層をマスクと17で半導体
基板に所定の深さの分離溝を形成する工程2分離溝を含
む半導体基板の全面にワ・ソクスJiv#を形成し、と
のワ・ソクス層を介して倒置形でガラス板に貼り付けろ
工程2半導体基板をワックス層表向が露出するまで工・
ソチングして薄jj便化する工程、薄膜化した半導体基
板の露出したワックス層を含む全面に導電層を形成する
工程、半導体基板の薄膜化により露出したワックス層上
の導電層の一部を覆う第2の被覆層を形成する工程、第
2のmm層をマスクとして導電層の露出部に選択的に厚
メッキ層を形成する工程、厚メッキ層をマスクとし、第
2の被覆層および導電層を除去した後、ガラス板から剥
離すると同時にワックス層および第1の被覆層を除去し
、チップ分離を行う工程を含むので、分離溝の精度なら
びに制御性が向上し、分離されたチップの形状ばらつき
が低減され、チップ収率の向上が達成できる効果がある
。[Effects of the Invention] This invention (as explained above, each of the plurality of element formation regions formed on the surface of the semiconductor substrate is connected to the first ?!!!)
Step of covering the first covering layer with a mask and step 17 of forming an isolation groove of a predetermined depth in the semiconductor substrate. Step 2: Forming a wax JIV# on the entire surface of the semiconductor substrate including the isolation groove, and Attach the semiconductor substrate upside down to a glass plate through the wax layer. Step 2: Process the semiconductor substrate until the surface of the wax layer is exposed.
A process of making the semiconductor substrate thinner by sowing, a process of forming a conductive layer on the entire surface including the exposed wax layer of the thinned semiconductor substrate, and a part of the conductive layer on the wax layer exposed by thinning the semiconductor substrate. a step of forming a second coating layer; a step of selectively forming a thick plating layer on the exposed portion of the conductive layer using the second mm layer as a mask; After removing the chips, the wax layer and the first coating layer are removed from the glass plate at the same time, and the chips are separated. This improves the precision and controllability of the separation grooves and reduces shape variations in the separated chips. This has the effect of reducing chip yield and improving chip yield.
第1図(a)〜(h)はこの発明の一実施例を示す半導
体装置の製造方法を説明するための主要工程におけろ断
面図、第2図および第:う図(11,(b)は従来の半
導体装置の製造方法を説明するための主要工程における
断面図である。。
図において、1は半導体基板、2は素子形成領域、3は
第1の被覆層、4は分離溝、5はワックス層、6はガラ
ス板、7は導電層、8は第2の被Wi層、9ば厚メッキ
層である。
なお、各図中の同一符号は同一または相当部分を示す、
。
代理人 大 岩 増 雄 (外2名)bガラス仮
ソ厚メッキ層FIGS. 1(a) to (h) are cross-sectional views of main steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 and FIGS. ) is a cross-sectional view of main steps for explaining a conventional method for manufacturing a semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is an element formation region, 3 is a first covering layer, 4 is a separation groove, 5 is a wax layer, 6 is a glass plate, 7 is a conductive layer, 8 is a second Wi layer, and 9 is a thick plating layer. Note that the same reference numerals in each figure indicate the same or equivalent parts.
. Agent: Masuo Oiwa (2 others) b Glass temporary soldering thick plating layer
Claims (1)
れぞれ第1の被覆層で覆う工程、前記第1の被覆層をマ
スクとして前記半導体基板に所定の深さの分離溝を形成
する工程、前記分離溝を含む前記半導体基板の全面にワ
ックス層を形成し、このワックス層を介して倒置形でガ
ラス板に貼り付ける工程、前記半導体基板を前記ワック
ス層表面が露出するまでエッチングして薄膜化する工程
、前記薄膜化した半導体基板の露出したワックス層を含
む全面に導電層を形成する工程、前記半導体基板の薄膜
化により露出したワックス層上の導電層の一部を覆う第
2の被覆層を形成する工程、前記第2の被覆層をマスク
として前記導電層の露出部に選択的に厚メッキ層を形成
する工程、前記厚メッキ層をマスクとし、前記第2の被
覆層および導電層を除去した後、ガラス板から剥離する
と同時に前記ワックス層および第1の被覆層を除去し、
チップ分離を行う工程を含むことを特徴とする半導体装
置の製造方法。a step of covering each of a plurality of element formation regions formed on a surface of a semiconductor substrate with a first coating layer; a step of forming a separation groove of a predetermined depth in the semiconductor substrate using the first coating layer as a mask; A step of forming a wax layer on the entire surface of the semiconductor substrate including the grooves and attaching it to a glass plate in an inverted manner through the wax layer, and a step of etching the semiconductor substrate until the surface of the wax layer is exposed to make it a thin film. , forming a conductive layer on the entire surface of the thinned semiconductor substrate including the exposed wax layer; forming a second covering layer covering a part of the conductive layer on the wax layer exposed by the thinning of the semiconductor substrate; a step of selectively forming a thick plating layer on the exposed portion of the conductive layer using the second covering layer as a mask; using the thick plating layer as a mask, removing the second covering layer and the conductive layer. After that, simultaneously removing the wax layer and the first coating layer from the glass plate,
A method for manufacturing a semiconductor device, the method comprising the step of separating chips.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62314608A JPH01152731A (en) | 1987-12-10 | 1987-12-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62314608A JPH01152731A (en) | 1987-12-10 | 1987-12-10 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01152731A true JPH01152731A (en) | 1989-06-15 |
Family
ID=18055344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62314608A Pending JPH01152731A (en) | 1987-12-10 | 1987-12-10 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01152731A (en) |
-
1987
- 1987-12-10 JP JP62314608A patent/JPH01152731A/en active Pending
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