JPS59105339A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59105339A JPS59105339A JP21506182A JP21506182A JPS59105339A JP S59105339 A JPS59105339 A JP S59105339A JP 21506182 A JP21506182 A JP 21506182A JP 21506182 A JP21506182 A JP 21506182A JP S59105339 A JPS59105339 A JP S59105339A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- silica
- conductive layer
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、配線用多結晶導電層のサイドエッチをなくす
ことによって電気的に良好な電極接触及び配線を得るこ
とができる半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device that can obtain electrically good electrode contact and wiring by eliminating side etching of a polycrystalline conductive layer for wiring.
第1図(a)乃至第1図(e)は、従来の半導体装置の
製造方法を示している。この製造方法は、第1図(a)
に示すようにP型巣結晶シリコン基板1の一生表面に気
相成長法によ)酸化膜2を形成し、次に配線用多結晶シ
リコン膜3およびアルミニウム4並びに光の反射による
フォトレジストの逆ひけ保止膜となる珪素薄膜5を被着
する。次に、第1図(′b)に示すように7オトレジス
ト6を所定のパターンにバターニングする。このフォト
レジスト6をマスクにエツチングし、その後、フォトレ
ジスト6を除去して第1図(C)を得る。次に珪素薄膜
5をエツチングすると、第1図(d)の様になる。もし
、この珪素薄膜5を残したままでバット部にボンデング
を行なうとボンデング強度が弱い。その後気相成長法に
よシカバー酸化膜7を被着すると第1図(e)を得る。FIGS. 1(a) to 1(e) show a conventional method of manufacturing a semiconductor device. This manufacturing method is shown in Figure 1(a).
As shown in FIG. 2, an oxide film 2 (by vapor phase growth method) is formed on the surface of a P-type nested crystalline silicon substrate 1, and then a polycrystalline silicon film 3 for wiring, aluminum 4, and a photoresist film are formed by reflecting light. A thin silicon film 5 serving as a sink prevention film is deposited. Next, as shown in FIG. 1('b), the 7-photoresist 6 is patterned into a predetermined pattern. This photoresist 6 is used as a mask for etching, and then the photoresist 6 is removed to obtain FIG. 1(C). Next, when the silicon thin film 5 is etched, it becomes as shown in FIG. 1(d). If bonding is performed on the butt portion with this silicon thin film 5 remaining, the bonding strength will be weak. Thereafter, a SiC cover oxide film 7 is deposited by vapor phase growth to obtain the structure shown in FIG. 1(e).
このように形成された半導体装置の製造方法では、珪素
薄膜5をエツチングした時に、配線ボリン!J/M(3
)もエツチングされてしまい電気的に良好な電極接触及
び配線を得ることが出来々い。又、この配線ポリシリの
サイドエッチは、カバー酸化膜のカバーレッジを悪くす
ると共に、クラックの恐れがある。In the method for manufacturing a semiconductor device formed in this manner, when the silicon thin film 5 is etched, wiring vol. J/M(3
) are also etched, making it impossible to obtain good electrical electrode contact and wiring. Further, side etching of the wiring polysilicon deteriorates the coverage of the cover oxide film and may cause cracks.
本発明は、上記点に鑑みてなされたものでその目的とす
る所は、珪素薄膜5をエツチングする時に配も;ポリシ
リ層3をサイドエッチさせないようにして電気的に良好
な電極接触及び配線を得るような半導体装置の製造方法
を提供するものである。The present invention has been made in view of the above points, and an object of the present invention is to prevent side etching of the polysilicon layer 3 when etching the silicon thin film 5, and to ensure electrically good electrode contact and wiring. The present invention provides a method for manufacturing a semiconductor device such that the semiconductor device can be obtained.
この発明の半導体装置は、−導型を有する半導体基板の
一生表面に絶縁膜を形成する工程と、該絶縁膜上に配線
用多結晶導電層およびその上に金属導電層を形成する工
程と、前記金属導電層上に光の反射によるフォトレジス
トの逆ひけ保止膜となる珪素薄膜を形成する工程と、該
多結晶導電層および金属導電層並びに珪素薄膜をフォト
レジストをマスクにして所定の形状にバターニングする
工程と、前記フォトレジストを除去する工程と、その後
配線用多結晶導電層を株うようにシリカフィルムを塗布
する工程と、該珪素薄膜上のシリカフィルムと珪素薄膜
をエツチングする工程とを含む本発明の製造方法である
。従えば、珪素薄膜をエツチングする時に配線ポリシリ
層(/iクリ力フィルムで覆っている、だめにサイドエ
ッチがなく電気的に良好f2電極接触及び配線を得るこ
とが出来る利点かを・る。又、このシリカフィルムによ
ってカバー酸化膜のカバーレッジが良好と力る。The semiconductor device of the present invention includes the steps of: forming an insulating film on the entire surface of a semiconductor substrate having a conductivity type; forming a polycrystalline conductive layer for wiring on the insulating film and a metal conductive layer thereon; A step of forming a silicon thin film on the metal conductive layer, which serves as a film to prevent reverse sinking of the photoresist due to light reflection, and forming the polycrystalline conductive layer, the metal conductive layer, and the silicon thin film into a predetermined shape using the photoresist as a mask. a step of removing the photoresist, a step of applying a silica film so as to cover a polycrystalline conductive layer for wiring, and a step of etching the silica film on the silicon thin film and the silicon thin film. The manufacturing method of the present invention includes: Accordingly, when etching a silicon thin film, the advantage of covering it with a wiring polysilicon layer (crystalline film) is that there is no side etching and electrically good f2 electrode contact and wiring can be obtained. This silica film provides good coverage of the cover oxide film.
次に本発明の実施例を図面を用いて説明する3j第2図
(a)乃至第2図(f)は、本発明の実施例を適用した
半導体装置の製造方法を説明するだめの断面図である。Next, embodiments of the present invention will be explained using drawings. 3j Figures 2(a) to 2(f) are cross-sectional views for explaining a method of manufacturing a semiconductor device to which an embodiment of the present invention is applied. It is.
P型車結晶シリコン基板11の一生表面に気相成長法に
よシ酸化膜12を形成し、次に配線用多結晶シリコン膜
13およびアルミニウム14並びに光の反射によるフォ
トレジストの逆ひけ保止膜となる珪素薄膜15を被着す
る。次にフォトレジスト16を所定のパターンにバター
ニングする。A silicon oxide film 12 is formed on the surface of a P-type crystalline silicon substrate 11 by a vapor phase growth method, and then a polycrystalline silicon film 13 for wiring, aluminum 14, and a photoresist anti-sink film due to light reflection are formed. A silicon thin film 15 is deposited. Next, the photoresist 16 is patterned into a predetermined pattern.
このフォトレジスト16をマスクにエツチングし、その
後フォトレジスト16を除去して第2図(C)を葡る。This photoresist 16 is used as a mask for etching, and then the photoresist 16 is removed to obtain the pattern shown in FIG. 2(C).
次にシリカフィルムを塗布しその後シリカフィルムを低
電1でベークして固めたのを第2図(d)に示す。次に
、エツチング法によシ珪素薄膜15が除去する甘でエツ
チングして第2図(e)を得る。Next, a silica film was applied, and then the silica film was baked with low electric current 1 to harden it, as shown in FIG. 2(d). Next, the silicon thin film 15 is etched by an etching method to obtain the image shown in FIG. 2(e).
次に気相成長法によ少カバー酸化膜18を成長して第2
図(f)を得る。Next, a small cover oxide film 18 is grown using a vapor phase growth method to form a second cover oxide film 18.
Figure (f) is obtained.
とのように製造された半導体装置の製造方法は、シリカ
フィルムで配線ポリシリ層のサイドエッチを防ぐことに
よシミ気菌に良好な電極接触及び配線を得ることができ
る。又、このシリカフィルムによってカバー酸化膜のカ
バーレッジが良好となる。The method for manufacturing a semiconductor device manufactured as described above can obtain good electrode contact and wiring against stains by preventing side etching of the wiring polysilicon layer with a silica film. Moreover, this silica film improves the coverage of the cover oxide film.
第1図(a)乃至第1図(e)は従来の半導体装置の製
造方法を示す断面図で、第2図(a)乃至第2図(f)
は本発明のNチャンネル型シリコン集積回路装置の製造
に実施した場合各々の製造工程断面図である。
同、図において、1.11・・四P型単結晶シリコン基
板、2.12・・・・・・CVD酸化膜、3.13・叩
・多i晶シIJ:+ン膜、4.14・・・・・・アルミ
ニウム電極、5.15・・・・・・珪累坩膜、6.16
・・・・・・フォトレジスト、7.18・・・・・・C
VD酸(111m、17・・曲シリカフィルム、である
。
/シl
(α)
ζ′
(bン
/171
(C)
′\−/
(d)
(e)
第l 凹
第1図
へ///
(0−)
97//
<b>
l/
/−又/
<C>
第2 z
Crt)
/3 、、A−/′/
(e)
(,7’)
第2閲FIGS. 1(a) to 1(e) are cross-sectional views showing a conventional method of manufacturing a semiconductor device, and FIGS. 2(a) to 2(f)
1A and 1B are cross-sectional views of each manufacturing process when implemented in manufacturing an N-channel type silicon integrated circuit device according to the present invention. In the same figure, 1.11...4P type single crystal silicon substrate, 2.12...CVD oxide film, 3.13. Polycrystalline silicon IJ:+n film, 4.14 ...Aluminum electrode, 5.15...Silicone crucible membrane, 6.16
...Photoresist, 7.18...C
VD acid (111m, 17... curved silica film, /sil (α) ζ' (bn/171 (C) '\-/ (d) (e) 1st concave to Figure 1// / (0-) 97// <b> l/ /-also/ <C> 2nd z Crt) /3 ,,A-/'/ (e) (,7') 2nd review
Claims (1)
する工程と、該絶縁膜上に配線用多結晶導電層およびそ
の上に金属導電層を形成する工程と、前記金属導電層上
に光の反射によるフォトレジストの逆ひけ保止膜となる
珪素薄膜を形成する工程と、該多結晶導電層および金属
導電層並びに珪素薄膜をフォトレジストをマスクにして
所定の形状にバターニングする工程と、前記フォトレジ
ストを除去する工程と、その後、配線用多結晶導電層を
覆うようにシリカフィルムを塗布する工程と、該珪素薄
膜上のシリカフィルムと珪素薄膜をエツチングする工程
とを含む半導体装置の製造方法。A step of forming an insulating film on the entire surface of a semiconductor substrate having one conductivity type, a step of forming a polycrystalline conductive layer for wiring on the insulating film and a metal conductive layer thereon, and a step of forming a polycrystalline conductive layer for wiring on the insulating film and a metal conductive layer thereon; a step of forming a silicon thin film to serve as a reverse sink prevention film for the photoresist due to reflection of the photoresist, and a step of patterning the polycrystalline conductive layer, the metal conductive layer, and the silicon thin film into a predetermined shape using the photoresist as a mask; Manufacturing a semiconductor device, comprising the steps of removing the photoresist, thereafter applying a silica film to cover the polycrystalline conductive layer for wiring, and etching the silica film on the silicon thin film and the silicon thin film. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21506182A JPS59105339A (en) | 1982-12-08 | 1982-12-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21506182A JPS59105339A (en) | 1982-12-08 | 1982-12-08 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59105339A true JPS59105339A (en) | 1984-06-18 |
Family
ID=16666101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21506182A Pending JPS59105339A (en) | 1982-12-08 | 1982-12-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59105339A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61263178A (en) * | 1985-05-16 | 1986-11-21 | Agency Of Ind Science & Technol | Manufacture of superconducting integrated circuit |
JPS6225474A (en) * | 1985-07-26 | 1987-02-03 | Agency Of Ind Science & Technol | Forming method for insulating film between superconductive wirings |
-
1982
- 1982-12-08 JP JP21506182A patent/JPS59105339A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61263178A (en) * | 1985-05-16 | 1986-11-21 | Agency Of Ind Science & Technol | Manufacture of superconducting integrated circuit |
JPH0513396B2 (en) * | 1985-05-16 | 1993-02-22 | Kogyo Gijutsuin | |
JPS6225474A (en) * | 1985-07-26 | 1987-02-03 | Agency Of Ind Science & Technol | Forming method for insulating film between superconductive wirings |
JPH0513397B2 (en) * | 1985-07-26 | 1993-02-22 | Kogyo Gijutsuin |
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