JPH01147762A - synchronous memory system - Google Patents

Abstract

PURPOSE:To improve the utilization factor of a system bus and the processing capacity of a system by changing the contact point of a switch for the time of the idleness of the system bus and the time of the completion of the write-in or the read-out of data. CONSTITUTION:A signal to request to use the system bus in order to write or read data to/from a system memory 500 is outputted from processors 100-1-100-n to a bus adjusting control circuit 400. When the system bus is idle, the circuit 400 switches a switching means 600-1-600-n to a side to connect directly the system bus and the processors 100-1-100-n. Besides, when the write or the read of the data is finished, the memory 500 switches them to the side of a storing means connected to the system bus in the means 600-1-600-n. Consequently, since the memory 500 can be read or written at a speed corresponding to its access time, the utilization factor of the system bus is improved, and the processing capacity of the system can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a synchronous memory system used in a multiprocessor system as one of various arithmetic control systems such as communication, the system bus utilization efficiency and system processing capacity in the above system are improved. The aim is to provide a synchronous memory system that uses multiple processors (hereinafter referred to as CP [I]) that perform arithmetic control on data read from system memory via a system bus, and control signals from the CPU. In a system that has a bus adjustment control circuit that adjusts and controls the use of the system bus by the CPU, and a system memory that reads or allocates data using control signals from the CPU, there are two routes, and the common route is One end is connected to the system bus, the other end is connected to the contacts of the switch, one route directly connects the system bus and the contacts of the switch, and the other route has a storage means for reading and storing data stored in the system memory. The control signal from the bus adjustment control circuit causes the system bus to be connected directly to the switch contact when the system bus is free, and the storage means to be connected directly to the switch when data has been written or read in the system memory. On the inserted side, a switching means for switching the contacts of the switch is inserted between the system bus and the CPU.

[Industrial application field]

The present invention relates to an improvement of a synchronous memory system used in a multiprocessor system as one of various arithmetic control systems such as communication.

At this time, there is a need for a synchronous memory system that improves the utilization efficiency of the system bus and the processing capacity of the system in the above system.

[Conventional technology]

FIG. 6 is a block diagram of a conventional synchronous memory system.

FIG. 7 is a time chart explaining the operation of the conventional example.

In the synchronous memory system used in the multiprocessor system shown in FIG.
-m- shares the system memory 5.

Each CPU connected to the local bus uses the system memory 5 after acquiring the right to use the system bus by each bus acquisition control circuit 2-1, 2-2, -m-. At this time, adjustment control is required to obtain the right to use the system bus, so a bus adjustment control circuit 4 is provided.

For example, when the CPU 1-1 writes data to the system 5 via the system bus, the CPU 1-1 sends a request signal RE to use the system bus via the bus acquisition control circuit 2-1. and transfers it to the bus adjustment control circuit 4 (see Figure 7).The bus adjustment control circuit 4 always monitors the usage status of the system bus, and when it receives the above REQI, it grants permission to use the system bus if it is free. The signal OKI (“l”) is transferred to CPUl-1 via the bus acquisition control circuit 2-1.
Immediately upon receiving the address or data to be written, it is transferred to the system memory 5 via the local bus, the bus acquisition control circuit 2-1, and the system bus.

In the system memory 5, after a certain period of time after CPU1-1 accesses, the signal CK (“0
”) is transferred to the CPU 1-1 via the system bus, the bus acquisition control circuit 2-1, and the local bus.

The CPU 1-1 receives the above CK and performs a procedure to complete the writing. This is shown in the time chart shown in FIG.

The CPUs 2-2, --- also perform the same operations as described above.

[Problem that the invention seeks to solve]

However, in the above synchronous memory system, C
Since the basic cycle of each PU is specified, there is a problem in that it is impossible to further increase the speed on the system bus.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a synchronous memory system that improves system bus utilization efficiency and system processing capacity in the above system.

[Means for solving problems]

The above problem is solved by the circuit configuration shown in FIG.

That is, in FIG. 1, a plurality of processors 100-1 to 100-n perform arithmetic control on data read from a system memory 500 via a system bus, and a system bus is controlled by a processor based on control signals from the processors. Bus adjustment control circuit 400 that performs adjustment control of the use of
600-1 to 600-n are inserted between the system bus and the processor, and have two routes, One common end is connected to the system bus, the other end is connected to the switch contacts, one route directly connects the system bus and the switch contacts, and the other route is used to read and store data stored in the system memory. By inserting a storage means to
A switching means that switches the contact of the switch to the side where the system bus and the switch contact are directly connected when the system bus is free, and to the side where the storage means is inserted when data writing or reading in the system memory is completed. .

[For production]

In FIG. 1, processors 100-1 to 100-n output a control signal to bus adjustment control circuit 400 requesting use of the system bus in order to write or read data in system memory 500.

The bus adjustment control circuit 400 outputs a system bus use permission signal when the system bus is vacant, switches the switching means 600-1 to 600-n to directly connect the system bus and the processor, and connects the system bus and the processor. Directly connected.

In the system memory 500, when data writing or reading is completed, a control signal is output, and the switching means 600-1 to 600-n switch to the storage means connected to the system bus.

Then, data is read between this storage means and the processor. Meanwhile, the system bus is freed up for use by other processors.

As a result, the system memory can be read or written at a speed commensurate with its access time, which improves system bus usage efficiency and improves system processing capacity.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a synchronous memory system according to an embodiment of the present invention.

FIG. 3 is a time chart explaining the operation of the embodiment.

FIG. 4 is a diagram showing the principle of the selector 60-1 used in the embodiment.

FIG. 5 is a principle diagram of a flip-flop changeover switch (hereinafter referred to as FF changeover switch) used in the embodiment.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, for example, when CPt1lO-1 wants to read data from the system memory 50, it outputs a read request signal to the decoder 20-1, and the decoder 20-1 outputs a read request signal to the decoder 20-1.
1 decodes this and outputs a signal CS shown as "O" in FIG. This CS signal is manually input to the priority controller 40 via the gate 21-1. The priority controller 40 constantly monitors the usage status of the system bus, and if the system bus is free, sends a usage permission signal OK shown as "0" in Figure 3 to 0E (Output) of the selector 60-1.61-1.
ut Enable) input terminal and a read/write (hereinafter referred to as R/W) control gate 22-1.

Then, in the selector 61-1, a buffer gate (not shown) made of an IC is made conductive by the OK signal. As shown in FIG. 3, the CPUs 10-1 almost always output address signals onto the local bus in preparation for use of a local memory (not shown) or the like. When the aforementioned selector 61-1 becomes conductive as shown by "O" in FIG. 3, the address signal is transferred to the system memory 50 via the system bus.

On the other hand, the gate 22-1 becomes conductive due to the OK signal, and a read control signal ("R") shown as "1" in FIG.

Furthermore, in the selector 60-1, the O input to the 0EOi child
Due to the readout control signal input to the K times signal and the T terminal,
The read side of the gate circuit shown in FIG. 4 is made conductive. This is indicated by "O" in FIG.

The FF changeover switch 62-1, whose principle is shown in FIG. 5, is always on the through side (
In other words, the side that directly connects the local bus and system bus)
It is set to . As a result, from the system memory 50 to the system bus, selector 60-1. Data is transferred to the CPU via the FF changeover switch 62-1 and the local bus.
Read 0-1.

When it becomes possible to finish reading data in the system memory 50, the signal ACK shown as "0" in FIG.
1 and FF changeover switch 62-1. As a result, game 21-1 becomes open.

This is shown as "1" in FIG. 3 (■). In addition, as shown in FIG. 30, the FF changeover switch 62-1 is
) to the FFO side (“0”). As a result, F
The data temporarily stored in the FF is transferred from the FF in the F changeover switch 62-1 to the CPU10-1 via the local bus.
Read it with . This is shown in Figure 3 (■).

(This is possible because the transfer speed of the system bus is higher than that of the local bus).

On the other hand, since the ACK signal has opened the gate 21-1, the priority controller 40 receives this and disables the gate C3).
Stop outputting the K times signal. As a result, selector 61
-1 is no longer conductive, leaving the system bus free for use by other CPUs. At the same time, the system memory 50 stores the data F as shown in FIG.
The reading to the FF in the F changeover switch is completed.

As a result, as shown in Figure 3 0 and
Reading to the FF in the changeover switch ends, but
Reading from the FF to the CPU 10-1 via the local bus continues until the basic cycle of the CPU is completed, making it possible to improve the utilization efficiency of the system bus.

Writing data from the CPU to the system memory is also performed based on the same operating principle as described above.

The same applies to reading and writing data to the system memory by other CPUs.

Note that the clock generator 1 in the CPU10-1 shown in FIG.
1-1 and φ2 shown in Figure 3 ■ are CPUl0-1
The basic cycle of In addition, the clock source 3 shown in FIG.
0 is the clock (CL
K), and is made using, for example, a crystal oscillator.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to create a synchronous memory system that improves system bus usage efficiency and system processing performance.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention. FIG. 2 is a block diagram showing the configuration of a synchronous memory system according to an embodiment of the present invention. FIG. 3 is a time chart explaining the operation of the embodiment. FIG. 5 is a principle diagram of the FF selector switch used in the embodiment. FIG. 6 is a block diagram of the configuration of a conventional synchronous memory system. FIG. 7 is a diagram of the conventional synchronous memory system. It is a time chart explaining the operation. In the figure, 100-1 to 100-n are processors, 400 is a bus adjustment control circuit, 500 is a system memory, and 600-1 to 600-n are switching means. l0θ−/t
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Claims (1)

[Claims] A plurality of processors (100-1 to 100-n) perform arithmetic control on data read from the system memory (500) via the system bus, and control of the system bus by the processors based on control signals from the processors. a bus adjustment control circuit (400) that performs usage adjustment control;
reading data according to a control signal from the processor;
Alternatively, in a system having a system memory (500) to write to, the system has two routes, one common end of which is connected to the system bus, and the other end connected to a contact of a switch, and one route is connected to the system bus. The contacts of the switch are directly connected, and a storage means for reading and storing data stored in the system memory is inserted into the other route, and a control signal from the bus adjustment control circuit is used to control when the system bus is free. A switching means (600-1) for switching the contacts of the switch on the side where the system bus and the contacts of the switch are directly connected, and on the side where the storage means is inserted when writing or reading data in the system memory is completed. 600-n) inserted between the system bus and the processor.