JPH01145891A - Manufacture of circuit substrate with solder bump - Google Patents
Manufacture of circuit substrate with solder bumpInfo
- Publication number
- JPH01145891A JPH01145891A JP30422187A JP30422187A JPH01145891A JP H01145891 A JPH01145891 A JP H01145891A JP 30422187 A JP30422187 A JP 30422187A JP 30422187 A JP30422187 A JP 30422187A JP H01145891 A JPH01145891 A JP H01145891A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- solder
- pattern
- copper
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 title abstract description 10
- 238000000034 method Methods 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 29
- 229910052802 copper Inorganic materials 0.000 abstract description 28
- 239000010949 copper Substances 0.000 abstract description 28
- 239000000463 material Substances 0.000 abstract description 6
- 238000007598 dipping method Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 238000007747 plating Methods 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 101100016026 Drosophila melanogaster GstE14 gene Proteins 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ベアICや電子部品を実装したチップオン
ボードやハイブリッド回路基板をマザーボードに、ハン
ダリフロー法等を用いて搭載する電子回路実装において
、軽薄短小を実現するための高密度表面実装に関するも
のである。[Detailed Description of the Invention] [Field of Industrial Application] This invention is applicable to electronic circuit mounting in which a chip-on-board or hybrid circuit board on which bare ICs or electronic components are mounted is mounted on a motherboard using a solder reflow method or the like. , concerning high-density surface mounting to realize lightness, thinness, and size.
本発明は、回路基板の製造工程において、従来の加工処
理技術を何ら変更することなく、回路基板上の電極パタ
ーンを貫通する穴を用いて、スルーホールを形成する中
間工程の電極銅メツキの際に生じる極小パターン電極で
の電界集中作用を利用し、スルーホール開口部周辺のパ
ターン電極部に円環状銅突起を形成し、この銅突起を芯
としてさらにこの銅突起の表面にバリヤメタル層と金メ
ツキ処理を行い、ハンダバンプを形成する回路基板の製
造方法である。また、ハンダバンプにはハンダリフロー
時にフロー性やセルフアライメント性が要求され、これ
を維持するためのハンダ量を確保する必要から、スルー
ホール内に開口部からソルダーレジストを印刷法等で充
填することも本発明に係わるハンダバンブ形成上の重要
な製造方法である。In the manufacturing process of circuit boards, the present invention can be applied to electrode copper plating, an intermediate process in which through-holes are formed using holes that penetrate electrode patterns on circuit boards, without any changes to conventional processing techniques. Utilizing the electric field concentration effect at the extremely small pattern electrode that occurs in the process, a circular copper protrusion is formed on the pattern electrode area around the through-hole opening, and a barrier metal layer and gold plating are further applied to the surface of the copper protrusion using this copper protrusion as a core. This is a method of manufacturing a circuit board in which processing is performed to form solder bumps. In addition, solder bumps are required to have flowability and self-alignment properties during solder reflow, and it is necessary to secure the amount of solder to maintain this property, so it is also possible to fill solder resist from the opening in the through hole using a printing method. This is an important manufacturing method for forming solder bumps according to the present invention.
従来は、回路基板上にハンダバンプを設けた例は見られ
ないが、近い技術としては、リードレスチップキャリア
パッケージの電極が上げられる。Conventionally, there have been no examples of providing solder bumps on circuit boards, but a similar technology includes electrodes for leadless chip carrier packages.
リードレスチップキャリア(L CC)パンケージをマ
ザーボード等の回路基板に実装し・回路接続を行うには
LCCパッケージの側面外周縁に配置された電極と、そ
れらに対向したマザーボード上の電極とをハンダ等を用
いて接続固定することが行われている。従って、LCC
パッケージでは電極数が多くなると、側面外周縁が長く
なることになり、このパンケージの平面サイズが増大す
ることになる。逆に平面サイズを抑制するためには、側
面外周縁に配設された電極ピンチを短くすることも考え
られるが、ハンダプリフジによるショートの問題があり
、容易に改善されていない。以上のごとく、LCCパッ
ケージで必要な電極数を多く得るためには、LCC回路
基板面積を側面外周縁に電極を配設するためにのみ、大
きくせざるを得ないという問題があった。また、これら
の接続固定に供される電極は側面外周縁に配されるが、
ハンダブリッジによるショートの問題があり、容易には
改善されていない。以上のごとく、リードレスチップキ
ャリアパッケージで必要な電極数を多(得るためには、
リードレスチップキャリアの回路基板面積を側面外周縁
に電極を配設するためのみで大きくせざるを得ないとい
う問題がある。To mount a leadless chip carrier (LCC) pancage on a circuit board such as a motherboard and make circuit connections, solder, etc. The connection is fixed using . Therefore, L.C.C.
As the number of electrodes increases in a package, the outer periphery of the side surface becomes longer, resulting in an increase in the planar size of the pancage. Conversely, in order to suppress the planar size, it is conceivable to shorten the electrode pinches disposed on the outer periphery of the side surfaces, but this poses the problem of short circuits due to solder prefixes, which cannot be easily solved. As described above, in order to obtain a large number of electrodes required for an LCC package, there is a problem in that the area of the LCC circuit board must be increased only in order to arrange the electrodes on the outer periphery of the side surface. In addition, the electrodes used to fix these connections are arranged on the outer periphery of the side surface,
There is a problem of short circuits caused by solder bridges, which cannot be easily resolved. As mentioned above, in order to obtain a large number of electrodes in a leadless chip carrier package,
There is a problem in that the area of the circuit board of the leadless chip carrier has to be increased only in order to arrange the electrodes on the outer periphery of the side surface.
また、これらの接続固定に供される電極はリードレスチ
ップキャリアの回路基板側面外周縁に配設することの制
約から、回路配線のレイアウトでスルーホールによるジ
ャンパー配線の多用や、外付はジャンパー線等を必要と
することになり、コストアンプが避けられず、問題とな
っていた。この発明は、LCCパッケージの側面接続電
極をキャリアすなわち回路基板の外周縁に配置しなけれ
ばならないという制約なしに、回路基板の貫通穴を用い
て、ハンダバンプを形成することにより、接続電極を回
路基板の平面内部で自由に配設することを可能ならしめ
た回路基板におけるスルーホールにハンダバンプを形成
する回路基板の製造方法に関するものである。In addition, due to the restriction of arranging the electrodes used to fix these connections on the outer periphery of the side surface of the circuit board of the leadless chip carrier, jumper wiring using through holes is often used in the circuit wiring layout, and jumper wiring is used for external wiring. etc., and the cost amplifier was unavoidable, which became a problem. This invention enables the connection electrodes to be placed on the circuit board by forming solder bumps using the through holes of the circuit board, without the restriction that the side connection electrodes of the LCC package must be placed on the outer periphery of the carrier, that is, the circuit board. The present invention relates to a method for manufacturing a circuit board in which solder bumps are formed in through holes in the circuit board, which allow solder bumps to be freely arranged within the plane of the circuit board.
本発明に係る回路基板のスルーホール開口部へハンダバ
ンプを形成する回路基板の製造方法は、ハンダハンプを
形成する貫通穴開口部の電極を平面的に小さく形成する
ことにより、スルーホール銅内壁補強を行なう電解銅メ
ツキ処理で開口部の電極に電界集中が発生し、その部分
に電解銅が盛り上がるように形成することができる。こ
のスルーホール開口部上の銅突起は、ハンダバンプとし
て重要であり、この銅突起形成後にはニッケルメッキや
金メツキを同様に処理し、ソルダーレジストを銅突起側
と逆の回路基板面から印刷で塗布すると、スルーホール
内にソルダーレジストの一部が流れ込み、これを硬化さ
せれば、バンプとしてのハンダをスルーホールの開口部
上に溜めることが可能な状態となり、さらにフラックス
塗布を行った後、ハンダディッピングを行なうと、スル
ーホール開口部にハンダバンプを形成することができる
。A method of manufacturing a circuit board according to the present invention in which a solder bump is formed in a through-hole opening of a circuit board reinforces the copper inner wall of the through-hole by forming the electrode of the through-hole opening that forms the solder hump to be small in plan view. During the electrolytic copper plating process, an electric field is concentrated on the electrode in the opening, and the electrolytic copper can be formed to swell in that area. The copper protrusions above the through-hole openings are important as solder bumps, and after the copper protrusions are formed, nickel plating or gold plating is similarly processed, and solder resist is applied by printing from the side of the circuit board opposite to the copper protrusions. Then, a part of the solder resist flows into the through hole, and if it is cured, it becomes possible to collect solder as a bump on the opening of the through hole.Furthermore, after applying flux, the solder resist is By performing dipping, solder bumps can be formed at the through-hole openings.
本発明の方法によれば、リードレスチップキャリアの特
徴である外部接続用電極を回路基板の外周縁に配置する
ことなく、回路基板内のスルーホールを用いて形成でき
る。According to the method of the present invention, external connection electrodes, which are a feature of leadless chip carriers, can be formed using through holes in the circuit board without arranging them on the outer periphery of the circuit board.
以下、本発明を図に示す実施例に基づいて説明する。図
において、1は基板材料、2は銅箔パターン、3は貫通
穴であり、無電解銅4や電解銅5をメツキ処理すると、
スルーホール10が形成される。第1図は、片面パター
ン基板の貫通穴3の開口部に電解銅メツキ処理で電極突
起6が生じ、それを覆うようにバンプとなるハンダ9が
ディッピングで形成された構造を示す断面図である。第
1図のスルーホールハンダバンプが製造される過程を第
2図の断面図で説明する。Hereinafter, the present invention will be explained based on embodiments shown in the drawings. In the figure, 1 is the substrate material, 2 is the copper foil pattern, and 3 is the through hole. When electroless copper 4 or electrolytic copper 5 is plated,
A through hole 10 is formed. FIG. 1 is a cross-sectional view showing a structure in which electrode protrusions 6 are formed at the openings of through-holes 3 of a single-sided patterned board by electrolytic copper plating, and solder 9 to serve as bumps is formed by dipping to cover the electrode protrusions 6. . The process of manufacturing the through-hole solder bump shown in FIG. 1 will be explained with reference to the sectional view shown in FIG. 2.
第2図[alは、片面パターン回路基板になる基板材料
であり、第2図(b)はハンダバンプを形成する位置に
貫通穴3をあけた基板材料で、第2図(C)は、無電解
銅4を基板全体にメツキ処理した状態であり、第2図T
dlは、パターン焼付、現像後のエッチングでパターン
が形成された状態で、この場合には非パターン側にハン
ダバンプを形成するため、貫通穴3の開口部の面積を小
さくするようにS電解銅4のパターンが形成されている
。第2図telは、無電解銅4の上に重ねて電解銅5を
メツキ処理した断面図であるが、電解銅メツキのため、
面積を小さくした貫通穴3の開口部ではメツキ浴槽内の
通電電流密度が集中し、その部分には図示したように電
解銅が突起状6に形成される。この電極突起6はハンダ
バンプの場合、対向するパターン電極にハンダリフロー
等で接合された時、ハンダバンプのハンダが対向パター
ン電極へ流れ出しても、この電極突起6は周辺の回路パ
ターンと回路配線を有したハンダバンプ基板との接触防
止の空隙を提供することが可能である重要な機能を有す
るのである。第2図(f)は電解銅5の上にニッケルメ
ッキおよび金メツキ7を処理した状態である。第2図T
g’lは、バンプのハンダ9がスルーホール10から抜
けずにスルーホール開口部電極に溜めておくために、ソ
ルダーレジスト8を非パターン側から印刷し、スルーホ
ール10の一部がソルダーレジスト8で充填された状態
である。ソルダーレジストを硬化させた後、電極突起を
含むスルーホール】O開口部にハンダをディッピングで
付着させ、フラックスを処理してリフローすると、第1
図に示すような断面形状のハンダバンプがスルーホール
開口部に形成することができる。第3図から第5図は他
の実施例の図であり、第3図(alにはパターン電極側
にソルダーレジスト8aで形成したスルーホール電極開
口部に前述の製造方法で電極突起6、ハンダバンプ9を
形成した例であり、第3図(blには非電極側に印刷し
たソルダーレジスト8b上から貫通穴をあけ、スルーホ
ールを形成し、前述の製造方法でハンダバンプを形成し
た例である。第3図に示すソルダーレジスト8aおよび
8bは、エポキシ系樹脂やラミネート樹脂フィルムを用
いても同様なハンダバンプがスルーホール開口部に形成
できる。第4図は両面パターン回路基板のスルーホール
開口部にハンダバンプを形成した例であり、スルーホー
ル10を充填するソルダーレジスト8を両面パターンの
どちらから印刷するか選択することによって、ハンダバ
ンプを回路基板表裏のどちらにも自由に形成することを
示すスルーホールハンダバンプの断面図であり、第5図
は多層基板を用いたスルーホールハンダバンプの実施例
で、その断面図を示す。第6図にはリードレスチップキ
ャリアの従来例であり、接続用の電極は回路基板の外周
縁に配設されている。Figure 2 (al) is a board material that will become a single-sided pattern circuit board, Figure 2 (b) is a board material with through holes 3 drilled at the positions where solder bumps will be formed, and Figure 2 (C) is a board material that will become a single-sided pattern circuit board. The entire board is plated with electrolytic copper 4, as shown in Figure 2T.
dl is a state in which a pattern is formed by pattern baking and etching after development, and in this case, in order to form solder bumps on the non-pattern side, S electrolytic copper 4 is used to reduce the area of the opening of the through hole 3. A pattern is formed. FIG. 2 tel is a cross-sectional view of electrolytic copper 5 plated over electroless copper 4, but because of electrolytic copper plating,
At the opening of the through-hole 3 whose area is reduced, the current density flowing inside the plating bath is concentrated, and electrolytic copper is formed in the shape of a protrusion 6 in that area as shown. If this electrode protrusion 6 is a solder bump, when it is joined to an opposing pattern electrode by solder reflow etc., even if the solder of the solder bump flows out to the opposing pattern electrode, this electrode protrusion 6 will have the surrounding circuit pattern and circuit wiring. It has an important function of providing a gap to prevent contact with the solder bump substrate. FIG. 2(f) shows a state in which nickel plating and gold plating 7 have been applied on the electrolytic copper 5. Figure 2 T
In order to keep the solder 9 of the bump from coming out of the through-hole 10 and to collect it in the through-hole opening electrode, the solder resist 8 is printed from the non-patterned side, and a part of the through-hole 10 is covered with the solder resist 8. It is filled with. After hardening the solder resist, attach solder to the through-hole including the electrode projection by dipping, process flux, and reflow.
A solder bump having a cross-sectional shape as shown in the figure can be formed at the through-hole opening. 3 to 5 are views of other embodiments, and in FIG. FIG. 3 (bl) shows an example in which a through hole is formed from above the solder resist 8b printed on the non-electrode side, and a solder bump is formed by the above-mentioned manufacturing method. The solder resists 8a and 8b shown in Fig. 3 can be used to form similar solder bumps at the through-hole openings even if epoxy resin or laminated resin film is used. This is an example of forming a through-hole solder bump, which shows that solder bumps can be freely formed on either the front or back of the circuit board by selecting which side pattern to print the solder resist 8 filling the through-hole 10 from. Fig. 5 shows a cross-sectional view of an example of a through-hole solder bump using a multilayer board. Fig. 6 shows a conventional example of a leadless chip carrier, in which the connecting electrodes are connected to a circuit board. It is arranged on the outer periphery of the
〔発明の効果〕
本発明の製造方法によれば、回路基板にスルーホールを
設けることにより、容易にスルーホール開口部にハンダ
バンプが形成でき、従来回路基板の外周縁部に限定され
ていた接続用電極を回路基板の内部に設けることができ
、電極数も回路基板の面積を大きくすることな(、増設
することができる。すなわちリードレスチップキャリア
での高密度多ピン化の効果が得られる。またプラスチッ
クピングリッドアレイパッケージにおいて金属ピンを本
発明のスルーホールハンダバンプに置き換えれば、大幅
なコストダウンが可能となり、品質上ではピン曲がり等
の問題が解決されるという大きな効果が得られる。[Effects of the Invention] According to the manufacturing method of the present invention, by providing a through hole in a circuit board, solder bumps can be easily formed at the openings of the through holes, and solder bumps can be easily formed at the openings of the through holes, which can be used for connections that were conventionally limited to the outer periphery of the circuit board. The electrodes can be provided inside the circuit board, and the number of electrodes can be increased without increasing the area of the circuit board. In other words, the effect of increasing the number of pins in a leadless chip carrier can be achieved. Furthermore, if metal pins in a plastic pin grid array package are replaced with the through-hole solder bumps of the present invention, it is possible to significantly reduce costs, and there is a significant effect in terms of quality in that problems such as pin bending are solved.
第1図は片面パターン回路基板のスルーホールハンダバ
ンプの断面図、第2図(alから(幻までは第1図にお
けるハンダバンプの製造方法を示す断面図、第3図(a
)及び(blはパターン電極側に形成されたスルーホー
ルハンダバンプの断面図、第4図は両面パターン回路基
板の断面図、第5図は少なくとも3N以上の多層回路基
板の断面図を示すものである。第6図は従来のリードレ
スチップキャリアの斜視図である。 ゛
1・・・・基板材料
2・・・・銅箔パターン
3・・・・貫通穴
4・・・・無電解メッキ銅
5・・・・電解メッキ銅
6・・・・電極突起
7・・・・ニッケルメッキおよび金メッキ8・・・・ソ
ルダーレジスト
8a、 8b・・ソルダーレジスト又はエポキシ樹脂又
はラミネート樹脂フィルム
9・・・・ハンダ
10・・・・スルーホール
以上
出願人 セイコー京葉工業株式会社
本宛哨171設遣方法δ示T藺面図
第2図
1t!、の亥lき例の面画図
第3図
tI7′l冥絶例のぼ1面図
弔4図
1i!のX犯1rlのI!I′r面図
第5図
促釆?1力#+視図
第6図Figure 1 is a cross-sectional view of a through-hole solder bump on a single-sided pattern circuit board, Figure 2 (al to
) and (bl are cross-sectional views of through-hole solder bumps formed on the pattern electrode side, FIG. 4 is a cross-sectional view of a double-sided pattern circuit board, and FIG. 5 is a cross-sectional view of a multilayer circuit board of at least 3N or more. 6 is a perspective view of a conventional leadless chip carrier. ゛1...Substrate material 2...Copper foil pattern 3...Through hole 4...Electroless plated copper 5 ... Electroplated copper 6 ... Electrode protrusion 7 ... Nickel plating and gold plating 8 ... Solder resist 8a, 8b ... Solder resist or epoxy resin or laminated resin film 9 ... Solder 10...Through hole or above Applicant: Seiko Keiyo Kogyo Co., Ltd. Main address 171 installation method Example Nobo 1 side view Condolence 4 Figure 1i! X criminal 1rl's I!
Claims (1)
、回路パターン上にスルーホールを形成する工程と、前
記スルーホールの片側の開口部で、前記スルーホールを
取り囲むように電極突起を形成する工程と、前記開口部
に対向するスルーホール開口部をソルダーレジストで充
填する工程と、前記電極突起にハンダを覆う工程とから
なる事を特徴とするハンダバンプ付き回路基板の製造方
法。In a circuit board having a pattern on at least one side, a step of forming a through hole on a circuit pattern, a step of forming an electrode protrusion at an opening on one side of the through hole so as to surround the through hole, and a step of forming an electrode projection on one side of the through hole; 1. A method for manufacturing a circuit board with solder bumps, comprising the steps of: filling a through-hole opening facing the solder resist with solder resist; and covering the electrode protrusion with solder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62304221A JP2548584B2 (en) | 1987-12-01 | 1987-12-01 | Method for manufacturing circuit board with solder bumps |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62304221A JP2548584B2 (en) | 1987-12-01 | 1987-12-01 | Method for manufacturing circuit board with solder bumps |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01145891A true JPH01145891A (en) | 1989-06-07 |
JP2548584B2 JP2548584B2 (en) | 1996-10-30 |
Family
ID=17930466
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62304221A Expired - Fee Related JP2548584B2 (en) | 1987-12-01 | 1987-12-01 | Method for manufacturing circuit board with solder bumps |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2548584B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06350256A (en) * | 1993-06-11 | 1994-12-22 | Nec Corp | Printed wiring board having non-through hole and production of thereof |
JPH0738008A (en) * | 1993-06-25 | 1995-02-07 | Matsushita Electric Works Ltd | Chip carrier |
JPH08167789A (en) * | 1994-12-12 | 1996-06-25 | O K Print:Kk | Ic chip carrier |
JPH08250619A (en) * | 1995-03-09 | 1996-09-27 | Nec Corp | Semiconductor device |
WO1998047179A1 (en) * | 1997-04-11 | 1998-10-22 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
US6199273B1 (en) | 1995-12-19 | 2001-03-13 | Sumitomo Metal Industries, Ltd. | Method of forming connector structure for a ball-grid array |
-
1987
- 1987-12-01 JP JP62304221A patent/JP2548584B2/en not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06350256A (en) * | 1993-06-11 | 1994-12-22 | Nec Corp | Printed wiring board having non-through hole and production of thereof |
JPH0738008A (en) * | 1993-06-25 | 1995-02-07 | Matsushita Electric Works Ltd | Chip carrier |
JPH08167789A (en) * | 1994-12-12 | 1996-06-25 | O K Print:Kk | Ic chip carrier |
JPH08250619A (en) * | 1995-03-09 | 1996-09-27 | Nec Corp | Semiconductor device |
US6199273B1 (en) | 1995-12-19 | 2001-03-13 | Sumitomo Metal Industries, Ltd. | Method of forming connector structure for a ball-grid array |
WO1998047179A1 (en) * | 1997-04-11 | 1998-10-22 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
US6228466B1 (en) | 1997-04-11 | 2001-05-08 | Ibiden Co. Ltd. | Printed wiring board and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JP2548584B2 (en) | 1996-10-30 |
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