JP3777687B2 - Chip carrier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In the present invention, one or a plurality of semiconductor integrated circuit elements (hereinafter referred to as chips) are mounted, and a chip carrier used for connecting to a printed wiring board, in particular, a connection terminal to the printed wiring board is provided on the surface. The present invention relates to a chip carrier having an arranged BGA (ball grid array) structure.
[0002]
[Prior art]
In order to meet the demand for miniaturization of electronic equipment, a method of mounting a semiconductor device on which a chip is mounted on the surface of a printed wiring board has been adopted. Conventionally, QFP (quad flat package) is mentioned as a typical surface mount chip carrier.
[0003]
In the QFP, a chip 51 and an inner lead 52 of a lead frame are connected to each other by a wire bonding or the like with a gold wire 54 inside the package, and a region including the chip 51 is molded with a resin 55 to form a package, and leads from four sides thereof This is a semiconductor package in which the outer lead 53 of the frame is pulled out, the lead is formed in a gull wing shape, and connected to an external circuit, and is most widely used (see FIG. 6).
[0004]
In recent years, in the field of ASICs such as gate arrays, the number of chip terminals tends to increase, but there is a high demand for package size at the current level or reduction. For this reason, the pitch of the outer leads is in a direction narrowing from 0.5 mm to 0.3 mm. With QFP having an outer lead pitch of 0.3 mm, it is said that problems such as solder bridges occur and mounting on external connection terminals such as a printed wiring board becomes difficult.
[0005]
Recently, a BGA type semiconductor device has been devised in which ball-like external connection terminals are arranged in a matrix in the plane of the substrate.
[0006]
As shown in FIG. 5, a general BGA type chip carrier has a copper-clad laminate (bismaleimide / triazine resin, so-called BT resin resin, etc.) on both surfaces of a printed circuit board. , Copper foil bonded together) is used as a base substrate, and a wiring circuit comprising a conductor wiring layer 32, a thin film insulating layer 35, and a conductor wiring layer 32 is formed on one side, and a chip 38 is mounted on the top layer and a gold wire. 39 is connected to each electrode pad by wire bonding. Solder balls 42 are formed on the opposite surface of the base substrate.
[0007]
In particular, a method for forming a thin film multilayer wiring layer portion will be described in more detail. A conductive layer formed on both surfaces of the insulating substrate 31 is patterned by a photo-etching method to form a conductive wiring layer 32 and a solder pad 33, and then a photosensitive resin is coated on the conductive wiring layer 32 to coat the photosensitive insulating layer. The thin film insulating layer 35 having via hole formation holes for conducting the conductive layer between the upper and lower sides is formed by performing exposure and development processes. Next, a conductor layer and a via hole 37 are formed on the thin film insulating layer 35 by plating, and the conductor layer is patterned to form a second conductor wiring layer 36. Further, when multilayering is necessary, the same process is repeated.
[0008]
Next, a process of mounting a chip on the chip carrier obtained by the above method to obtain a semiconductor device will be described. First, after the chip 38 is mounted and wire bonding is performed with the gold wire 39, the chip carrier upper surface portion is sealed with the mold resin 40. On the lower surface, solder balls are arranged on the solder pads 33, and the solder balls 42 are formed by a reflow furnace.
[0009]
[Problems to be solved by the invention]
In recent years, the operating speed of the chip to be mounted has been improved, and for the purpose of reducing inductance, the chip carrier electrode 23 formed on the multilayer wiring board and the chip electrode 25 on the chip 24 are brought into direct contact as shown in FIG. Thus, flip-chip mounting is performed in which the adhesive layer 22 on the insulating layer 21 and the protective layer 26 on the chip 24 are bonded and fixed for electrical connection.
[0010]
However, when flip chip mounting is performed, if there are variations in the height of the chip carrier electrode, an electrode that can be stably connected and an electrode that cannot be connected stably, or an electrode that cannot be connected, will appear. There arises a problem that the connection reliability is significantly lowered.
[0011]
The present invention is intended to solve the above-described problem, and an object of the present invention is to improve electrical connection reliability between a chip carrier electrode and a chip electrode at the time of flip chip mounting in a chip carrier.
[0012]
[Means for Solving the Problems]
In order to achieve the above object in the present invention, first, in claim 1, a semiconductor integrated circuit element is mounted on one side of a multilayer wiring board formed by alternately laminating insulating resin layers and conductor wiring patterns, and the multilayer wiring board. In the chip carrier in which solder balls for connecting to an external circuit are formed on the opposite surface, the mounting surface of the semiconductor integrated circuit element is composed of an adhesive layer (9) and an electrode portion (10). The at least one conductor layer (7) extends in the horizontal direction from the electrode part (10) and is electrically connected from the end part to the lower conductor wiring pattern (3).
[0013]
Furthermore, in claim 1 , the conductor layer (7) extending in the horizontal direction is composed of two conductor layers (7a, 7b) of different metals, and the conductor layer (7b) on the semiconductor integrated circuit element mounting side is formed. The linear expansion coefficient is larger than that of the other conductor layer (7a).
[0014]
Furthermore, in claim 2 , the elastic modulus of the lower insulating resin layer (9) of the conductor layer (7) extending in the horizontal direction is set to 10 ⁶ to 10 ⁸ Pa at room temperature.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The chip carrier of the present invention will be described in detail with reference to FIG. 1, FIG. 2, and FIG.
In the structure in the vicinity of the chip carrier electrode part connected to the chip electrode, the conductor layer 7 extends in the horizontal direction from the lower part of the electrode part 10, and is further connected to the lower conductor wiring pattern 3 and the via hole 8 at the end part. Yes. Further, the insulating resin layer 5 below the conductor layer 7 extending in the horizontal direction has rubber elasticity as compared with the other insulating resin layers 1. More specifically, the elastic modulus is 10 ⁶ to 10 ⁸ Pa at room temperature. desirable.
[0016]
By adopting this structure, when connecting to the chip electrode, the conductor layer 7 acts as a spring with the end of the conductor layer 7 as a fulcrum, so that it acts as a force that constantly pushes up the chip electrode at the electrode portion 10. Even if there is a variation in the height, the reliability of electrical connection with all the electrodes of the chip can be improved.
[0017]
The conductor layer 7 is not limited to extending in one direction as shown in FIG. 2, and can be provided in two directions, four directions, or more. In the case of two or more directions, each is connected to a lower conductor wiring pattern of a via hole connected to each end. As a result, the end portions of the respective conductor layers extending in two or more directions serve as springs, so that the contact pressure with the chip electrode is increased and the electrical connection reliability can be improved.
[0018]
The chip is fixed by the adhesive layer 9 on the chip carrier surface layer. By using a thermoplastic adhesive as the adhesive, the mounted chip can be easily repaired. The conductor layer 7 is composed of two conductor layers (7a, 7b) of dissimilar metals, and the coefficient of linear expansion of the conductor layer 7a on the chip mounting side of the two conductor layers (7a, 7b) is opposite. The larger conductor layer 7b is used. If this structure is taken, the force which warps to the opposite side to a chip mounting surface will be added by the heating at the time of fixing a chip | tip, and it can fix a chip | tip more stably. Furthermore, since a reverse force is applied when the temperature is returned to room temperature, it becomes possible to further stabilize the connection between the electrode having a variation in height and the electrode of the chip.
[0019]
Since the conductor layer 7 can be formed by plating, a metal that can be plated can be selected. As the combination of the upper layer and lower layer metals, zinc and copper, zinc and nickel, etc. are optimal.
[0020]
【Example】
Hereinafter, the present invention will be specifically described by way of examples.
A 200 μm through hole was formed in a 100 μm thick double-sided copper-coated polyimide film 1 with a mold, and electroless copper plating and electrolytic copper plating were applied to form a through hole 4 to establish conduction between the upper and lower copper foils. Furthermore, about 5 μm of photoresist PMER was applied to both sides, and prebaked at a predetermined temperature. Through a photomask having a pad pattern connected to the inner wiring layer on the front side and solder balls on the back side, exposure was performed at an exposure amount of 500 mJ / cm ² and development was performed with a dedicated developer to form a resist pattern. . After the post-baking at a predetermined temperature, the copper foil at portions other than the resist pattern was etched with a ferric chloride solution at 50 ° C. to form the solder pad 2 and the conductor wiring pattern 3 (FIG. 3A )reference).
[0021]
On the upper surface of the substrate, a thermosetting epoxy resin liquid in which a rubber component was previously added and an elastic modulus was adjusted to 10 ⁸ Pa at room temperature was coated and cured at a predetermined temperature to form an insulating resin layer 5 (see FIG. 3 (b)).
[0022]
Further, a via hole forming hole 6 of 50 μmφ was formed at a predetermined position of the insulating resin layer 5 with an excimer laser processing machine (see FIG. 3C).
[0023]
Next, the surface of the insulating resin layer 5 was roughened by immersing the substrate in an oxidizing agent solution containing 70 g / l of potassium permanganate and 40 g / l of sodium hydroxide. Furthermore, after applying electroless plating, a conductor layer 7a having a thickness of about 10 μm was formed by electrolytic copper plating. Further, galvanization was performed on the conductor layer 7 a to form a conductor layer 7 b having a thickness of about 10 μm, and the conductor wiring pattern 3 and the via hole 8 were electrically connected. Thereafter, patterning was performed by photoetching to form a conductor layer 7 (see FIG. 3D).
[0024]
Furthermore, the upper surface was coated with a heat-resistant thermoplastic adhesive HIMARU (manufactured by Hitachi Chemical Co., Ltd.) to form an adhesive layer 9 having a thickness of about 30 μm. Further, an opening of 50 μmφ was formed at a predetermined position by an excimer laser processing machine. Thereafter, the electrode part 10 was formed by performing electrolytic copper plating on the opening using the solder pad 2 as a plating electrode (FIG. 3E).
[0025]
【The invention's effect】
As described above, according to the present invention, the horizontal conductor layer leading to the chip carrier electrode portion is formed as a two-layer conductor layer made of a dissimilar metal, thereby acting as a force for constantly pushing up the chip electrode at the electrode portion 10, Even if the height of the electrode part 10 varies, electrical contact between the chip electrode and the chip carrier electrode is performed, and electrical connection reliability with all the electrodes of the chip can be improved.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view showing a configuration of an embodiment of a chip carrier of the present invention.
FIG. 2A is a top view showing an electrode portion 10 and a conductor layer 7 of an embodiment of a chip carrier of the present invention. (B)-(c) is a top view which shows the electrode part 10 and conductor layer of the other Example of the chip carrier of this invention.
FIGS. 3A to 3E are partial cross-sectional views showing a manufacturing method of an embodiment of a chip carrier of the present invention. FIGS.
FIG. 4 is a partial cross-sectional view showing a configuration of a conventional chip carrier (flip chip).
FIG. 5 is a partial cross-sectional view showing a configuration of a conventional chip carrier (BGA).
FIG. 6 is a cross-sectional view showing a configuration of a conventional chip carrier (QFP).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Insulating resin layer 2 ... Solder pad 3 ... Conductor wiring pattern 4 ... Through hole 5 ... Insulating resin layer 6 ... Via-hole formation hole 7 ... Conductor layer 7a ... Conductor layer 7b with a large linear expansion coefficient …… Conductor layer 8 with small linear expansion coefficient ...... Via hole 9 ...... Adhesive layer 10 ...... Electrode part 21 ...... Insulating resin layer 22 ...... Adhesive layer 23 ...... Chip carrier electrode 24 ...... Chip 25 …… Chip Electrode 26 ... Protective layer 31 ... Insulating substrate 32 ... Conductor wiring layer 33 ... Solder pad 34 ... Through hole 35 ... Thin film insulating layer 36 ... Second conductor wiring layer 37 ... Via hole 38 ... Chip 39 ... Gold wire 40 ... Mold resin 41 ... Insulating part 42 around solder pad ... Solder ball 51 ... Chip 52 ... Inner lead 53 ... Outer lead 54 ... Gold wire 55 ... Resin

Claims (2)

A semiconductor integrated circuit element is mounted on one side of a multilayer wiring board formed by alternately laminating insulating resin layers and conductor wiring patterns. On the opposite side of the multilayer wiring board, a solder ball for connecting to an external circuit is planar. In the chip carrier formed on the semiconductor integrated circuit device, the mounting surface of the multilayer wiring board of the semiconductor integrated circuit element includes an adhesive layer (9) and an electrode portion (10) penetrating the adhesive layer . At least one or more conductor layers (7) extend in the horizontal direction along the lower surface of the adhesive layer from the lower part, and from the end where the conductor layers extend in the horizontal direction to the lower conductor wiring pattern (3). The conductor layer (7) that is electrically conductive and extends in the horizontal direction is composed of two conductor layers (7a, 7b) made of different metals, and the semiconductor integration of the two conductor layers made of different metals. Linear expansion of the conductor layer (7b) on the circuit element mounting side Chip carrier, wherein the number is large compared with that of the other conductor layer (7a). The multilayer wiring board further includes an insulating resin layer adjacent to the adhesive layer below the conductor layer (7) extending in the horizontal direction, and the elastic modulus of the insulating resin layer is 10 ⁶ to 10 ⁸ at room temperature. The chip carrier according to claim 1, wherein the chip carrier is Pa.

Images