JPH01140643A - Semiconductor device - Google Patents

Abstract

PURPOSE:To evade the intersection of internal wirings and the increase of wiring length, by forming an active element on a GaAs layer epitaxially grown on an Si or Ge substrate of low resistance, and constituting a wiring member to supply a specific potential to the element by using the Si substrate. CONSTITUTION:After a semi-insulative GaAs layer 2 is epitaxially grown on an Si substrate 1 of low resistance, and an element like an FET is formed, a vial hole is opened, and the surface region of the GaAs layer 2 and the substrate are connected by a metal layer 3. On the GaAs layer 2, the metal layer is connected to. e.g., the source electrode of the FET. When the Si substrate is connected to ground potential, it is supplied to the source of the FET, too. As a result, the Si substrate operates as a wiring member to supply the ground potential to the source of each FET. Thereby enabling the back surface connection, evading the intersection of wiring, and reducing parasitic capacitances between electrodes.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to the wiring structure of GaAs LSI, and aims to avoid intersections of internal wiring and increase in wiring length. A layer is provided, an active element such as an FET is formed on the GaAs layer, and a specific potential wiring body to the element is formed of an St substrate. The specific potential is, for example, ground potential.

[Industrial application field]

Although the number of elements constituting a GaAs integrated circuit (LSI) has been steadily increasing in recent years, as chips become larger, the length of wiring becomes unavoidable.

When the wiring length becomes large, a delay occurs in signal transmission, which impedes high-speed operation of the device.

In order to avoid this, efforts have been made to miniaturize elements and wiring patterns and reduce chip size, but it is also desirable to take other effective measures. As one such countermeasure, it has been proposed to form part of the wiring on the back surface of the semiconductor substrate. This is intended to reduce the area of the wiring formation region and to avoid unnecessary coupling at wiring intersections.

However, it is very difficult to embody such a structure using a normal semiconductor substrate. That is, since the thickness of a GaAs substrate on which semi-insulating GaAsji is epitaxially grown is 400 to 500 um, it is difficult to form a small-diameter via hole penetrating it, and furthermore, it is difficult to form a small diameter via hole through it. It is also difficult to electrically connect the front and back surfaces of the substrate. Increasing the diameter of the via hole would make these tasks easier, but it would not be compatible with the intended purpose of reducing the wiring length.

It may be possible to achieve the above structure by reducing the thickness of the chip including the substrate, but if the thickness of a crystal that easily creases, such as GaAs, is reduced to less than 100 μm, the mechanical strength would be insufficient, so it would be difficult to achieve this during the process. Not only do wafers frequently break, but even if an LSI chip is completed, it may be damaged during use, resulting in a lack of reliability.

(Prior art) As a semiconductor device with wiring provided on the back side of a substrate, GaAs
There is an amplification device using a FET with a simple configuration, in which the source electrode of the FET is provided with a backside connection through which W is connected to the substrate.

In this device, the source electrode to which the back surface connection is formed has a relatively large area, and the through hole is formed by anisotropic etching, so the size of the opening on the back side is also large.

The purpose of employing backside connection in this device is to avoid wiring crossings and to reduce parasitic capacitance between electrodes.

[Problem that the invention seeks to solve]

As already mentioned, it is difficult to realize backside wiring with the same board structure as before. Furthermore, an increase in the number of steps for forming a wiring layer on the back side is also unavoidable.

An object of the present invention is to provide a back wiring type semiconductor device which has sufficient mechanical strength and is free from problems in process operations.

[Means for solving problems]

To achieve the above object, in the semiconductor device of the present invention, an active element is formed in a low impurity concentration GaAs layer epitaxially grown on a low resistance Si or Ge single crystal substrate, and the active element is supplied with a specific voltage. The electrode has a structure in which it is connected to the low resistance Si or Ge single crystal substrate by an i-electric body provided through the GaAsJi.

In the embodiment, the Si substrate connects the ground potential to each FET.
It functions as a wiring body for supplying to the source.

[For production]

By providing the ground wiring on the back side of the element formation layer as in the embodiment, the wiring area on the front side is reduced and the wiring length is reduced. Furthermore, since crossing wiring can be eliminated, the wiring formation process on the front side is simplified and parasitic capacitance is also reduced.

〔Example〕

FIG. 1 is a schematic cross-sectional view showing the basic structure of the present invention.

In the diagram, 1 is a low resistance Si substrate, on which semi-insulating Q a A s q 2 is epitaxially grown. After forming elements such as FETs on the GaAsJI, via holes are opened and G
The aAs layer surface region and the substrate are electrically connected.

On the upper surface of the GaAs layer, the metal layer is connected to, for example, the source electrode of the FET, so when the Si substrate is connected to the ground potential, the ground' potential is also supplied to the source of the FET. If the resistivity of the Si substrate is as low as about 10<-4 >[Omega], the variation in source potential due to changes in operating current is negligible and causes no problem in the operation of the integrated circuit.

The ohmic electrode for through connection is made by laminating Ti and Au, for example.

3i and GaAs have slightly different lattice constants, so conventionally S
Although it was considered difficult to epitaxially grow G and aAs on an i-substrate, recent advances in crystal growth technology have made it possible to epitaxially grow this combination. Note that in the case of a Ge substrate, epitaxial growth is conventionally possible since the lattice constant is similar to that of GaAs.

FIG. 3 shows an embodiment in which the present invention is applied to the three-man power NOR circuit shown in FIG. 2. Fat of the cough layer is a plan view showing the layout, and its YY' cross section is schematically shown in figure fb1. Since the NOR circuit is well known, its explanation will be omitted.

1 in the figure is a Si substrate containing e(P) of I A semi-insulating GaAs layer 2 having a thickness of 2 is epitaxially grown, and an Mg3 type FET is formed in the core layer.

In the figure, 5 is a source region of the FET, 6 is a drain region, and 7 is a gate electrode having a Schottky barrier. The method for forming each of these regions is based on known techniques.

In addition, 3 is an ohmic electrode that connects the source of the selected FET and the Si substrate, and 4 is an FET as in a normal device.
ET's S/D? This is an ohmic electrode provided in the IN region. The latter ohmic electrode is connected to a predetermined node or power source by a wiring 8 on the front side, as shown in the plan view fa1.

In this example, the sources of the three FETs that receive logic inputs are connected to a low-resistance Si substrate by ohmic electrodes penetrating the GaAs layer, and the Si substrate is connected to the back wiring. is formed.

〔Effect of the invention〕

FIG. 4 shows a layout when the NOR circuit of FIG. 2 is formed using the conventional technology and the same design rules.

ta+ in the same figure is a plan view, (bl is its zz' cross section. This is a well-known structure formed by a well-known technique, so the explanation is omitted, but as is clear from the comparison with this, the third In the figure, the pattern size is reduced. Note that a GaAs substrate 1' is used here.

As explained above, the present invention substantially realizes a semiconductor device having backside wiring, but it is only by using Si or Ge that the substrate can be made into a wiring body by lowering its resistance. It becomes possible,
If a GaAs substrate is used as in the conventional device, it is not possible to achieve a sufficiently low resistance, and it cannot be expected to be used as a wiring body for supplying a ground potential.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional schematic diagram showing the basic structure of the present invention, Fig. 2 is a wiring diagram showing a NOR circuit, Fig. 3 is a schematic diagram showing the structure of a NOR circuit according to the present invention, and Fig. 4 is a NOR circuit according to the prior art. This is a schematic diagram showing the structure of the circuit. In the figure, ■ is a Si substrate, 1' is a GaAs substrate, 2 is a GaAs layer, 3.4 is an ohmic electrode, 5 is a source, 6 is a drain, and 7 is a gate electrode. , 8 is a wiring body, and 9 is an insulating film.

Claims (1)

[Claims] An active element is formed in a low impurity concentration GaAs layer epitaxially grown on a low resistance Si or Ge single crystal substrate, and an electrode of the active element to which a specific voltage is supplied is formed of the GaAs layer. A semiconductor device, characterized in that the semiconductor device is connected to the low resistance Si or Ge single crystal substrate by a conductor provided through the layers.