JP2550623B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a wiring structure of a GaAs LSI, and a GaAs active layer epitaxially grown on a low resistance Si (or Ge) substrate for the purpose of avoiding crossing of internal wiring and increase of wiring length. Is provided, an active element such as a FET is formed on the GaAs layer, and a specific potential wiring body to the element is constituted by a Si substrate. The specific potential is, for example, the ground potential.

[Industrial applications]

The number of elements that make up GaAs integrated circuits (LSI) has been increasing in recent years, but with the increase in size of chips, the increase in wiring length is inevitable. When the wiring length becomes long, signal transmission is delayed, which hinders high-speed operation of the device.

In order to avoid this, miniaturize the element and wiring pattern,
Although chip sizes are being reduced, it is desirable that other effective measures be taken in conjunction therewith. As one of such measures, it has been proposed to form a part of the wiring on the back surface of the semiconductor substrate. This reduces the area of the wiring formation region and tries to avoid the generation of unnecessary coupling at the wiring intersection.

However, it is very difficult to embody such a structure using a normal semiconductor substrate. That is, since a substrate obtained by epitaxially growing a semi-insulating GaAs layer on a GaAs substrate has a thickness of 400 to 500 μm, it is difficult to form a via hole having a small diameter penetrating the substrate, and a conductor is formed in the via hole. It is also difficult to fill and electrically connect both sides of the substrate. If the diameter of the via hole is increased, these operations will be easier, but they will not meet the intended purpose of reducing the wiring length.

It is possible to realize the above structure by reducing the thickness of the chip including the substrate, but if a crystal such as GaAs, which is easy to cleave, has a thickness of 100 μm or less, the mechanical strength is insufficient, so that the process Of course, the wafer is frequently damaged, and even if the LSI chip is completed, it may be damaged during use, resulting in unreliability.

[Conventional technology]

As a semiconductor device with wiring on the back surface of the substrate, GaAsFE
There is a simple amplification device using T, in which the source electrode of the FET is provided with a backside connection penetrating the substrate. In this device, the source electrode, which is the target for forming the back surface connection, has a relatively large area, and the through hole is formed by anisotropic etching, so the size of the opening on the back surface side is also large.

The purpose of adopting the backside connection in the device is to avoid crossing of the wiring and to reduce the parasitic capacitance between the electrodes.

[Problems to be solved by the invention]

As described above, it is difficult to realize the back wiring with the same substrate structure as the conventional one. Further, an increase in the number of steps for forming the wiring layer on the back side is inevitable.

An object of the present invention is to provide a backside wiring type semiconductor device which has sufficient mechanical strength and has no problem in process work.

[Means for solving problems]

To achieve the above object, in the semiconductor device of the present invention, an active element is formed in a low impurity concentration GaAs layer epitaxially grown on a low resistance Si or Ge single crystal substrate, and the active element is supplied with a specific voltage. The electrode has a structure in which it is connected to the low-resistance Si or Ge single crystal substrate by a conductor provided through the GaAs layer.

In the embodiment, the Si substrate functions as a wiring body for supplying the ground potential to the source of each FET.

[Action]

By providing the ground wiring on the back surface of the element forming layer as in the embodiment, the wiring area on the front surface side is reduced and the wiring length is reduced. Further, since the cross wiring can be eliminated, the wiring formation process on the front surface side is simplified and the parasitic capacitance is also reduced.

〔Example〕

 FIG. 1 is a schematic sectional view showing the basic structure of the present invention.

In the figure, 1 is a low resistance Si substrate, on which a semi-insulating GaAs layer 2 is epitaxially grown. The Ga
After a device such as a FET is formed in the As layer, a via hole is opened and the metal layer 3 electrically connects the GaAs layer surface region to the substrate.

Since the metal layer is connected to the source electrode of the FET, for example, on the upper surface of the GaAs layer, when the Si substrate is connected to the ground potential, the ground potential is also supplied to the source of the FET. If the specific resistance of the Si substrate is a low value of about 10 ⁻⁴ Ωcm, the fluctuation of the source potential due to the change of the operating current is negligible, and there is no problem in the operation of the integrated circuit. The ohmic electrode for through connection is, for example, a stack of Ti and Au.

Since Si and GaAs have slightly different lattice constants, it has been conventionally difficult to epitaxially grow GaAs on a Si substrate, but recent advances in crystal growth technology have enabled epitaxial growth of this combination. Note that
In the case of a Ge substrate, since the lattice constant is close to that of GaAs, epitaxial growth has been possible conventionally.

FIG. 3 shows an embodiment in which the present invention is applied to the 3-input NOR circuit shown in FIG. (A) of the drawing is a plan view showing the layout, and the YY 'cross section is schematically shown in (b). Since the NOR circuit is well known, its explanation is omitted.

1 in the figure contains the neighbor (P) of 1 × 10 ²¹ cm ^-3 as an impurity
It is a Si substrate, the specific resistance is about 2 × 10 ⁻⁴ Ωcm, the substrate surface is (100), and the semi-insulating GaAs layer 2 having a thickness of about 3 μm is epitaxially grown on the substrate. To ME
An S-type FET is formed.

In the figure, 5 is a source region of the FET, 6 is a drain region, and 7 is a gate electrode having a Schottky barrier. The method for forming each of these regions is based on a known technique. Also, 3 was selected
An ohmic electrode connecting the source of the FET and the Si substrate, and 4 is an ohmic electrode provided in the S / D region of the FET, as in a normal device. The latter ohmic electrode is connected to a predetermined node or power source by a wiring 8 on the front surface side, as shown in the plan view (a).

In this embodiment, as clearly shown in (b), the sources of the three FETs receiving the logic input are connected to the low-resistance Si substrate by ohmic electrodes penetrating the GaAs layer,
The Si substrate forms the backside wiring.

〔The invention's effect〕

FIG. 4 shows a layout in the case where the NOR circuit of FIG. 2 is formed by the conventional technique according to the same design rule.
9A is a plan view, and FIG. 9B is its ZZ ′ cross section. Since this is a well-known structure formed by a well-known technique, description thereof will be omitted, but as is apparent from comparison with this, the pattern size of FIG. 3 has been reduced. The GaAs substrate 1'is used here.

As described above, according to the present invention, a semiconductor device substantially having a back wiring is realized, but it is Si or
This is possible only when Ge is used, and it is not possible to achieve a sufficiently low resistance by using a GaAs substrate as in conventional devices, and it is used as a wiring body for supplying the ground potential. I can't hope for that.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing the basic structure of the present invention, FIG. 2 is a connection diagram showing a NOR circuit, FIG. 3 is a schematic diagram showing the structure of a NOR circuit according to the present invention, and FIG. 4 is a conventional NOR circuit. 1 is a schematic diagram showing the structure of a circuit, in which 1 is a Si substrate, 1'is a GaAs substrate, 2 is a GaAs layer, 3 and 4 are ohmic electrodes, 5 is a source, 6 is a drain, and 7 is a gate electrode. , 8 is a wiring body, and 9 is an insulating film.

Claims (1)

(57) [Claims] 1. An active element is formed on a GaAs layer of low impurity concentration epitaxially grown on a low-resistance Si or Ge single crystal substrate, and the electrode of the active element to which a specific voltage is supplied is
A semiconductor device, characterized in that it is connected to the low-resistance Si or Ge single crystal substrate by a conductor provided through the GaAs layer.