JPH01135225A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To generate only the set number of smooth pulses by sending a carry signal at a period in accordance with the data read from a memory and preventing the carry signal by the generation of a counting-up signal. CONSTITUTION:The number of pulses to occur during one period is set to a down-counter 2 with a PLOADH signal and a PLOADL signal from a microprocessor. Next, by a sequencer 6, the data to give an corresponding optimum output pulse period are read from a memory 5 with the set value of a counter 2 as an address, set to an FF 7, a pulse prohibiting circuit 10 gives an ADDER-CLOCK to an FF9 by the completion of the setting and full adders 8 are operated. The FF9 latches the output of the full adders 8, every time the most significant bit is changed, the carry signal is generated and the number of the pulses of a signal F is counted by the counter 2. When a counting-up signal CU is generated, the circuit 10 prohibits the passage of a CLOCK signal, the carry signal does not occur and the generation of the serial pulse signals is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a pulse generation circuit that outputs a serial pulse signal having a predetermined number of pulses.

[Prior Art] In a conventional pulse generation circuit, the number of pulses to be output in one cycle is set by a microprocessor;
There was one that outputs a serial pulse signal at a constant frequency.

However, in this pulse generating circuit, since the frequency of the output pulse signal is constant, the output signal becomes a burst-like pulse signal as shown in FIG.

For this reason, if the receiving side of the output pulse is, for example, a pulse motor drive circuit, a problem arises in that the pulse motor does not rotate smoothly.

As a pulse generation circuit that solves these problems, the patent application No. 11 of Japanese Patent Application No. 168099/1983 filed by the present applicant
There was something written in Book II.

This pulse generation circuit reads data that provides an optimal output pulse period from the memory according to the number of pulses generated in one period, and converts this data into [)OA (Digital
[)ifferentialAdder> circuit to generate a smooth pulse signal using the carry signal of the DDA circuit.

[Problems to be Solved by the Invention] However, this pulse generation circuit is configured to generate serial pulses at the timing when the microprocessor sets the number of output pulses for one cycle. Therefore, if the setting timing is shifted due to microprocessor interrupt processing, etc., as shown in Figure 5, the number of output pulses for the next cycle will be set before the set number of pulses has been output. Sometimes I put it away. To prevent this, the microprocessor software must be designed to minimize variations in setting timing. Therefore, there was a problem in that the burden on the software increased.

The present invention has been made to solve these problems, and aims to realize a pulse generation circuit that can generate a set number of smooth pulses without being affected by timing deviations defined by software. purpose.

Means for Solving Problems] The present invention provides the following features: - The number of pulses generated in one cycle is set, and when a pulse is input, the count changes and the count up signal is output when the count changes. a counter that outputs a value, a memory that stores data that provides an optimal output pulse period corresponding to the set value of the counter, and a memory that, when activated by a trigger signal provided by hardware, enables the memory and causes the output of the counter to a starting means for reading out data giving an optimum output pulse period from the memory using a set value as an address signal, and generating a latch signal for latching the read data; A DDA circuit latches the data read out from the DDA circuit and outputs a carry signal at a cycle corresponding to this data, and a DDA circuit that prohibits the passage of the carry signal when the counter generates a count-up signal and outputs a serial pulse signal. This is a pulse generation circuit characterized by comprising a pulse prohibition circuit that terminates output.

[Example] The present invention will be explained below using the drawings.

FIG. 1 is a block diagram of an embodiment of a pulse generating circuit according to the present invention.

In FIG. 1, 1 is a latch that holds and outputs data on the number of pulses generated in one cycle. The data held in latch 1 is 16 bit data, and this data is given in a time-division manner via 8-bit data buses DO to D7.

A counter 2, for example, a down counter, is set with the data output from the latch 1, counts down every time a pulse signal is input, and generates a count up signal CU when the count reaches 0. This counter is 1
It is a 4-bit counter, and the set value is provided by a 16-bit data bus IDO-ID15.

3 is a logic circuit, PLOADL.

PLOADH, 5YNC/ASYNC.

A TRRI GER signal is provided.

The PLOADL and PLOADH signals are signals used to time-divisionally latch the lower byte and upper byte of the 16-bit data held in latch 1. These signals are applied to latch 1 via Nant gates 31 and 32, and are also applied to OR gates 33 and 34 and AND gate 3.
It is also given to the down counter 2 via 5 and 36.

The 5YNC/ASYNC signal is a synchronous/asynchronous operation switching signal. This signal is applied to Nant gates 31 and 32, OR gates 33 and 34, and AND gate 37.

Synchronous and asynchronous operations will be discussed later.

The TRRIGER signal is a signal that triggers the setting of the number of output pulses. This signal is applied to AND gate 37.

4 is a mono multivibrator which is operated by the CLOCK signal, is given the output of an AND gate 37, and gives its output to AND gates 35 and 36.

Reference numeral 5 denotes a memory in which, at an address determined by the set value of the down counter 2, data giving an optimal output pulse cycle corresponding to the set value is stored. This memory 5
For example, an external ROM or the like is used.

A sequencer 6 operates at the timing given by the CLOCK signal, and is activated by the TRRIGER signal based on the level of the output signal of the AND gate 36. When the sequencer 6 is activated, the enable signal ROM0E
enables memory 5 by DLATCH, UL
Generates the ATCH signal and the GATE signal. When memory 5 is enabled, address buses RA1-RA
14, a 14-bit address determined by the set value is sent to the memory 5.

Reference numeral 7 is a first 7-lip/70-tube, 8 is a full adder, and 9 is a third 7-lip flop, and these constitute a DDA circuit.

The first 7-lip/70-tub 7 latches and outputs the data read from the memory 5.

The read data is 16-bit data, and the read data is transmitted by an 8-bit data bus RDO-RD7. For this reason, reading and latching must be performed in time division. The time division of reading is performed by a signal transmitted from the sequencer 6 via a 1-bit address bus RAO.

Time division of the latch is performed using DLATCH and tJLATCH.

The full adder 8 receives the output of the first flip-flop 7 and provides the added value to the second flip-flop 9.

The second flip 70 tube 9 contains the added value of the full adder 8 and AD'DERCLOC from the pulse inhibit circuit described later.
K is input. The second 7 lip-flop 9 is connected to the full adder 8 at the timing of ADDER CLOCK.
The added value is latched and this value is fed back to the input section of the full adder 8.

The full adder 8 adds the outputs of the first flip 70-tube 7 and the second 7-lip 70-tube 9, and provides the added value to the second 7-lip 70-tube 9. The second flip-flop 9 generates a carry pulse signal F every time the most significant pit of the latched data changes. Carry signal F is D
This becomes the output of the DA circuit.

The first 7-rip/70-tube 7, the full adder 8, and the second flip/70-tube 9 handle 16-bit data.

Reference numeral 10 designates a pulse inhibition circuit, which passes the carry signal F and outputs it to the outside before the down counter 2 generates the count up C signal, and also provides it to the down counter 2, and when the count up signal is generated, it is inhibited. state, and prohibits the passage of the carry signal F. The carry signal output to the outside becomes the output signal of the pulse generation circuit. Further, when the pulse inhibit circuit 10 is not in the inhibit state, the pulse inhibit circuit 10
Pass the CK signal and give it to the second 7 lip/70 knob 9 as an ADDER CLOCK,
When in the inhibited state, passage of the CLOCK signal is prohibited. .

Reference numeral 11 denotes an error detection circuit, which receives a signal S from an AND gate 35 and a pulse inhibition circuit 10 indicating whether or not the inhibited state is in effect, and based on these signals, outputs an error to the down counter 2 while a serial pulse is being generated. When a new number of output pulses is set, an error signal ERROR is generated. Signal S becomes a handshake signal that informs the microprocessor whether the pulse generation circuit is ready to set the number of output pulses.

Here, the activation means referred to in the claims are the logic circuit 3,
This corresponds to the mono multivibrator 4 and the sequencer 6.

PLOADL, PLOADH, CLOCK, and data bus transmission signals are given from the microprocessor.

Next, the operation of such a circuit will be explained.

FIG. 2 is a time chart of each signal when the 5YNC/ASYNC signal is at low level. In this case, the timing for setting the number of output pulses is given by software executed by the microprocessor. Further, the AND gate 37 is closed and the passage of the TRIGER signal is prohibited.

PLOADH, PLOADL, ULATCH.

The DLATCH signal is read at the timing when it rises from low level to high level, and the DLATCH signal is read from ROM0E.
The signal enables the memory 5 when it goes low.

The number of pulses generated during one cycle is set in the down counter 2 by the PLOADH and PLOADL signals from the microprocessor.

After setting the number of pulses, the sequencer 6 starts operating.
Using the set value of the down counter 2 as an address, data giving an optimal output pulse period corresponding to the set value is read from the memory 5 and set in the first flip-flop 7. When the setting is completed, the pulse inhibition circuit 10
Give DERCLOCK to the second 7 lip/70 knob 9. This causes the full adder 8 to start operating.

The second flip-flop 9 latches the output of the full adder 8, that is, the sum of the first 7-lip/70-tube 7 and the second flip-flop 9 at the ADDERCLOCK period. Every time the most significant bit of the latched output changes, the second flip 70 tube 9 generates a carry signal F (pulse signal). The number of pulses of this carry signal F is counted by a down counter 2.

When the down counter 1 generates the count up signal CU, the pulse inhibit circuit 10 inhibits the passage of the CLOCK signal and does not provide it to the second flip-flop 9. As a result, the second 7-lip flop 9 no longer generates a carry signal, and the generation of the serial pulse signal ends.

When the error detection circuit 11 sets a new number of output pulses in the down counter 2 while a serial pulse is being generated, an error signal ERROR is generated.

Next, a case where the 5YNC/ASYNC signal becomes high level will be explained. The time chart in this case is as shown in FIG.

The difference in operation from when the 5YNC/ASYNC signal is at low level will be explained.

Gate 37 passes the TRIGER signal.

When the TRRIGER signal becomes high level, the sequencer 6 starts operating, and the ROM0E signal and DLATCH-1, U
Set the LATCH signal to low level, read the data that gives the optimum output pulse period from the memory 5, and perform the flip.
Set the flop to 7.

The TRRIGER signal is provided independently of microprocessor operation.

The subsequent operation is the same as when the 5YNC/ASYNC signal becomes low level.

[Effect] According to the present invention, data read from the memory can be set to the DDA circuit only after activation by the TRRIGER signal. can generate all the set number of pulses. This allows a set number of smooth pulses to be output without being affected by timing deviations defined by software.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the pulse generation circuit according to the present invention, FIGS. 2 and 3 are time charts for explaining the operation of the circuit in FIG. 1, and FIGS. 5 is a time chart for explaining the operation of the pulse generation circuit. 2...down counter, 3...logic circuit, 4...
...Mono multivibrator, 5...Memory, 6...
・Sequencer, 7...1st flip ・7O knob, 8
...Adder, 9...Second flip, 70 knobs, 1
0...Pulse prohibition circuit.

Claims (1)

[Scope of Claims] A counter in which the number of pulses generated during one cycle is set, the count changes when the pulse is input, and outputs a count-up signal when the count changes by the set value; and the set value of the counter. When activated by a trigger signal given by hardware, the memory is enabled, and the set value of the counter is used as an address signal to obtain the optimal output pulse period from the memory. a starting means for reading data giving an output pulse period and generating a latch signal for latching the read data; latching the data read from the memory when the latch signal is generated; , a DDA circuit that outputs a carry signal at a period corresponding to the count-up signal, and a pulse prohibition circuit that prohibits passage of the carry signal and terminates output of the serial pulse signal when the counter generates a count-up signal. A pulse generation circuit characterized by: