JPH0113309B2 - - Google Patents
Info
- Publication number
- JPH0113309B2 JPH0113309B2 JP13236482A JP13236482A JPH0113309B2 JP H0113309 B2 JPH0113309 B2 JP H0113309B2 JP 13236482 A JP13236482 A JP 13236482A JP 13236482 A JP13236482 A JP 13236482A JP H0113309 B2 JPH0113309 B2 JP H0113309B2
- Authority
- JP
- Japan
- Prior art keywords
- winding
- voltage
- shielding layer
- capacitor
- electrostatic shielding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004804 winding Methods 0.000 claims description 99
- 238000006243 chemical reaction Methods 0.000 claims description 35
- 239000003990 capacitor Substances 0.000 description 57
- 230000005540 biological transmission Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000000926 separation method Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Description
【発明の詳細な説明】
この発明は直流電力をスイツチングしてトラン
スの1次巻線へ供給し、そのトランスの2次巻線
の出力を整流平滑して直流出力を得るDC−DC変
換回路に関し、特に入出力間を高インピーダンス
で分離し、しかも同相モードスイツチング雑音の
発生が少ない回路に係わる。[Detailed Description of the Invention] This invention relates to a DC-DC conversion circuit that switches DC power and supplies it to the primary winding of a transformer, rectifies and smoothes the output of the secondary winding of the transformer, and obtains a DC output. In particular, it relates to a circuit that separates input and output with high impedance and generates little common-mode switching noise.
<背景>
この種のDC−DC変換回路は例えばデイジタル
加入者線伝送方式における加入者宅内側に設置さ
れるデイジタル回線終端装置の電源として用いら
れる。即ち第1図に示すように、加入者宅内側に
設置されるデイジタル回線終端装置11は一般に
局からの遠方給電によつて動作するように構成さ
れ、デイジタル回線終端装置11に接続された平
衡形ケーブルの加入者線12上にはデイジタル信
号と給電直流電流とが重畳されている。加入者線
12の他端は図に示してないが局内に引込まれ、
局内側のデイジタル回線終端装置に接続される。
加入者線12上のデイジタル信号は装置11との
接続点13、トランス14を介してパルス伝送回
路15に入力される。パルス伝送回路15は等化
増幅回路、パルス送信回路などから構成される。
加入者線12上の給電直流電流は接続点13、電
力分離フイルタ16a,16bを介してDC−DC
変換回路17の1次側18a,18bに入力さ
れ、これら1次側18a,18b間には例えば直
流電圧30Vが印加される。DC−DC変換回路17
ではDC−DC変換を行い、DC−DC変換回路17
の2次側19a,19b間には、例えば直流電圧
5Vを発生する。デイジタル回線終端装置11の
主要部あるいは全体は、DC−DC変換回路17の
2次側19a,19bの出力によつて動作する。
接続点13及びフイルタ16a,16bの接続点
とトランス14との間に挿入された直流阻止コン
デンサ21はトランス14に給電直流電流を流さ
ないために設けている。電力分離フイルタ16
a,16bは、直流低インピーダンス、交流高イ
ンピーダンスとなるように例えばコイルで構成さ
れている。これは、DC−DC変換回路17の1次
側18a,18b間の交流インピーダンスが低い
ため、デイジタル信号を短絡することを避けるた
めである。<Background> This type of DC-DC conversion circuit is used, for example, as a power source for a digital line termination device installed inside a subscriber's premises in a digital subscriber line transmission system. That is, as shown in FIG. 1, the digital line termination device 11 installed inside the subscriber's premises is generally configured to operate by distant power supply from the station, and the balanced type connected to the digital line termination device 11 is A digital signal and a feeding direct current are superimposed on the subscriber line 12 of the cable. Although the other end of the subscriber line 12 is not shown in the figure, it is led into the office,
Connected to the digital line termination equipment inside the office.
A digital signal on the subscriber line 12 is input to a pulse transmission circuit 15 via a connection point 13 with the device 11 and a transformer 14. The pulse transmission circuit 15 includes an equalization amplifier circuit, a pulse transmission circuit, and the like.
The feed DC current on the subscriber line 12 is DC-DC through the connection point 13 and the power separation filters 16a, 16b.
The voltage is input to the primary sides 18a and 18b of the conversion circuit 17, and a DC voltage of 30 V, for example, is applied between the primary sides 18a and 18b. DC-DC conversion circuit 17
Now perform the DC-DC conversion and create the DC-DC conversion circuit 17.
For example, a DC voltage is applied between the secondary sides 19a and 19b of
Generates 5V. The main part or the whole of the digital line termination device 11 is operated by the outputs of the secondary sides 19a and 19b of the DC-DC conversion circuit 17.
A DC blocking capacitor 21 inserted between the connection point 13 and the connection point between the filters 16a and 16b and the transformer 14 is provided to prevent the supply DC current from flowing through the transformer 14. Power separation filter 16
a and 16b are constructed of, for example, coils so as to provide low impedance for direct current and high impedance for alternating current. This is to avoid short-circuiting the digital signals since the AC impedance between the primary sides 18a and 18b of the DC-DC conversion circuit 17 is low.
さて、以上の構成のデイジタル回線終端装置1
1の電源であるDC−DC変換回路17に、従来構
成のDC−DC変換回路を適用する場合、以下の欠
点が生じる。 Now, the digital line termination device 1 with the above configuration.
When a conventionally configured DC-DC converter circuit is applied to the DC-DC converter circuit 17, which is the power source of No. 1, the following drawbacks occur.
(a) DC−DC変換回路17の1次側と2次側との
間、すなわち1次側18a及び2次側19a
間、あるいは1次側18b及び2次側19b
間、にDC−DC変換回路17のスイツチングに
ともなうスイツチング雑音v1、いわゆる同相モ
ードスイツチング雑音が発生する。この同相モ
ードスイツチング雑音は、加入者線12及びデ
イジタル回線終端装置11などによつて決る不
平衡減衰量に応じて差動モード音に変換され、
トランス14の2次側22a,22b間に廻り
込み、デイジタル信号の符号誤りの原因とな
る。このため同相モードスイツチング雑音の発
生を充分に小さくする必要があるが、従来の
DC−DC変換回路ではこれを満足させることが
できなかつた。(a) Between the primary side and the secondary side of the DC-DC conversion circuit 17, that is, the primary side 18a and the secondary side 19a
between the primary side 18b and the secondary side 19b
During this period, switching noise v1 , so-called common mode switching noise, occurs due to switching of the DC-DC conversion circuit 17. This common mode switching noise is converted into differential mode sound according to the amount of unbalanced attenuation determined by the subscriber line 12, digital line termination device 11, etc.
It goes around between the secondary sides 22a and 22b of the transformer 14, causing a code error in the digital signal. For this reason, it is necessary to sufficiently reduce the generation of common-mode switching noise, but conventional
A DC-DC conversion circuit could not satisfy this requirement.
(b) 加入者線12上には、アナログ電話回線から
のインパルス性雑音等の各種縦雑音が誘導さ
れ、デイジタル信号の符号誤りの原因となるた
め、デイジタル回線終端装置11の不平衡減衰
量は充分に高くする必要がある。前記(a)項に記
載した欠点を除去するため、第2図に示すよう
にDC−DC変換回路17のスイツチング周波数
で充分に低インピーダンスの外付コンデンサ2
3を、1次側18a及び2次側19a間(ある
いは1次側18b及び2次側19b間)に接続
することにより前記同相モードスイツチング雑
音を抑圧しているものがある。しかし、このよ
うな構成とし、かつDC−DC変換回路17の2
次側19aあるいは19bを低インピーダンス
でアースに接続する場合、電力分離フイルタ1
6a(あるいは16b)用のコイルと外付コン
デンサ23とから縦回路に共振点を形成し、こ
の共振点においてデイジタル回線終端装置11
の不平衡減衰量が極度に劣化し符号誤りを生じ
る。このため、前記共振点をパルス伝送帯帯域
より充分に高い周波数とする必要があり、これ
には外付コンデンサ23を除去し、DC−DC変
換回路17の1次側18a,18bと2次側1
9a,19bとをトランス14のストレー容量
程度の高インピーダンスで分離することが必要
である。しかし、このようにすると従来の回路
構成では前記(a)項に記載した欠点が生じる。(b) Various types of vertical noise such as impulsive noise from the analog telephone line are induced on the subscriber line 12 and cause code errors in the digital signal, so the unbalanced attenuation of the digital line termination device 11 is It needs to be high enough. In order to eliminate the drawback described in the above item (a), as shown in FIG.
Some devices suppress the common-mode switching noise by connecting 3 between the primary side 18a and the secondary side 19a (or between the primary side 18b and the secondary side 19b). However, with such a configuration and the second part of the DC-DC conversion circuit 17.
When connecting the next side 19a or 19b to earth with low impedance, power isolation filter 1
A resonance point is formed in the vertical circuit from the coil for 6a (or 16b) and the external capacitor 23, and at this resonance point, the digital line termination device 11
The unbalanced attenuation of the signal is extremely degraded, resulting in code errors. For this reason, it is necessary to set the resonance point to a frequency sufficiently higher than the pulse transmission band, and for this purpose, the external capacitor 23 is removed and the primary side 18a, 18b and secondary side of the DC-DC conversion circuit 17 are 1
9a and 19b must be separated by a high impedance comparable to the stray capacitance of the transformer 14. However, in this case, the conventional circuit configuration suffers from the drawbacks described in item (a) above.
以下これらの点について更に詳細に説明する。 These points will be explained in more detail below.
第3図に従来のDC−DC変換回路の基本構成を
示す。直流電源24から1次側18a,18bを
通じて入力された直流入力電圧E1はスイツチ素
子25のオン/オフの繰返し動作(以下スイツチ
ングと呼ぶ)により交番電圧(以下スイツチング
電圧と呼ぶ)に変換され、トランス26の1次巻
線27の両端29,31間にはスイツチング電圧
e1が生じる。このためトランス26の2次巻線2
8の両端32,33間にはスイツチング電圧e2が
誘起される。このスイツチング電圧e2はダイオー
ド34で半波整流され、出力コンデンサ35で平
滑され、直流出力電圧E2が得られ、この直流出
力は2次側19a,19bを通じて負荷36へ供
給される。なお1次巻線27の両端29,31間
に誘起されるスイツチング電圧e1と2次巻線28
の両端32,33間に誘起されるスイツチング電
圧e2との比は1次巻線27と2次巻線28との巻
線比により定まる。直流電源24の両端間に入力
コンデンサ37が接続され、またスイツチ素子2
5は例えばトランジスタであつて、このトランジ
スタ25は1次巻線27と直列に挿入され、トラ
ンジスタ25のベース・エミツタ間に駆動回路3
8が接続されている。 FIG. 3 shows the basic configuration of a conventional DC-DC conversion circuit. The DC input voltage E1 input from the DC power supply 24 through the primary sides 18a and 18b is converted into an alternating voltage (hereinafter referred to as switching voltage) by the repeated on/off operation (hereinafter referred to as switching) of the switch element 25, A switching voltage is applied between both ends 29 and 31 of the primary winding 27 of the transformer 26.
e 1 occurs. Therefore, the secondary winding 2 of the transformer 26
A switching voltage e 2 is induced between both ends 32 and 33 of 8. This switching voltage e2 is half-wave rectified by a diode 34 and smoothed by an output capacitor 35 to obtain a DC output voltage E2 , which is supplied to a load 36 through the secondary sides 19a and 19b. Note that the switching voltage e 1 induced between both ends 29 and 31 of the primary winding 27 and the secondary winding 28
The ratio to the switching voltage e 2 induced between both ends 32 and 33 of is determined by the winding ratio between the primary winding 27 and the secondary winding 28. An input capacitor 37 is connected between both ends of the DC power supply 24, and a switch element 2
5 is a transistor, for example, and this transistor 25 is inserted in series with the primary winding 27, and the drive circuit 3 is connected between the base and emitter of the transistor 25.
8 are connected.
この第3図に示した従来のDC−DC変換回路で
は1次側−2次側間、すなわち1次側18a、2
次側19a間に大きなスイツチング電圧が発生す
る欠点であつた。これを同相モードスイツチング
雑音と呼び、以下第4図を用いて説明する。第4
図は第3図に示したDC−DC変換回路において、
同相モードスイツチング雑音の発生機構を交流成
分に着目して示したものである。第4図中の記号
は第3図に順じ、e1、e2、v1及びv2は任意の時点
での各端子間のスイツチング電圧を、また矢印は
各電圧極性の相互関係を示す。スイツチ素子25
と電源24との接続点を1次側18b、ダイオー
ド34と出力コンデンサ35との接続点を2次側
19bとしている。巻線端29,32間のコンデ
ンサ42、巻線端31,33間のコンデンサ43
はそれぞれ1次巻線27と2次巻線28との間に
分布するストレー容量を集中定数回路で表わした
ものである。スイツチ素子25、1次巻線27、
入力コンデンサ37よりなる閉回路を閉路と名
付け、1次巻線27、2次巻線28、コンデンサ
42,43よりなる閉回路を閉路と、2次巻線
28、ダイオード34、出力コンデンサ35より
なる閉回路を閉路とそれぞれ呼ぶ。 In the conventional DC-DC conversion circuit shown in FIG. 3, between the primary side and the secondary side, that is, the primary side 18a,
The disadvantage was that a large switching voltage was generated between the next side 19a. This is called common mode switching noise, and will be explained below using FIG. 4. Fourth
The figure shows the DC-DC conversion circuit shown in Figure 3.
This figure shows the generation mechanism of common-mode switching noise, focusing on the AC component. The symbols in Fig. 4 are the same as in Fig. 3, e 1 , e 2 , v 1 and v 2 indicate the switching voltage between each terminal at any given time, and the arrows indicate the mutual relationship of each voltage polarity. . Switch element 25
The connection point between the diode 34 and the power supply 24 is the primary side 18b, and the connection point between the diode 34 and the output capacitor 35 is the secondary side 19b. Capacitor 42 between winding ends 29 and 32, capacitor 43 between winding ends 31 and 33
are the stray capacitances distributed between the primary winding 27 and the secondary winding 28, respectively, expressed by lumped constant circuits. switch element 25, primary winding 27,
The closed circuit consisting of the input capacitor 37 is called a closed circuit, the closed circuit consisting of the primary winding 27, the secondary winding 28, and the capacitors 42 and 43 is called a closed circuit, and the closed circuit consisting of the secondary winding 28, the diode 34, and the output capacitor 35 is called a closed circuit. Each closed circuit is called a closed circuit.
第4図において、まず閉路に着目する。入力
コンデンサ37はスイツチング周波数成分に対し
ては短絡(充分に低インピーダンス)であるから
その両端にはスイツチング電圧は発生しない。従
つてキルヒホツフの電圧側からスイツチ素子25
の両端には1次巻線27の両端29,31間に誘
起されるスイツチング電圧e1に等しい振幅のスイ
ツチング電圧が逆位相で発生する。次に閉路に
着目する。出力コンデンサ35はスイツチング周
波数成分に対しては短絡であるから、その両端に
はスイツチング電圧は発生しない。したがつてキ
ルヒホツフの電圧側からダイオード34の両端に
は2次巻線28の両端32,33間に誘起される
スイツチング電圧e2に等しい振幅のスイツチング
電圧が逆位相で発生する。 In FIG. 4, first focus on the closed circuit. Since the input capacitor 37 is short-circuited (sufficiently low impedance) for the switching frequency component, no switching voltage is generated across it. Therefore, from the Kirchoff voltage side, the switch element 25
A switching voltage with an amplitude equal to the switching voltage e 1 induced between both ends 29 and 31 of the primary winding 27 is generated at both ends of the primary winding 27 in opposite phases. Next, we will focus on closed circuits. Since the output capacitor 35 is short-circuited for the switching frequency component, no switching voltage is generated across it. Therefore, a switching voltage with an amplitude equal to the switching voltage e 2 induced between the ends 32 and 33 of the secondary winding 28 is generated in opposite phase across the diode 34 from the Kirchhoff voltage side.
次に閉路に着目する。通常コンデンサ42,
43の容量値はともに小さく、スイツチング周波
数を含む高周波域に亘り充分に高いインピーダン
スとなる。さて閉路において、コンデンサ4
2,43の両端に発生するスイツチング電圧を
各々v1、v2とすると、キルヒホツフの電圧側から
v1+v2=e1−e2となる関係を満たす。また電圧v1
とv2の比は各々のコンデンサ42,43の容量値
に反比例する。コンデンサ42の両端に発生する
スイツチング電圧v1は同相モードスイツチング雑
音である。以下閉路部分の拡大図である第5図
を用いて説明する。第5図中の記号は第4図に順
ずる。各々コンデンサ42,43の容量値をC1、
C2とする。第5図から同相モードスイツチング
雑音の振幅値v1は
v1=C2/C1+C2(e2−e1) (1)
となり、1次巻線27の両端に生じるスイツチン
グ電圧e1と、2次巻線28の両端に誘起されるス
イツチング電圧e2との双方の影響から発生する。
通常のDC−DC変換回路においてはe1≠e2であ
る。このため1次側18a,18b、2次側19
a,19b間を高インピーダンスで分離し、かつ
同相モードスイツチング雑音の発生を少なくする
ためにはコンデンサ43の容量値C2をコンデン
サ42の容量値C1に対して充分に小さくする必
要がある。しかし、コンデンサ43の容量値C2
はトランスの1次巻線27、2次巻線28及びコ
アの形状によつて定まり、容量値C2はあまり小
さくできない。一方コンデンサ42の容量値C1
を大きくすると(例えばコンデンサ外付により)、
同相モードスイツチング雑音は小さくなるが、分
離フイルタと共振点を形成し、1次側18a,1
8b−2次側19a,19b間が低インピーダン
スとなつて不平衡減衰量が異なる。以上から1次
側18a,18b−2次側19a,19b間を高
インピーダンスで分離し、かつ同相モードスイツ
チング雑音を低減化させることは従来技術は困難
であつた。一例として第3図に示した構成で直流
入力電圧E1=30V、直流出力電圧E2=5V、出力
電力1W程度のDC−DC変換回路においては、同
相モードスイツチング雑音はリツプル成分で約
10Vpp程度生じる。但し、1次、2次巻線の構成
によりこの雑音値は微妙に異なつてくる。 Next, we will focus on closed circuits. Normal capacitor 42,
The capacitance values of 43 are both small, and the impedance is sufficiently high over a high frequency range including the switching frequency. Now, in a closed circuit, capacitor 4
If the switching voltages generated at both ends of 2 and 43 are v 1 and v 2 , respectively, then from the Kirchhoff voltage side
It satisfies the relationship v 1 + v 2 = e 1 − e 2 . Also the voltage v 1
and v 2 is inversely proportional to the capacitance value of each capacitor 42, 43. The switching voltage v 1 generated across capacitor 42 is common mode switching noise. The following description will be made with reference to FIG. 5, which is an enlarged view of the closed circuit portion. The symbols in FIG. 5 correspond to those in FIG. 4. The capacitance values of capacitors 42 and 43 are C 1 ,
Let it be C 2 . From FIG. 5, the amplitude value v 1 of the common mode switching noise is v 1 = C 2 /C 1 +C 2 (e 2 - e 1 ) (1), and the switching voltage e 1 generated across the primary winding 27 is and the switching voltage e 2 induced across the secondary winding 28.
In a normal DC-DC conversion circuit, e 1 ≠ e 2 . Therefore, the primary side 18a, 18b, the secondary side 19
In order to isolate between a and 19b with high impedance and to reduce the occurrence of common mode switching noise, it is necessary to make the capacitance value C2 of the capacitor 43 sufficiently smaller than the capacitance value C1 of the capacitor 42. . However, the capacitance value C 2 of the capacitor 43
is determined by the shapes of the primary winding 27, secondary winding 28, and core of the transformer, and the capacitance value C2 cannot be made very small. On the other hand, the capacitance value C 1 of the capacitor 42
If you increase (for example, by adding an external capacitor),
Although the common mode switching noise becomes small, it forms a resonance point with the separation filter, and the primary side 18a, 1
8b and the secondary sides 19a and 19b have low impedance and have different unbalanced attenuation amounts. From the above, it has been difficult with the prior art to isolate the primary sides 18a, 18b and the secondary sides 19a, 19b with high impedance and reduce common mode switching noise. As an example, in a DC-DC converter circuit with the configuration shown in Figure 3, with a DC input voltage E 1 = 30V, a DC output voltage E 2 = 5V, and an output power of about 1W, the common-mode switching noise is a ripple component and is approximately
Approximately 10Vpp is generated. However, this noise value differs slightly depending on the configuration of the primary and secondary windings.
<発明の概要>
この発明の目的は直流及びスイツチング周波数
を含む高周波域に亘り1次側−2次側間を高イン
ピーダンスで分離し、しかも同相モードスイツチ
ング雑音の発生が少ないDC−DC変換回路を提供
することにある。<Summary of the Invention> The purpose of the present invention is to provide a DC-DC conversion circuit that isolates the primary side and the secondary side with high impedance over a high frequency range including DC and switching frequencies, and that generates little common mode switching noise. Our goal is to provide the following.
この発明によれば1次巻線と2次巻線との間に
静電遮へい層が配され、この静電遮へい層は1次
巻線の静止端に接続され、かつ2次巻線の中点か
らみて、2次巻線の一方の側に静電遮へい層に対
して誘起される電圧と、1次巻線の他方の側に静
電遮へい層に対して誘起される電圧が互いに逆極
性となる打消手段が設けられる。 According to this invention, an electrostatic shielding layer is arranged between the primary winding and the secondary winding, and this electrostatic shielding layer is connected to the stationary end of the primary winding and inside the secondary winding. From the point of view, the voltage induced against the electrostatic shielding layer on one side of the secondary winding and the voltage induced against the electrostatic shielding layer on the other side of the primary winding have opposite polarity. A canceling means is provided.
<第1実施例>
第6図はこの発明の第1実施例を示す。この実
施例では2次巻線28はその中点が開放されて2
次巻線28a,28bとされ、その開放端44,
45間に半波整流用のダイオード34が接続され
て打消手段が構成される。また1次巻線27と2
次巻線28a,28bとの間に静電遮へい層46
が介在され、この静電遮へい層46は1次巻線2
7の交流的な零電位点(以下静止端と呼ぶ)であ
る1次側18aに接続している。1次側18bも
静止端であり、静電遮へい層46を1次側18b
に接続しても効果は同一である。その他の記号は
第3図に順ずる。このような構成をしているから
以下に説明するように1次側18a−2次側19
a間に発生するスイツチング電圧、すなわち同相
モードスイツチング雑音を低減化する作用があ
る。<First Embodiment> FIG. 6 shows a first embodiment of the present invention. In this embodiment, the secondary winding 28 is open at its midpoint and 2
The next windings 28a, 28b are the open ends 44,
A diode 34 for half-wave rectification is connected between 45 and 45 to constitute canceling means. Also, the primary windings 27 and 2
Electrostatic shielding layer 46 between the next windings 28a and 28b
is interposed, and this electrostatic shielding layer 46 is connected to the primary winding 2.
It is connected to the primary side 18a which is the AC zero potential point (hereinafter referred to as the stationary end) of No.7. The primary side 18b is also a stationary end, and the electrostatic shielding layer 46 is connected to the primary side 18b.
The effect is the same even if connected to . Other symbols follow Figure 3. Since it has such a configuration, as explained below, the primary side 18a-secondary side 19
This has the effect of reducing the switching voltage generated between terminals a, that is, common mode switching noise.
第3図に示した従来のDC−DC変換回路の場
合、同相モードスイツチング雑音は、式(1)から1
次巻線27の両端に生じるスイツチング電圧e1と
2次巻線28の両端に誘起されるスイツチング電
圧e2との双方の影響により発生する。しかし、第
6図に示した実施例では(i)1次巻線27−2次巻
線28a,28b間に静電遮へい層46が設けら
れ、かつこれが1次巻線27の静止端である1次
側18aに接続されていることにより、1次巻線
27の両端に生じるスイツチング電圧e1が1次側
18a−2次側19a間の電圧(同相モードスイ
ツチング雑音)として発生しない。(ii)また、半波
整流用ダイオード34が2次巻線28の中点に挿
入接続されていることにより、静電遮へい層46
と2次巻線28aとの間のスイツチング電圧の電
位分布と、静電遮へい層46と2次巻線28bと
の間のスイツチング電圧の電位分布とが逆極性と
なり互いに打ち消し合つて2次巻線28a,28
bの各両端に生じるスイツチング電圧e2/2が1次
側18a−2次側19a間の電圧(同相モードス
イツチング雑音)として発生しない。 In the case of the conventional DC-DC conversion circuit shown in Figure 3, the common mode switching noise is calculated from equation (1) as 1
This occurs due to the effects of both the switching voltage e 1 generated across the secondary winding 27 and the switching voltage e 2 induced across the secondary winding 28 . However, in the embodiment shown in FIG. 6, (i) an electrostatic shielding layer 46 is provided between the primary winding 27 and the secondary windings 28a, 28b, and this is the stationary end of the primary winding 27; By being connected to the primary side 18a, the switching voltage e1 generated across the primary winding 27 does not occur as a voltage between the primary side 18a and the secondary side 19a (common mode switching noise). (ii) Also, by inserting and connecting the half-wave rectifying diode 34 to the middle point of the secondary winding 28, the electrostatic shielding layer 46
The potential distribution of the switching voltage between the electrostatic shielding layer 46 and the secondary winding 28a and the potential distribution of the switching voltage between the electrostatic shielding layer 46 and the secondary winding 28b have opposite polarities, cancel each other out, and the secondary winding 28a, 28
The switching voltage e 2 /2 generated across each end of the signal b does not occur as a voltage (common mode switching noise) between the primary side 18a and the secondary side 19a.
これらの点につき第7図を用いて更に詳細に説
明する。第7図は第6図に示したDC−DC変換回
路において同相モードスイツチング雑音の低減化
作用を交流成分に着目して示したものである。第
7図中の記号は第5図に順じ、e1、e2及びv1は任
意の時点での各端子間のスイツチング電圧をまた
矢印は各電圧極性の相互関係を示す。コンデンサ
47,48は2次巻線28aと静電遮へい層46
との間に分布するストレー容量を集中定数回路で
表わし、コンデンサ47,48はそれぞれ2次巻
線28aの両端32,44と静電遮へい層46と
の間に接続してある。コンデンサ49,51は2
次巻線28bと静電遮へい層46との間に分布す
るストレー容量を集中定数回路で表わし、コンデ
ンサ49,51はそれぞれ2次巻線28bの両端
45,33と静電遮へい層46との間に接続され
る。コンデンサ52,53は1次巻線27と静電
遮へい層46との間に分布するストレー容量を集
中定数回路で表わし、コンデンサ52,53は1
次巻線27の両端29,31と静電遮へい層46
との間に接続される。コンデンサ37、1次巻線
27、スイツチ素子25の閉回路を閉路とし、
1次巻線27、コンデンサ52,53、静電遮へ
い層46の閉回路を閉路とし、2次巻線28
a、コンデンサ47,48、静電遮へい層46の
閉回路を閉路とし、ダイオード34、コンデン
サ48,49、静電遮へい層46の閉回路を閉路
とし、2次巻線28b、コンデンサ49,5
1、静電遮へい層46の閉回路を閉路とし、2
次巻線28a,28b、ダイオード34、コンデ
ンサ47,51、静電遮へい層46の閉回路を閉
路とし、2次巻線28a,28b、ダイオード
34、出力コンデンサ35の閉回路を閉路とす
る。 These points will be explained in more detail using FIG. 7. FIG. 7 shows the effect of reducing the common mode switching noise in the DC-DC conversion circuit shown in FIG. 6, focusing on the alternating current component. The symbols in FIG. 7 are the same as in FIG. 5, and e 1 , e 2 and v 1 represent the switching voltages between the respective terminals at any given time, and the arrows represent the mutual relationship between the voltage polarities. The capacitors 47 and 48 are connected to the secondary winding 28a and the electrostatic shielding layer 46.
The stray capacitance distributed between is represented by a lumped constant circuit, and capacitors 47 and 48 are connected between both ends 32 and 44 of the secondary winding 28a and the electrostatic shielding layer 46, respectively. Capacitors 49 and 51 are 2
Stray capacitance distributed between the secondary winding 28b and the electrostatic shielding layer 46 is represented by a lumped constant circuit, and capacitors 49 and 51 are connected between both ends 45 and 33 of the secondary winding 28b and the electrostatic shielding layer 46, respectively. connected to. The capacitors 52 and 53 represent the stray capacitance distributed between the primary winding 27 and the electrostatic shielding layer 46 using lumped constant circuits.
Both ends 29 and 31 of the next winding 27 and the electrostatic shielding layer 46
connected between. The closed circuit of the capacitor 37, the primary winding 27, and the switch element 25 is a closed circuit,
The closed circuit of the primary winding 27, the capacitors 52 and 53, and the electrostatic shielding layer 46 is a closed circuit, and the secondary winding 28
a, the closed circuit of the capacitors 47, 48 and the electrostatic shielding layer 46 is a closed circuit, the closed circuit of the diode 34, the capacitors 48, 49, and the electrostatic shielding layer 46 is a closed circuit, the secondary winding 28b, the capacitors 49, 5
1. The closed circuit of the electrostatic shielding layer 46 is a closed circuit, and 2.
A closed circuit of the secondary windings 28a, 28b, the diode 34, the capacitors 47, 51, and the electrostatic shielding layer 46 is a closed circuit, and a closed circuit of the secondary windings 28a, 28b, the diode 34, and the output capacitor 35 is a closed circuit.
最初に上記(i)項を説明する。第7図において、
まず閉路に着目する。入力コンデンサ37はス
イツチング周波数成分に対しては短絡(充分に低
インピーダンス)であるから、その両端にはスイ
ツチング電圧は発生しない。従つてキルヒホツフ
の電圧則からスイツチ素子25の両端には1次巻
線27の両端29,31間に誘起されるスイツチ
ング電圧e1に等しい振幅のスイツチング電圧が逆
位相で発生する。次に閉路に着目する。コンデ
ンサ52の両端は静電遮へい層46により短絡さ
れているからスイツチング電圧は発生しない。し
たがつて、閉路におけるキルヒホツフの電圧則
からコンデンサ53の両端には1次巻線27の両
端29,31間に生じるスイツチング電圧e1に等
しい振幅のスイツチング電圧が逆位相で発生す
る。以上から1次側に発生するスイツチング電圧
e1は静電遮へい層46により1次側のみに閉じ1
次側18a−2次側19a間の電圧には影響を及
ぼさないことが説明された。 First, the above item (i) will be explained. In Figure 7,
First, let's focus on closed circuits. Since the input capacitor 37 is short-circuited (sufficiently low impedance) to the switching frequency component, no switching voltage is generated across it. Therefore, according to Kirchhoff's voltage law, a switching voltage with an amplitude equal to the switching voltage e 1 induced between the ends 29 and 31 of the primary winding 27 is generated at both ends of the switch element 25 in opposite phases. Next, we will focus on closed circuits. Since both ends of the capacitor 52 are short-circuited by the electrostatic shielding layer 46, no switching voltage is generated. Therefore, according to Kirchhoff's voltage law in a closed circuit, a switching voltage with an amplitude equal to the switching voltage e 1 generated between both ends 29 and 31 of the primary winding 27 is generated at both ends of the capacitor 53 in opposite phases. Switching voltage generated on the primary side from the above
e 1 is closed only on the primary side by the electrostatic shielding layer 46 1
It was explained that the voltage between the secondary side 18a and the secondary side 19a is not affected.
次に前記(ii)項について説明する。第7図におい
て閉路に着目する。出力コンデンサ35はスイ
ツチング周波数成分に対しては短絡であるから、
その両端にはスイツチング電圧は発生しない。2
次巻線28は中点44,45にて2分割されてい
るから、2次巻線28aの両端32,44間と2
次巻線28bの両端33,45間とには、等しい
振幅のスイツチング電圧e2/2が同位相で誘起され
る。ここで閉路におけるキルヒホツフの電圧側
からダイオード34の両端には2次巻線28aの
両端32,44間、2次巻線28bの両端45,
33間にそれぞれ誘起されるスイツチング電圧の
和e2に等しい振幅のスイツチング電圧が逆位相で
発生する。 Next, the above item (ii) will be explained. In FIG. 7, attention is paid to the closed circuit. Since the output capacitor 35 is short-circuited for the switching frequency component,
No switching voltage is generated across it. 2
Since the secondary winding 28 is divided into two parts at the midpoints 44 and 45, between both ends 32 and 44 of the secondary winding 28a,
Switching voltages e 2 /2 of equal amplitude and in phase are induced between both ends 33 and 45 of the next winding 28b. Here, from the Kirchhoff voltage side in the closed circuit, between both ends 32 and 44 of the secondary winding 28a, between both ends 45 of the secondary winding 28b,
A switching voltage with an amplitude equal to the sum e 2 of the switching voltages induced between 33 and 33 is generated in opposite phase.
次に閉路、及びに着目する。通常コンデ
ンサ47,48,49及び51の容量値はともに
小さく、スイツチング周波数を含む高周波域に亘
り充分に高インピーダンスとなる。また、通常2
次巻線28a,28bとその一端32,45を同
一側としてバイフアイラ巻きにすることにより、
静電遮へい層46−巻線端32間と、静電遮へい
層46−巻線端45間との物理的な位置関係は等
しくなる。このため、コンデンサ47とコンデン
サ49の容量値は概ね等しく、これをC3とする。
同様に静電遮へい層46−巻線端44間と静電遮
へい層46−巻線点33間との物理的な位置関係
は等しい。このためコンデンサ48とコンデンサ
51の容量値は概ね等しく、これをC4とする。 Next, we will focus on cycles and. Normally, the capacitance values of capacitors 47, 48, 49, and 51 are all small, and the impedance is sufficiently high over a high frequency range including the switching frequency. Also, usually 2
By bifilar winding with the next windings 28a, 28b and their one ends 32, 45 on the same side,
The physical positional relationship between the electrostatic shielding layer 46 and the winding end 32 is equal to that between the electrostatic shielding layer 46 and the winding end 45. Therefore, the capacitance values of capacitor 47 and capacitor 49 are approximately equal, and this is designated as C3 .
Similarly, the physical positional relationship between the electrostatic shielding layer 46 and the winding end 44 and between the electrostatic shielding layer 46 and the winding point 33 are the same. Therefore, the capacitance values of capacitor 48 and capacitor 51 are approximately equal, and this is designated as C4 .
ここで閉路に着目する。コンデンサ47の両
端にスイツチング電圧v1が発生したとする。先に
述べた2次巻線28a,28bの電圧とダイオー
ド34の電圧とは等しく逆位相であるから、キル
ヒホツフの電圧則から、コンデンサ51の両端に
はコンデンサ47の両端に発生するスイツチング
電圧v1に等しい振幅のスイツチング電圧が逆位相
で発生する。このスイツチング電圧v1は同層モー
ドスイツチング電圧である。次に第8図を用いて
説明する。第8図は第7図中の閉路、及び
部分を抽象したものであり、記号は第7図に順ず
る。コンデンサ47,49の容量値をC3、コン
デンサ47,51の容量値をC4とする。第8図
の閉路、及びについてそれぞれ閉路方程式
を解くと、
v1=C4−C3/C3+C4 e2/4 (2)
v2=3C3+C4/C3+C4 e2/4 (3)
v3=C3+3C4/C3+C4 e2/4 (4)
となる。式(2)から同相モードスイツチング雑音は
コンデンサ47,49の容量値C3とコンデンサ
48,51の容量値C4との差が小さい程、低減
化される。さて、第6図において、静電遮へい層
46−巻線端32(あるいは45)間のストレー
容量と静電遮へい層46−巻線端44(あるいは
33)間のストレー容量を等しくする技術は比較
的容易であり、静電遮へい層46に対する巻線端
32(あるいは45)の物理的位置と、静電遮へ
い層46−巻線端44(あるいは33)との物理
的位置を対称とすればよい。例えば2次巻線28
a,28bを静電遮へい層46に対して1層巻き
となるよう構成すればよい。すなわち、第8図に
おいてコンデンサ47(あるいはコンデンサ4
9)の容量値C3と、コンデンサ48(あるいは
コンデンサ51)の容量値C4とを概ね等しくす
る技術は既知である。以上から半波整流用のダイ
オード34を2次巻線28の中点に挿入接続する
ことにより、2次巻線28a,28bの両端に誘
起されるスイツチング電圧e2/2が1次側18a−
2次側19a間の電圧に及ぼす影響を低減化させ
得ることを説明できた。 Here, we will focus on closed circuits. Assume that a switching voltage v 1 is generated across the capacitor 47. Since the voltages of the secondary windings 28a and 28b mentioned above and the voltage of the diode 34 are equal and in opposite phases, from Kirchhoff's voltage law, the switching voltage v 1 generated at both ends of the capacitor 47 is applied to both ends of the capacitor 51. Switching voltages of amplitude equal to are generated in opposite phases. This switching voltage v 1 is the same layer mode switching voltage. Next, it will be explained using FIG. FIG. 8 is an abstraction of the circuit and parts in FIG. 7, and the symbols are the same as in FIG. 7. It is assumed that the capacitance values of the capacitors 47 and 49 are C 3 and the capacitance values of the capacitors 47 and 51 are C 4 . Solving the cycle equations for the cycles and in Figure 8, v 1 = C 4 − C 3 /C 3 +C 4 e 2 /4 (2) v 2 =3C 3 +C 4 /C 3 +C 4 e 2 / 4 (3) v 3 =C 3 +3C 4 /C 3 +C 4 e 2 /4 (4). From equation (2), the common mode switching noise is reduced as the difference between the capacitance value C 3 of the capacitors 47 and 49 and the capacitance value C 4 of the capacitors 48 and 51 is smaller. Now, in FIG. 6, the techniques for equalizing the stray capacitance between the electrostatic shielding layer 46 and the winding end 32 (or 45) and the stray capacitance between the electrostatic shielding layer 46 and the winding end 44 (or 33) are compared. The physical position of the winding end 32 (or 45) with respect to the electrostatic shielding layer 46 and the physical position of the electrostatic shielding layer 46 - the winding end 44 (or 33) may be made symmetrical. . For example, the secondary winding 28
a, 28b may be configured to be wound in one layer around the electrostatic shielding layer 46. That is, in FIG. 8, capacitor 47 (or capacitor 4
9) and the capacitance value C 4 of the capacitor 48 (or capacitor 51) are known. From the above, by inserting and connecting the diode 34 for half-wave rectification to the middle point of the secondary winding 28, the switching voltage e 2 /2 induced across the secondary windings 28a and 28b is changed to the primary side 18a- It has been explained that the influence on the voltage between the secondary side 19a can be reduced.
以上、第6図に示した構成により直流及びスイ
ツチング周波数を含む高周波数に亘り1次側18
a,18b−2次側19a,19b間を高インピ
ーダンスで分離し、かつ同相モードスイツチング
雑音の発生が少ないDC−DC変換回路を提供し得
る。 As described above, with the configuration shown in FIG. 6, the primary side 18
A, 18b and the secondary sides 19a, 19b are separated by high impedance, and a DC-DC conversion circuit that generates less common mode switching noise can be provided.
第6図において2次側が多出力で2次巻線を複
数個有するDC−DC変換回路とする場合には1次
巻線、複数の2次巻線を順次同軸心上に形成し、
2次巻線相互間にも静電遮へい層を設け、かつこ
の静電遮へい層を、1次巻線−2次巻線間の静電
遮へい層46に接続した構成とすることが、同相
モードスイツチング雑音の発生を少なくする上で
有利である。 In FIG. 6, when the secondary side is a DC-DC converter circuit with multiple outputs and multiple secondary windings, the primary winding and multiple secondary windings are sequentially formed on the same axis,
By providing an electrostatic shielding layer between the secondary windings and connecting this electrostatic shielding layer to the electrostatic shielding layer 46 between the primary winding and the secondary winding, common mode This is advantageous in reducing the occurrence of switching noise.
<第2実施例>
以上はいわゆる電流伝送形、つまり第6図にお
いて、1次側のスイツチ素子25がオフの時に、
2次側の半波整流用のダイオード34が導通する
形式のDC−DC変換回路にこの発明を適用した
が、いわゆる電圧伝送形、つまり1次側のスイツ
チ素子がオンの時に2次側の半波整流用のダイオ
ードが導通する形式のDC−DC変換回路にも、こ
の発明を適用できる。第6図を対応するこの発明
の電圧伝送形のDC−DC変換回路を第9図に示
す。これらの場合において整流用ダイオード34
が第6図の場合と逆極性とされ、その他は同一構
成である。<Second Embodiment> The above is a so-called current transmission type, that is, in FIG. 6, when the primary side switch element 25 is off,
The present invention was applied to a DC-DC conversion circuit in which the half-wave rectifier diode 34 on the secondary side conducts, but it is a so-called voltage transmission type, that is, when the primary side switch element is on, the The present invention can also be applied to a DC-DC conversion circuit in which a diode for wave rectification is conductive. FIG. 9 shows a voltage transmission type DC-DC conversion circuit of the present invention corresponding to FIG. 6. In these cases, the rectifier diode 34
The polarity is opposite to that in the case of FIG. 6, and the other configurations are the same.
<効果>
以上説明したようにこの発明により、直流及び
スイツチング周波数を含む高周波域に亘り1次側
及び2次側間を高インピーダンスで分離し、かつ
同相モードスイツチング雑音の発生が少ないDC
−DC変換回路が提供できるため、平衡形ケーブ
ルを用いたデイジタル加入者線伝送系において、
局からの遠方給電によつて動作する加入者宅内側
に設置されるデイジタル回線終端装置用の受電用
電源としての適用に利点がある。具体的にはDC
−DC変換回路の発生するスイツチング雑音のパ
ルス伝送系回路への廻り込みが少なく、デイジタ
ル回線終端装置と加入者線との高インピーダンス
分離が可能である。これによる効果はパルス伝送
帯域においてデイジタル回線終端装置の高い不平
衡減衰量が得られ、加入者線上に誘導される大き
な縦雑音に対してデイジタル信号の符号誤りを極
力抑圧し得ることである。<Effects> As explained above, the present invention provides a DC switching system that isolates the primary side and secondary side with high impedance over a high frequency range including DC and switching frequencies, and generates less common mode switching noise.
-Since we can provide DC conversion circuits, we can provide
It has an advantage in application as a power receiving power source for a digital line termination device installed inside a subscriber's premises that operates by supplying power from a remote station. Specifically, DC
- Switching noise generated by the DC conversion circuit is less likely to enter the pulse transmission system circuit, and high impedance separation between the digital line termination device and the subscriber line is possible. The effect of this is that a high unbalanced attenuation of the digital line termination device can be obtained in the pulse transmission band, and code errors in the digital signal can be suppressed as much as possible against large vertical noise induced on the subscriber line.
次に数値例を示す。第6図に示した構成におい
て、入力電圧E1を約26V、入力電流を約24mA、
出力電圧E2を5V±3.5%、出力電力約500mW1次
巻線27の巻線数を80回程度、2次巻線28a,
28bの巻線数を各8回程度の2線巻き(バイフ
アイラ巻き)、静電遮へい層46は銅箔、スイツ
チ素子25はMOS−FET、整流用ダイオード3
4はシヨツトキーバリアダイオード、トランス2
次巻線28a,28bは静電遮へい層46に対し
て1層巻き、スイツチング周波数約70KHzとした
DC−DC変換回路において、同相モードスイツチ
ング雑音はリツプル成分で約0.5Vpp、電力変換
効率は約80%であつた。なお、スイツチ素子の駆
動回路38は他励形あるいは自励形としても、上
記同相モードスイツチング雑音は同一であつた。 A numerical example is shown next. In the configuration shown in Figure 6, the input voltage E1 is approximately 26V, the input current is approximately 24mA,
The output voltage E2 is 5V±3.5%, the output power is about 500mW, the number of turns of the primary winding 27 is about 80, the secondary winding 28a,
The number of turns of the wire 28b is about 8 times each (bifilar winding), the electrostatic shielding layer 46 is copper foil, the switch element 25 is a MOS-FET, and the rectifier diode 3 is used.
4 is a shot key barrier diode, transformer 2
The next windings 28a and 28b are wound in one layer around the electrostatic shielding layer 46, and the switching frequency is approximately 70KHz.
In the DC-DC conversion circuit, the common mode switching noise was approximately 0.5Vpp as a ripple component, and the power conversion efficiency was approximately 80%. Note that the common mode switching noise was the same whether the switch element drive circuit 38 was a separately excited type or a self-excited type.
第1図及び第2図はそれぞれ加入者宅内側に設
置されるデイジタル回線終端装置の構成を示す
図、第3図は従来の電流伝送形DC−DC変換回路
の基本構成を示す接続図、第4図は第3図のDC
−DC変換回路における同相モードスイツチング
雑音発生機構の説明図、第5図は第4図の閉路
部分の拡大図、第6図はこの発明を電流伝送形
DC−DC変換回路に適用した実施例を示す接続
図、第7図は第6図のDC−DC変換回路における
同相モードスイツチング雑音低減化作用の説明
図、第8図は第7図の閉路、、部分の拡大
図、第9図はこの発明を電圧伝送形DC−DC変換
回路に適用した実施例を示す接続図である。
24:直流電源、25:スイツチ素子、26:
トランス、27:1次巻線、28:2次巻線、2
8a,28b:中点で2分割した2次巻線、3
4:半波整流用のダイオード、35:出力コンデ
ンサ、36:負荷、37:入力コンデンサ、3
8:スイツチ素子の駆動回路、46:静電遮へい
層。
Figures 1 and 2 are diagrams showing the configuration of a digital line termination device installed inside a subscriber's premises, respectively. Figure 3 is a connection diagram showing the basic configuration of a conventional current transmission type DC-DC conversion circuit. Figure 4 is the DC of Figure 3.
- An explanatory diagram of the common-mode switching noise generation mechanism in a DC conversion circuit, Figure 5 is an enlarged view of the closed circuit part of Figure 4, and Figure 6 shows the current transmission type of this invention.
A connection diagram showing an example applied to a DC-DC conversion circuit, Fig. 7 is an explanatory diagram of the common mode switching noise reduction effect in the DC-DC conversion circuit of Fig. 6, and Fig. 8 is a closed circuit diagram of Fig. 7. FIG. 9 is a connection diagram showing an embodiment in which the present invention is applied to a voltage transmission type DC-DC conversion circuit. 24: DC power supply, 25: Switch element, 26:
Transformer, 27: Primary winding, 28: Secondary winding, 2
8a, 28b: Secondary winding divided into two at the midpoint, 3
4: Diode for half-wave rectification, 35: Output capacitor, 36: Load, 37: Input capacitor, 3
8: Switch element drive circuit, 46: Electrostatic shielding layer.
Claims (1)
巻線へ供給し、そのトランスの2次巻線の出力を
整流平滑して直流出力を得るDC−DC変換回路に
おいて、前記1次巻線と2次巻線との間に、その
1次巻線の静止端に接続された静電遮へい層を有
し、前記2次巻線がその中点で開放され、その開
放端子間に前記整流のための半波整流用のダイオ
ードが接続されたものであることを特徴とする
DC−DC変換回路。1. In a DC-DC conversion circuit that switches and supplies DC power to the primary winding of a transformer and rectifies and smoothes the output of the secondary winding of the transformer to obtain a DC output, the primary winding and the secondary an electrostatic shielding layer connected to the stationary end of the primary winding between the winding and the secondary winding being open at its midpoint, and having an electrostatic shielding layer between the open terminals for the rectification. It is characterized by a diode connected for half-wave rectification.
DC-DC conversion circuit.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13236482A JPS5925578A (en) | 1982-07-28 | 1982-07-28 | Dc-dc converting circuit |
US06/515,754 US4507721A (en) | 1982-07-28 | 1983-07-21 | DC-DC Converter for remote power feeding |
DE8383107388T DE3374745D1 (en) | 1982-07-28 | 1983-07-27 | Dc-dc converter for remote power feeding |
EP83107388A EP0100098B1 (en) | 1982-07-28 | 1983-07-27 | Dc-dc converter for remote power feeding |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13236482A JPS5925578A (en) | 1982-07-28 | 1982-07-28 | Dc-dc converting circuit |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63262622A Division JPH0295168A (en) | 1988-10-18 | 1988-10-18 | Dc/dc converter circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5925578A JPS5925578A (en) | 1984-02-09 |
JPH0113309B2 true JPH0113309B2 (en) | 1989-03-06 |
Family
ID=15079635
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13236482A Granted JPS5925578A (en) | 1982-07-28 | 1982-07-28 | Dc-dc converting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5925578A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0740786B2 (en) * | 1987-04-22 | 1995-05-01 | 新電元工業株式会社 | Switching power supply |
US8154371B2 (en) * | 2008-11-06 | 2012-04-10 | Power Integrations, Inc. | Method and apparatus for adjusting displacement current in an energy transfer element |
JP5434370B2 (en) * | 2009-08-26 | 2014-03-05 | サンケン電気株式会社 | Resonant switching power supply |
-
1982
- 1982-07-28 JP JP13236482A patent/JPS5925578A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5925578A (en) | 1984-02-09 |
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