JPH01124251A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance electrostatic breakdown strength sufficiently even when a current- limiting resistor connected to an input terminal of a protective element is not contained or when only a resistor with an extremely small value can be connected by a method wherein the current-limiting resistor is used between a first constant-voltage clamping element and a second constant-voltage clamping element. CONSTITUTION:When static electricity is impressed on a terminal 1, an electric current ID at an input node D flows to a grounding terminal 103 mainly through a protective resistor 2, a first constant-voltage clamping element 4 and a parasitic resistor 7. In this case, although a potential at a node E is clamped with reference to a node G, a potential at the node G is increased due to the resistor 7 and an electric current; as a result, it is not possible to suppress the potential to a sufficiently small voltage capable of protecting a gate insulating film. However, when a diode 102 is connected as a second constant-voltage clamping element, it is connected to a power-supply wiring part which is different from the MOS FET 4; as a result, it is possible to clamp a potential at a node F to a sufficiently small potential. In this case, a current- limiting resistor 101 functions so as to limit an electric current flowing through the diode 102 and a resistor 9 and to suppress an increase of the potential at the node F.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and in particular to an MIS (Metal-I n5olator) such as an insulated gate field effect transistor (hereinafter referred to as MOS-FET).
The present invention relates to a protection device for a 3-3amiconductor type device.

[Conventional technology]

Conventionally, with regard to protection devices for MIS type elements such as MOS-FETs, for example, as described in Japanese Patent Laid-Open No. 60-767, a constant voltage clamp element forming a protection element and a protected MO3-FET are used. Each was formed in a different region in the semiconductor substrate, and each was connected to a power supply terminal.

FIG. 2 is an explanatory diagram of a conventional protection device for MIS elements such as MOS-FET, and (a) is a circuit diagram.

(b) is a cross-sectional structural diagram of the device, and (c) and (d) are characteristic diagrams of internal voltage and current versus time.

In Fig. 2(,a), 1 is an input terminal, 2 is a first constant voltage clamp element, 3 is a first current limiting resistor, and 4 is a second
constant voltage clamp element, 5 is protected MIS-FET, 6
is the parasitic resistance of the wiring for fixing the anodes of the diodes forming the constant voltage clamping elements 2 and 4 to a predetermined potential, 7
8 is a parasitic resistance of wiring for fixing the substrate potential of the protected MIS-FET to a predetermined potential, 8 is a ground terminal, and 9 is a second current limiting resistor. As shown in FIG. 2(a), in this protection device, constant voltage clamp elements 2 and 4
This prevents the gate oxide film of the protected MO3-FET 5 from being damaged by electrostatic discharge.

In FIG. 2(b), 10 is an n-type semiconductor substrate, 11.
12 is an n-type region formed in an n-type substrate; 14.
15 are n-type regions for forming the constant voltage clamp elements 2.4, 17 and 19 are n-type regions for forming the drain and source of the MOS-FET, and 18 is a p-type region for forming the gate. It is a substance.

Conventionally, constant voltage clamp elements 2 and 4, pn
It utilizes reverse breakdown of junctions. That is, when a voltage higher than the specified voltage is applied between the input terminal 1 and the ground terminal 8, the pn junction of the constant voltage clamp elements 2 and 4 is destroyed, and the gate oxide film of the protected MO8-FET 5 is damaged. I was protecting her.

Further, the n-type region 11 in FIG. 2B is fixed to the ground potential G through the n-type region 13.16 that forms an ohmic connection. On the other hand, drain 17. A MOS-FET consisting of a gate 18 and a source 19 has a gate oxide film 21 between them.

Generally, the cause of destruction of the gate oxide film of an input circuit is that noise entering from the input pad during operation adversely affects the internal circuit. Therefore, a constant voltage clamp element for protection is usually provided in a region different from these internal circuits (regions 12 and 11 are different regions).

(b) In the figure, when static electricity is applied to the input pad 1, the charge passes through the current limiting resistor 9, passes through the first pn junction consisting of the n-type region 14 and the n-type region 11, and passes through the node G (the n-type region ) is bypassed. At this time,
Since the first pn junction has an internal parasitic resistance, a potential difference is generated with respect to the flowing current. Therefore, the potential of node E increases with respect to node G. Therefore, in the protection device shown in FIG. 2, the potential of node F is lowered by a second constant voltage clamp element consisting of n-type region 15 and n-type region 11 connected to node F through second current limiting resistor 3. This is intended to protect the gate insulating film 21 of the MO8-FET to be protected.

[Problem that the invention seeks to solve]

In this way, in the conventional technology, two constant voltage clamp elements are used.
This is an extremely effective method in that the voltage caused by static electricity can be effectively lowered by providing one or more of them. However, in recent years, as integrated circuits have become larger,
The following problems have arisen. That is, in FIG. 2(b), the parasitic resistance 6 shown in FIG. 2(a) necessarily exists in the wiring for fixing the region 11 to the ground potential, but this resistance 6 has become larger in recent years. Ta. As a result, when static electricity is applied, a large potential difference is generated when the charge passes through the resistor 6, so that the potential of the node E increases more than expected. Therefore, even if the voltage between the points FG is kept low, an excessive potential difference is applied to the gate oxide film 21, which may lead to electrostatic damage.

In order to suppress this phenomenon, the current limiting resistor 9 may be made sufficiently large. However, when this current limiting resistor 9 cannot be used, for example when a data input/output pin is used, the above-mentioned situation becomes even more severe.

FIGS. 2(Q) and (d) are characteristic diagrams of internal voltage and current when static electricity is applied to a conventional protection device. Here, VDtVE, VF, and VC represent the respective potentials of nodes D, E, F, and G in FIGS. 2(a) and (b). ,
represents the current flowing through nodes D and F.

Input terminal 1 (node D) of the protective device shown in Fig. 2(a)
When static electricity, that is, electricity that initially has a unique charge and voltage, is applied to the node D, the internal voltage at node D is as shown in Figure 2 (c).
V. It decreases over time along the curve shown in . Along with this, the node E, F, G (7) voltage also changes to VD
, VE-VF, decreases with time as shown in Vc. Here, vo indicated by a thick line indicates the clamp voltage by the first and second constant voltage clamp elements 2.4.

When static electricity with an initial voltage vT is applied to input terminal 1, a current is generated at that location. flows, but this decreases exponentially as the discharge by the constant voltage clamp elements 2 and 4 progresses. Most of this current will flow from resistor 9 through resistor 6.

At the moment when static electricity is applied, voltage VT is divided between resistor 9, clamp element 2, and resistor 6. Therefore,
The following voltages are applied to node E at maximum.

Here, R6 and R9 are the values of resistor 6 and resistor 9, respectively. That is, due to the existence of the resistance value R6, V
The potential of c increases, and this potential is superimposed on the clamp voltage. In other words, Va is the protected MIS-FET5
As the permanent breakdown pressure of, if the conditions of are satisfied,
There is a problem that the insulating film is destroyed.

Usually, the protection element is designed so that the condition of the above formula (2) is not satisfied by increasing the current limiting resistor R9 and decreasing the power supply resistor R6.

However, as mentioned above, for data input/output terminals, etc., where the resistor 9 cannot be intentionally added due to circuit operation,
Since R9 becomes only a parasitic resistance and has a very small value, the value of R6/ (R6 + R9) in the above equation (1) increases, and the voltage generated in the power supply wiring is applied to the gate electrode of the protected element. However, there was a problem in that the gate insulating film was destroyed.

The purpose of the present invention is to improve this problem, and to sufficiently increase the electrostatic breakdown voltage even when there is no current limiting resistor connected to the input terminal of the protection element, or when only an extremely small value resistor can be connected. An object of the present invention is to provide a semiconductor integrated circuit that can perform the following steps.

[Means for solving problems]

In order to achieve the above object, the semiconductor integrated circuit of the present invention includes:
A first constant voltage clamp element and a second constant voltage clamp element are formed in different first and second regions, and the potential of each region is connected to a predetermined power supply terminal via an ohmic contact means. In addition, the present invention is characterized in that a current limiting resistor is used between the first constant voltage clamp element and the second constant voltage clamp element. Furthermore, a second current limiting resistor is connected to the rear stage of the first constant voltage clamp element, and a second constant voltage clamp element is connected to the rear stage of the first constant voltage clamp element. Another feature is that the other terminals are connected by different power supply wiring.

[For production]

In the first invention (corresponding to claim 1), the first constant voltage clamp element and the second constant voltage clamp element are formed in different regions, and the potential of each region is The first constant voltage clamp element and the second constant voltage clamp element are connected to a predetermined power supply terminal via an ohmic contact means.
Since a current limiting resistor is used between the constant voltage clamp elements, they are necessarily connected by different power supply wirings. Therefore, when static electricity is applied to the input pin of an integrated circuit, the static electricity is bypassed by the first constant voltage clamp element, and the parasitic resistance that inevitably occurs in the power supply wiring connected to the first constant voltage clamp element is increased. The generated potential difference can be lowered by the second constant voltage clamp element. This is particularly effective for data input/output pins where current limiting resistors cannot be inserted.

Next, in the second invention (corresponding to claim 4), the first constant voltage clamp element and the second constant voltage clamp element are connected to the power supply terminal by the first and second power supply wirings, respectively. Therefore, when a current flows from the first constant voltage clamp element to the power supply wiring, the voltage generated in the power supply wiring can be clamped by the second constant voltage clamp element, and as a result, It is possible to prevent excessive voltage from being applied to the gate insulating film of the protected MIS-FET.

In addition, the current limiting resistor between the first constant voltage clamp element and the second constant voltage clamp element limits the current flowing to the second constant voltage clamp element, and prevents parasitic current flowing into the second constant voltage clamp element. Preventing potential rise due to the resistor and the second power supply wiring connected to the second constant voltage clamp element,
It also serves to prevent the junction of the second constant voltage clamp element from being thermally destroyed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The configuration and effects of the present invention will be briefly described with reference to FIG. FIG. 3(a) is a circuit diagram of a conventional protection device shown for comparison, FIG. 3(b) is a circuit diagram of a protection device of the present invention, and FIG. 3(c) is a circuit diagram of a semiconductor integrated protection device. The layout of the protection device on the circuit, Figure 3(d) shows the MIS-FE protected by the parasitic resistance R1 of the power supply shown in (b).
FIG. 3 is a characteristic diagram of the voltage applied to the gate insulating film of T.

In FIG. 3(a), the first constant current limiting resistor is R7
1. The first constant voltage clamp element is CL, and the parasitic resistance of the power supply connected to the first constant voltage clamp element CL is R8. On the other hand, in FIG. 3(b), in addition to these elements, there is a second current limiting resistor R0, a second constant voltage clamping element CL2, and a parasitic resistor R of the power supply.
8' is provided. Since the first constant voltage clamp element CL and the second constant voltage clamp element CL2 are connected to separate power supply wirings (resistors Rs1.Rν), the first
Since the voltage generated when current flows from the constant voltage clamp element CL to the power supply wiring R81 can be clamped by the second constant voltage clamp element CL2, M, l
No excessive voltage is applied to the gate insulating film of the 5-FET.

In FIG. 3(C), on the semiconductor integrated circuit, (b)
This shows how the elements shown in Figure 1 are arranged. A large number of input terminals 1 are arranged on the chip according to the number of input signals, and each is connected to a constant voltage clamp element CL through a resistor R1. The power supply wiring of the constant voltage clamp element is connected from the power supply terminal 8 to all the clamp elements, but as shown in the figure, the value of the parasitic resistance of the power supply differs depending on the order of the clamp element. Figure 3(c)
, Ml is an MI protected by conventional methods
S-FET, and M2 is a MI S-FET protected by the method of the present invention.

Among the curves ■, ■, and ■ in FIG. 3(d), ■ is a curve showing the characteristics of the conventional protection device, and shows the case where the value of the input resistance R1 is relatively large. This voltage is expressed by the previous formula (1)
Similarly, it is expressed by a linear equation.

This voltage increases as the parasitic resistance R8 of the power supply increases, provided the input resistance RPL is large.

Since the voltage applied to the input terminal drops considerably at the input resistor R21, it does not exceed the breakdown voltage VB of the gate insulating film. In addition, ■ in the figure indicates a case where the input resistance R21 is small, and for example, a special resistance cannot be used due to normal circuit operation, and R1□ is only a parasitic resistance of the connection. be. If the parasitic resistance R of the power supply is small, it will not exceed the breakdown voltage VB of the insulating film, but if the parasitic resistance R8 becomes large, the breakdown voltage will be exceeded.
That is, it is far away from the power supply terminal 8, and the parasitic resistance R
In the case of a protection element with a large value of 8, the protection function is not sufficient.

Next, ■ in FIG. 1 shows the voltage applied to the gate insulating film when the present invention is used. In the present invention, the second constant voltage clamp element CL2 is used, and since this clamp element CL2 uses a different power supply wiring from the first constant voltage clamp element CL, the clamp voltage of the second constant voltage clamp element CL2 is Only a small amount of the insulating film is applied to the gate insulating film of the protected MIS-FET, and as a result, the insulating film is not destroyed.

That is, as shown in the figure, the second constant voltage clamp element C
The clamp voltage VC of L2 maintains a substantially constant value regardless of the parasitic resistance R8 of the power supply.

FIG. 1 is a circuit diagram, a layout diagram on a semiconductor substrate, and an internal waveform diagram of a protection device showing a first embodiment of the present invention. In FIG. 1, MO is used as the first constant voltage clamp element.
A case is shown in which a diode is used as the S-FET and a second constant voltage clamp element, respectively.

In FIG. 1(A), 1 is the input terminal (node D), 2
is a protection resistor, 3 is a node E, 4 is a MOS-FET,
This is a first constant voltage clamp element using surface breakdown. 5 is a protected MIS-FET, 6 is a terminal connected to the power supply wiring of the first constant voltage clamp element 4, and 7 is a parasitic resistance of the ground wiring connected to the bypass element. Also,
101 is a second protective resistor, 102 is a diode that is a second constant voltage clamp element, and 103 is a ground terminal (node G
), 8 is a terminal connected to the power supply wiring of the second constant voltage clamp element 102, and 9 is a parasitic resistance of the ground wiring connected to the MIS-FET 5. Further, 30 is a second node F.

On the semiconductor chip, as shown in FIG. 1(b), the power supply or ground wiring of the protection element 4 and the protected MIS-FE
The ground wiring is separated from the power supply or ground wiring for the internal circuit including T5. Namely.

The ground wiring of the MOS-FET4, which is the first constant voltage clamp element, is connected to the ground terminal 103 (node G) via the parasitic resistor 7, while the ground wiring of the second constant voltage clamp element, which includes the MIS-FET5, is , parasitic resistances 9 and 9'
It is connected to ground terminal 103 (node G) via.

The effects of this embodiment will be described with reference to FIGS. 1(c) and 1(d).

Now, when static electricity is applied to terminal 1, current I at input node D. mainly includes the protective resistor 2, the first constant voltage clamp element 4. and flows to the ground terminal 103 through the parasitic resistance 7 (see FIG. 1(d)). In this case, the potential of node E will be clamped with respect to node G, but since the potential of node G will rise due to the resistor 7 and the current, it will be small enough to protect the gate insulating film. It cannot be suppressed by voltage. That is, as shown in FIG. 1(c), the potential V of the node G. is higher than the ground potential at the moment static electricity is applied, and this value decreases over time, but the breakdown voltage Va
Don't go lower.

However, in this embodiment, a diode 102 is connected as the second constant voltage clamp element, and this diode 1
Since node 02 is connected to a power supply wiring different from that of MOS-FET 4, the potential of node F can be clamped to a sufficiently low potential (see v2 in FIG. 1(c)). At this time, the current limiting resistor 101 operates to limit the current flowing through the diode 102 and the resistor 9, and suppress the rise in the potential of the node F (see FIG. 1(d)).

FIG. 4 is a circuit diagram of a protection device showing a second embodiment of the present invention.

In this embodiment, as the first bypass element, a parasitic MO
5-FET31 is used. The second bypass element is the diode 102 as in the previous example. That is, M
The gate and source of the OS-FET 31 are connected to operate as a diode, and the potential applied to the input terminal 1 is applied to the gate to control the passing current of the MOS-FET 31. In this way, in this embodiment, by inserting the second bypass element 102 between the node 30 and the node 8, regardless of the type of the first bypass element, the MI
Breakdown of the gate insulating film of the S-FET 5 can be prevented.

FIG. 6 is a circuit diagram of a protection device according to a third embodiment of the present invention, and shows a case where the present invention is implemented at an input/output terminal for inputting or outputting data. 108
110 is an output circuit section, 110 is an internal circuit section including an input circuit, and 104 and 405 are MOs forming a push-pull circuit.
This is an S-FET, and the other symbols that are the same as in FIG. 4 represent the same elements and parts. 1 is the input terminal, 106,1
07 is a push-pull output terminal, and external capacitive load (
Data is output by charging and discharging the battery (not shown). MOS-FET5 is MO for inputting data.
It is an S-FET.

Here, when static electricity is applied to terminal 1, the current flows through the MOS
- will be discharged through FET 4 and further through node 6. In the first and second embodiments, by increasing the protective resistance 2, it is possible to reduce the current flowing through the parasitic resistance 7 of the ground wiring, thereby reducing the voltage applied to the gate oxide film of the MIS/FET 5. However, in the case of the third embodiment shown in FIG. 5, the protection resistor 2 cannot be added to ensure the TTL interface during data output. Also, during normal circuit operation, the MOS-FET
Since a large current flows through the circuit 104, noise due to parasitic paper and F is generated, and this noise adversely affects the internal circuit. In order to avoid this influence, as shown in Figure 1, an internal circuit section 11 including an output circuit section 1o8 and an input circuit.
It is common practice to place the 0 and 0 at a separate location, and to use ground wiring and power wiring. Due to this situation, if static electricity is applied to the input terminal 1 without applying this embodiment to the input/output pins, the MIS-FE
The voltage applied to the gate oxide film of T5 increases. Therefore, for the input/output pin, the protective resistor according to this embodiment is 10
1 and the diode 102 are required to protect the gate oxide film of the MI S-FET 5 more than in the first and second embodiments.

FIG. 6 is a circuit diagram of a protection device showing a fourth embodiment of the present invention.

In this embodiment, as the second constant voltage clamp element, MO
I am using S-FETIIO. That is, MOS
- Connect the gate and source of the FET to operate it as a diode. In addition, in this example, a MOS-FE using surface breakdown is used as a bypass element.
Since T is used, the breakdown voltage is lower than when a diode is used, and it is possible to further reduce the voltage applied to the gate oxide film of the MIS-FET 5.

FIG. 7 is a circuit diagram of a protection device showing a fifth embodiment of the present invention.

In this example, the constant voltage clamp element is a MOS
-The case where it is provided on the power supply terminal side like FET34 is shown. In this case, when static electricity is applied to the input terminal 1, a current flows not only to the parasitic resistance 7 on the ground wiring side but also to the parasitic resistance 35 on the power wiring side. At this time, a potential difference is generated and the potential of the node 36 increases, and this potential increase destroys the gate oxide film of the P-type MOS-FET 31 whose substrate potential is the power supply potential. Therefore, as shown in FIG. 7, by inserting a diode 111 between the gate electrode and the source electrode of the MOS-FET 31 through the protective resistor 101, the voltage applied to the gate oxide film of the MOS-FET 31 is reduced, thereby preventing electrostatic damage. The withstand pressure can be increased.

FIG. 8 is a circuit diagram of a protection device showing a sixth embodiment of the present invention.

In the embodiment shown in FIG. 7, the input protection resistor 2 can be inserted, but in the embodiment shown in FIG. cannot be used. Therefore, when the second constant voltage clamp element is not provided, the current flowing through the parasitic resistors 7 and 35 increases, and the voltage applied to the gate insulating films of the MOS-FETs 32 and 5 increases. As shown in FIG. 8, a protective resistor 101, diodes 102 and 111
By inserting MOS-FETs 32 and 5, the voltage applied to the gate oxide films of MOS-FETs 32 and 5 can be reduced.

FIG. 9 is a layout diagram of a protection circuit on a semiconductor substrate showing a seventh embodiment of the present invention.

A terminal 103 that provides a ground potential and a terminal 108 that provides a power supply potential are arranged on the board, and these terminals supply the power supply potential and the ground potential to the protection element and the internal circuit, respectively, as shown in FIG. ing. Here, the protection elements 34 and 4 and the NMOS-FET 1 constituting the output buffer are
05 and 104 are arranged as a group in the aggregate 112. Also, as an internal circuit, this aggregate 11
A circuit group formed in a region separate from 2 is arranged. In this embodiment, when static electricity is applied to input terminal 1, NM
Since a large current flows through OS-FET104 and 105,
By arranging the clamp element in the same area as the NMOS-'FET of the output buffer, the provided area can be effectively utilized. In addition, MOS-FET5, 31
Since the protection resistor 101 is connected to the diodes 102 and 111 connected in front of the diodes 102 and 111, only a small current flows and a small area is required. In the circuit area, the allowable product is often small, but in this embodiment, a protective element with high electrostatic breakdown voltage can be manufactured while effectively using a small area. In the figure, numerals 7 and 9 are parasitic resistances of ground wirings provided separately for the two clamp elements, and 33 and 35 are parasitic resistances of power supply wirings also provided separately.

FIG. 10 is a sectional view on a semiconductor chip showing an example of a constant voltage clamp element according to the present invention.

In the figure, 113 is an n-type substrate, 114 is a p-type well,
115, 117, 119 are n-type high concentration impurity layers, 116
is a p-type high concentration impurity layer, 118 is a conductive layer, and 1
Reference numerals 18, 117, and 119 form parasitic M*S-FETs having a gate, a source, and a drain, respectively. Normally, node 8 is fixed to the ground potential, and node 32 is fixed to the power supply potential.

Now, when a potential is applied to the input terminal 112, a current flows from the region 119 to the region 117. In addition, since the high concentration impurity layer 119, the p-type well 114, and the base 113 form an npn bipolar structure, the current flows from the region 119 to the region 117. A current flows from the terminal 112 to the base body 113 due to the vertical bipolar operation, and reaches the terminal 32 from the region 115. Therefore, this element acts as a constant voltage clamp not only on terminal 112 but also on terminal 32. A circuit using this element is 1
This will be explained with reference to FIG. 11 below.

FIG. 11 is a circuit diagram of a protection device showing an eighth embodiment of the present invention, in which the element shown in FIG. 10 is used as a constant voltage clamp element 120, 121 for protecting the gate. It is. With the structure shown in FIG. 10, one element can connect the source terminal 8 of MI S-FET 5 and
A constant voltage clamp element is formed at the source terminal 32 of the S-FET 31, so that the voltage applied to the parasitic resistors 7 and 35 is
It is possible to avoid applying voltage to the gate insulating films of MIS-FETs 5 and 3↓. That is, by connecting the terminals 112 and 32 in FIG. 10 to the terminals 8 and 32 in FIG. 11, respectively, the bipolar transistor 121 in FIG. and 118 and 117 to form the MOS-FE in Fig. 11.
It constitutes T120.

FIG. 12 is a sectional view of a semiconductor chip showing a ninth embodiment of the present invention.

In FIG. 12, 210 is a semiconductor substrate, 211 is a first
A first region of conductivity type, 228, a second region of first conductivity type, 2
14 is a third region of the second conductivity type for forming a constant voltage clamp element, 226 is a fourth region of the second conductivity type, and 203 is a current limiting resistor.

In this embodiment, for the sake of explanation, the first conductivity type is assumed to be P type, and the second conductivity type is assumed to be N type. As the first constant voltage clamp element,
A MOS-FET is used in which regions 214, 223, and 222 serve as a drain, gate, and source, respectively, and are formed in a p-type well 211. This p-type well 21
1 is connected by ohmic electrodes 213 and 216 to a pad 208 that provides a ground potential, and a parasitic resistance 206 is inevitably present in the wiring between them.

On the other hand, within the p-type well 228, there is an n-type layer 226,
Regions 228 and 226 form a pn junction, and the second
This forms a constant voltage clamp element. Also, within the same well 228, regions 217, 218, and 219 are used as drain and gate regions, respectively.

A protected MO8-FET serving as a source is formed.

Note that 224 and 221 in the p-type wells 211 and 228 are gate oxide films of the MOS-FET. p
The mold well 228 has ohmic junctions 225, 227, 2
20 and is connected to a ground electrode pad 208 .

At this time, a parasitic resistance 207 necessarily exists in the ground wiring.

Further, 209 and 203 are current limiting resistors, which are made of a resistor such as polycrystalline silicon, doped semiconductor, or silicide.

Now, when static electricity is applied to pad 201, the current is 2
It flows to the ground terminal 208 through the path 09→214→211→222→206→208. At this time, the MOS
- Since a constant voltage clamp element using a FET is used, the potential difference between regions 214 and 222 is kept almost constant. However, since the parasitic resistance 206 exists, a current flows there, and the potential at the 0 point increases. As a result, the voltage potential rises to such an extent that the gate oxide film 221 cannot be protected. Therefore, the voltage is clamped by a diode 226 provided in a separate well 228 via a second current limiting resistor 203. By lowering the node voltage at point B, excessive voltage is prevented from being applied to gate oxide film 221. At this time, current limiting resistor 2
03 serves to limit the current flowing to the second constant voltage clamp element, thereby reducing the voltage generated by the parasitic resistance inside the clamp element. Also during normal operation.

If excessive noise is input to input pin 201,
Because of the current limiting resistor 203, the current due to noise mainly flows through the region 214, and the internal circuit formed in the well 228 will not malfunction.

FIG. 13 is a circuit diagram and a plan layout diagram of a protection device showing a tenth embodiment of the present invention.

In FIG. 13, 229 is a MOS-FET which is a first constant voltage clamp element, 230 is a diode which is a second constant voltage clamp element, and 231 is a protected MO3-FET.
It is. The regions surrounded by broken lines 232 and 233 indicate that they are formed in different regions within the semiconductor. Therefore, wiring for fixing the potential to a predetermined potential is connected to each of the regions 232 and 233, but parasitic resistances 206 and 207 are inevitably present in each wiring.

In this embodiment, in order to reduce the voltage generated in the parasitic resistance existing in the ground wiring of the ground resistor 207, the MOS-FE
It protects the gate oxide film of T229.

FIG. 14 is a sectional view of a semiconductor chip showing an eleventh embodiment of the present invention.

In this embodiment, regions 234, 235, and 237 are used as a drain, a gate, and a second constant voltage clamp element, respectively.
- This Mo using a MOS-FET as a source
5-FET corresponds to 238 in FIG. 14(b).

As a result, as in the embodiment shown in FIG. 12, the voltage generated across the parasitic resistance 206 is not directly applied to the MO8-FET to be protected, so that the IMOs-FET to be tested can be protected from electrostatic damage. That is, as in this embodiment, M with the gate grounded as the second constant voltage clamp element
When using an o8-FET, the effect of the - layer can be expected because it breaks down at a lower voltage than when using a diode, that is, the clamp voltage is lower.

FIG. 15 is a cross-sectional view and a circuit diagram of a semiconductor chip showing a twelfth embodiment of the present invention.

In this embodiment, a diode 239 is formed by a p-type semiconductor region 231 and an n-type semiconductor region 229 as a second constant voltage clamp element.

In this case, it is conceivable that the potential at point B also increases due to the current flowing through the parasitic resistance 271 of the power supply connected to the well 231; The current flowing through the constant voltage clamp element 232 is small, and the rise in the potential at point B can be suppressed to a small level. At this time, most of the charge flowing into the terminal 201 passes through the Mo8-FET 229 and is bypassed to the ground terminal 208. Therefore, the protected MO5-FET231
The voltage applied to the gate of can be made sufficiently small.

FIG. 16 is a sectional view and circuit diagram of a semiconductor chip showing a thirteenth embodiment of the present invention.

This embodiment shows a case where a Mo5-FET is used in place of the diode of the second constant voltage clamp element in FIG. 15. This makes it possible to lower the clamp voltage and increase the effect of the negative layer. Figure 16(a)
, regions 214 and 223 of the first well 211
, 222, the first constant voltage clamp element Mo8-
FET is formed in the region 234 of the second well 231,
MO which is the second constant voltage clamp element at 235°236
S-FET is formed and the region 21 of the third well 212
9.218 and 217 form a protected MO5-FET.

FIG. 17 is a sectional view and a circuit diagram of a semiconductor chip showing a fourteenth embodiment of the present invention.

The case where the protected element is a CMo8-FET consisting of an nMo5-FET and a 9MO8-FET is shown. In figure (b), 257 is 9MO3-F of 0M08 circuit
ET, 229, 256 is a constant voltage clamp element nM
o8-FET, 242 is a power supply terminal, 243 and 244 are parasitic resistances parasitic to the power supply terminal, and 238 is an nMOS-FET which is a second constant voltage clamp element. In figure (a), 245.252 are each Mo5-FET252
The gate electrodes 57, 246 and 253 are Mo8-, respectively.
Gate oxide film of FET256, 257, 247.249
, 250 is an n-type impurity region, 248.251, 254
is a p-type impurity region.

201 is an input terminal, 208 is a power supply terminal, and 242 is a ground terminal.
3-A region 258 where FET 258 is formed and nMo
The region 259 where the 8-FET 259 is formed is formed in a different region. As the first constant voltage clamp element, a Mo3-FET 229 is used on the ground potential side, and a MOS-FET 256 is used on the power supply potential side. On the other hand, a larger parasitic capacitance exists between the power supply terminal 242 and the ground terminal 208 due to the circuit within the chip. Therefore, for high-speed phenomena such as when static electricity is applied,
The terminal 242 and the terminal 208 are equivalent to a conductive state. Therefore, when static electricity is applied to the input terminal 201, current flows through both the Mo3-FETs 229 and 256, creating a potential difference between the parasitic resistors 206 and 243.
This potential is applied to the gate oxide films of MO≦・FETs 257 and 231, but by lowering the voltage using the constant voltage clamp element 238 and current limiting resistor 203, the gate oxide films of Mo8-FETs 257 and 231 are applied. Protect from destruction.

FIG. 18 is a cross-sectional view on a semiconductor chip and a circuit diagram showing a fifteenth embodiment of the present invention.

In this embodiment, the protection element is used at the data input/output terminal of the CMO3 circuit. In figure (b), 268,
269 is a 1MO8-FET for outputting data to the input/output terminal 201, and outputs data according to the output signal applied to the input terminals 266 and 267. On the other hand, p
A circuit consisting of MO5-FET 257 and nMO5-FET 259 is a circuit for inputting the signal given to terminal 201. 0 where a signal is input from terminal 255
In figure (a), regions 214, 259, and 261 are MOS-
These are the drain, gate, and source of the FET 269, and the regions 265, 263, and 262 are the MOS-FET 268 (
7) Drain, gate, and source. In the case of a terminal that outputs data as in this embodiment, using the current limiting resistor 209 at the input as in the previous embodiment
It is extremely difficult to secure input/output interfaces.

Therefore, when static electricity is applied to the terminal 201, M
A very large current will flow through OS-FETs 268, 269, 256, 229 into parasitic resistances 206 and 243. Therefore, the power terminal 242 and the ground terminal 2
The potential increase at 08 is also large. Therefore, in this embodiment, a large voltage is not applied to the gate insulating films of the MOS-FETs 257 and 231 by providing the current limiting resistor 203 and the MOS-FET 238 which is a second constant voltage clamp element.

FIG. 19 is a diagram of electrostatic breakdown test results showing the 16th embodiment of the present invention.

Figure (a) is a diagram showing a test method. First, the chip is charged through a 100 MΩ resistor to the device. This charging is done to the stray capacitance between the chip and ground.

The value of this stray capacitance is typically in the range of 1 to 10 pF. This charged device discharges the charge from the test pin by closing the switch. This testing method is commonly referred to as the Charsito-Device method.

Since the capacitance is small, the electrostatic energy is small, but since there is no resistance during discharge, a large current flows the moment the switch is closed. Therefore, in the present invention, the effects of this charsite device method are particularly remarkable.

Figure (b) shows the result of applying this embodiment to data input/output pins. These protection elements are not particularly connected to the first current limiting resistor, and only have parasitic resistance. Here, the data is when the present invention is not applied to the pins with pin numbers 1, 2, and 4, that is, when there is no second constant voltage clamp element, and the data is when the present invention is applied to the pins with pin number 3. Indicates the case where Also, the smaller the pin number, the more the terminal Vas that provides the ground potential.
This is a pin located close to . In Figure (b), the gate insulating film is destroyed at a voltage of 2000V or less for pins with pin numbers 1 and 2.4, and the farther from the vs8 terminal, the weaker the 0 lines. The pin number 3 to which the invention was applied did not break even at 3000V, demonstrating the effectiveness of the invention.

Note that in the previous embodiments, the current limiting resistor 9 inserted is not necessarily an essential requirement; rather, the effects of the present invention are significant without this resistor.

As described above, in each embodiment of the present invention, when static electricity is applied to the input pin of an integrated circuit, the static electricity is bypassed by the first constant voltage clamp element; The second constant voltage clamp element can reduce the potential difference generated in the parasitic resistance that is inevitably parasitic in the power supply wiring connected to the power supply wiring. Therefore, if the parasitic resistance of the power supply wiring is large, and if a current limiting resistor cannot be inserted between the first constant voltage clamp element and the input pin due to circuit operation, the potential difference generated across the parasitic resistor will become large. According to the invention, it is possible to avoid such adverse effects. According to the present invention, electrostatic damage can be prevented against static electricity at a voltage more than twice that of the conventional method, especially in the case of data input/output pins in which a current limiting resistor cannot be inserted.

〔Effect of the invention〕

As explained above, according to the present invention, even if there is no current limiting resistor to be connected to the input terminal, the electrostatic breakdown voltage can be sufficiently increased.
It is possible to effectively protect the gate insulating film.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram, layout diagram, and internal characteristic diagram of a protection element on a semiconductor chip showing a first embodiment of the present invention, and FIG. 2 is a circuit diagram, sectional view, and internal characteristic diagram of a protection element on a conventional semiconductor chip. Internal characteristic diagram, Figure 3 is a circuit diagram, chip layout diagram, and internal voltage characteristic diagram for comparing the conventional and the present invention.
Fig. 4 is a circuit diagram of a protection element on a semiconductor chip showing a second embodiment of the present invention, Fig. 5 is a circuit diagram showing a third embodiment of the invention, and Fig. 6 is a modification of Fig. 5. Circuit diagram showing an example, No. 7
The figure is a circuit diagram showing a fourth embodiment of the invention, FIG. 8 is a circuit diagram showing a fifth embodiment of the invention, and FIG. 9 is a circuit diagram showing a sixth embodiment of the invention.
Layout diagram on a semiconductor chip showing an example of
11 is a cross-sectional view of a protection element on a semiconductor chip showing a seventh embodiment of the present invention, FIG. 11 is a circuit diagram showing an application of FIG. 10, and FIG. 12 is a circuit diagram showing an application of FIG. 13 is a sectional view of a protection element showing a ninth embodiment of the present invention, FIG. 13 is a circuit layout diagram and a circuit layout diagram showing a tenth embodiment of the present invention, and FIG. FIG. 15 is a cross-sectional view and circuit layout diagram showing the twelfth embodiment of the present invention, and FIG. 16 is a cross-sectional diagram and circuit diagram showing the thirteenth embodiment of the present invention. Circuit layout diagram, 1st
7 is a sectional view and circuit layout diagram showing the 14th embodiment of the present invention, FIG. 18 is a sectional diagram and circuit layout diagram showing the 15th embodiment of the invention, and FIG. 1st
It is an explanatory view of the results of an electrostatic breakdown test showing a sixth example. 1.201: Input terminal, 2,101,209': Protection resistor, 4: MO8-FET for bypass, 7,9°33.3
5,206,207,271,243°244: Parasitic resistance in ground wiring and power supply wiring, 5,231,2
57: Protected MO8-FET, 102.123: Bypass diode, 31: Parasitic MO3-FET for bypass
, 211: first area, 228, 231: second area, 2
14: Third area, 226.2-34, 229: Fourth area. Figure 1 Prisoner Figure 1 CB) Figure 1 (C) Figure 2 (&) Figure 2 Figure 2 (C) Time Time Figure 3 (a) Figure 3 (d) (R White 1"R82+ ... ) Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 10 Figure 11 Figure 12 Figure 13 Figure 13 CB) Figure 14 (a) Figure 15
16 Figure fal Figure 17 (b) Figure 18 (b) Figure 19 (a) Test pin (No. 3
is the present invention)

Claims (1)

[Claims] 1. A first constant voltage clamp element connected to an input terminal, a second current limiting resistor having one end connected to the input terminal, and a second current limiting resistor connected to the other end of the current limiting resistor. A semiconductor integrated circuit comprising a second constant voltage clamp element and a protected element protected by the second constant voltage clamp element, the semiconductor integrated circuit comprising a semiconductor substrate and a semiconductor substrate formed within the semiconductor substrate. The first constant voltage clamp element includes a first region and a second region of a first conductivity type, and the first constant voltage clamp element is formed at least in part by a third region of a second conductivity type formed in the first region. . A semiconductor integrated circuit, wherein the second constant voltage clamp element is at least partially formed by a fourth region of the second conductivity type formed within the second region. 2. The semiconductor integrated circuit according to claim 1, wherein the first region and the second region are connected to a predetermined operating potential via first and second ohmic contact means, respectively. Semiconductor integrated circuit. 3. In the semiconductor integrated circuit according to claim 1, regions in which an input circuit and an output circuit are formed are formed at separate positions on a semiconductor chip equipped with an input/output common terminal, and is the first voltage for fixing at a predetermined potential.
and a second power supply wiring, and a second constant voltage clamp element is connected to the second power supply wiring connected to the input circuit. 4. A first current limiting resistor connected to the input terminal; a first constant voltage clamp element connected to the other end of the current limiting resistor; one end of the constant voltage clamp element connected to the other end; is the first wiring connected to the first power supply terminal, and the first wiring connected to the first power terminal.
a second current limiting resistor connected to one end of a constant voltage clamp element, a second constant voltage clamp element connected to the other end of the current limiting resistor, and one end of the constant voltage clamp element connected to the second current limiting resistor; A second wiring whose other end is connected to a first power supply terminal, and a protected MIS/FET whose gate electrode or drain electrode is connected to the other end of the second current limiting resistor. Semiconductor integrated circuit. 5. The value of the first current limiting resistor is R_P, the clamp voltage of the first constant voltage clamp element is V_C, and the parasitic resistance of the first wiring is R_S, which will cause permanent destruction of the gate oxide film of the protected MIS/FET. Voltage is V_B, surge voltage is V_T
The semiconductor integrated circuit according to claim 4, wherein the semiconductor integrated circuit is used under the following conditions. V_B<(V_T-V_C)(R_P)/(R_P+R
_S)+V_C