JP2650276B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit (MI) such as an insulated gate type field effect transistor (hereinafter referred to as a MOS-FET).
The present invention relates to a protection device for an S (Metal-Insulator-Semiconductor) element.

[Conventional technology]

2. Description of the Related Art Conventionally, as for a protection device for an MIS type device such as a MOS / FET, for example, as described in JP-A-60-767, a constant voltage clamp device forming a protection device and a protected device are provided.
MOS FETs were formed in different regions of the semiconductor substrate, and were each connected to a power supply terminal.

FIG. 2 is an explanatory view of a conventional protection device for a MIS element such as a MOS-FET, in which (a) is a circuit diagram, (b) is a cross-sectional structure diagram of the device, (c) and (d) are internal voltages. FIG. 7 is a characteristic diagram with respect to time and current.

In FIG. 2 (a), 1 is an input terminal, 2 is a first constant voltage clamp element, 3 is a first current limiting resistor, and 4 is a second
Is a MIS-FET to be protected, 5 is a parasitic resistance of a wiring for fixing an anode of a diode forming the constant-voltage clamp elements 2 and 4 at a predetermined position, and 7 is a protected MIS-FET.
Parasitic resistance of wiring for fixing the substrate potential of the MIS • FET to a predetermined potential, 8 is a ground terminal, and 9 is a second current limiting resistor. As shown in FIG. 2 (a), in this protection device, the MOS-FET to be protected is
5 prevents the gate oxide film from being electrostatically damaged.

In FIG. 2B, reference numeral 10 denotes an n-type semiconductor substrate;
Is a p-type region formed in the n-type substrate, 14 and 15 are n-type regions for forming the constant voltage clamp elements 2 and 4, respectively, and 17 and 19 are drain and source of the MOSFET. An n-type region 18 to be formed is also a p-type material for forming a gate.

Conventionally, the reverse breakdown of the pn junction which is the constant voltage clamp elements 2 and 4 is used. That is,
When a voltage higher than the specified voltage is applied between the input terminal 1 and the ground terminal 8, the pn junction of the constant voltage clamp elements 2 and 4 is broken, thereby protecting the gate oxide film of the protected MOSFET 5. I was

Further, the p-type region 11 in FIG. 2B is fixed to the ground potential G through the p-type regions 13 and 16 that form ohmic connections. On the other hand, a MOS comprising a drain 17, a gate 18, and a source 19
In the FET, a gate oxide film 21 is provided between them. Generally, the cause of destruction of a gate oxide film of an input circuit is that noise entering from an input pad during operation adversely affects an internal circuit. Therefore, the constant voltage clamp element for protection is usually provided in a region different from these internal circuits (regions different from regions 12 and 11).

In FIG. 2B, when static electricity is applied to the input pad 1, the electric charge passes through the current limiting resistor 9, passes through the first pn junction including the n-type region 14 and the p-type region 11, and the node G
Bypassed (via the p-type region). At this time, since the first pn junction has an internal parasitic resistance, a potential difference occurs with respect to the flowing current. That is, the potential of the node E rises with respect to the node G. Therefore, in the protection device shown in FIG. 2, the potential of the node F is lowered by the second constant voltage clamp element including the n-type region 15 and the p-type region 11 connected to the node F through the second current limiting resistor 3. And protected MOS ・ F
This is to protect the gate insulating film 21 of the ET.

[Problems to be solved by the invention]

As described above, the conventional technique is an extremely effective method in that by providing two or more constant voltage clamp elements, the voltage due to static electricity can be effectively reduced. However, in recent years, as the size of an integrated circuit has increased, the following problem has occurred. That is, in FIG. 2B, the parasitic resistance 6 shown in FIG. 2A is necessarily present in the wiring for fixing the region 11 to the ground potential, but this resistance 6 has recently increased. Was. As a result, when static electricity is applied, a large potential difference occurs when the charge passes through the resistor 6, and the potential of the node E rises more than expected. Therefore, even if the voltage between the points FG is kept small, an excessive potential difference is applied to the gate oxide film 21, which may lead to electrostatic breakdown.

In order to suppress this development, the current limiting resistor 9 may be sufficiently increased. However, when the current limiting resistor 9 cannot be used, for example, when a data input / output pin is used, the above situation becomes more severe.

FIGS. 2C and 2D are characteristic diagrams of internal voltage and current when static electricity is applied to a conventional protection device. _{Here, V D, V E, V} F, V G , the node D in FIG. 2 (a) (b), E , F, represents the potential of G, I _D, I _F, the node D, Indicates the current flowing through F.

When static electricity, that is, electricity having an initial specific charge and voltage is initially applied to the input terminal 1 (node D) of the protection device shown in FIG. 2A, the internal voltage of the node D becomes as shown in FIG. It lowered with the lapse of time along a curve indicated by V _D) of. Accordingly, the voltages of the nodes E, F, and G also become V _D , V _E , V _F ,
It drops with time as shown in V _G. Here, V _C indicated by an arrow shows the first and second constant voltage clamp voltage by the clamp elements 2,4. Static electricity having an initial voltage V _T is applied to the input terminal 1, but flows current I _D in its place, which decreases exponentially as the discharge by constant voltage clamping elements 2 proceeds. Most of this current will flow from resistor 9 through resistor 6.

At the moment when static electricity is applied, the voltage V _T is divided between the resistor 9 and the clamp element 2 resistors 6 and bisection. Therefore,
The following maximum voltage is applied to the node E.

Here, R6 and R9 are the values of the resistor 6 and the resistor 9, respectively. That is, by resistance R6 is present, the potential of V _G is increased, the potential is to be superimposed on the clamp voltage. In other words, V _B is the permanent breakdown voltage of the protected MIS If the above condition is satisfied, there is a problem that the insulating film is broken.

Normally, the protection element is designed so as not to satisfy the condition of the above equation (2) by increasing the current limiting resistance R9 and decreasing the power supply resistance R6. However, as described above, in a data input / output terminal or the like where the resistor 9 cannot be consciously added due to the circuit operation, R9 is only a parasitic resistance and has a very small value. R6 / (R
6 + R9) becomes large, and the voltage generated in the power supply wiring is applied to the gate electrode of the protected element, which causes a problem that the gate insulating film is broken.

An object of the present invention is to improve such a problem and to sufficiently increase the electrostatic breakdown withstand voltage even when there is no current limiting resistor connected to the input terminal of the protection element, or even when only a very small resistance can be connected. It is to provide a semiconductor integrated circuit that can perform the operation.

[Means for solving the problem]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention has a first constant voltage clamp element and a second constant voltage clamp element formed in different first and second regions, respectively, The element is formed in the same area as the second constant voltage clamp element, the potential of each area is connected to a predetermined power supply terminal via ohmic contact means, and the first constant voltage clamp element and the second constant voltage clamp element are connected. It is characterized in that a current limiting resistor is used between the clamp elements. Further, a current limiting resistor is connected to a stage subsequent to the first constant voltage clamp element, and a second constant voltage clamp element is connected to a stage subsequent thereto, so that the other terminals of the first and second constant voltage clamp elements are connected. Are connected by different power supply wirings.

[Action]

In the first invention (corresponding to claim 1), the first constant voltage clamp element and the second constant voltage clamp element are formed in different areas, respectively, and the protected element is The potential of each region is formed in the same region as the second constant voltage clamp element, and the potential of each region is connected to a predetermined power supply terminal via ohmic contact means. Since a current limiting resistor is used between the clamp elements, they are necessarily connected by different power supply wirings. Therefore, when static electricity is applied to the input pin of the integrated circuit, the static electricity is bypassed by the first constant voltage clamp element, and the parasitic resistance inevitably occurs in the power supply wiring connected to the first constant voltage clamp element. The generated potential difference can be reduced by the second constant voltage clamp element. In particular, it is effective for a data input / output pin to which a current limiting resistor cannot be input.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The configuration and effects of the related art of the present invention will be outlined with reference to FIG. FIG. 3 (a) is a circuit diagram of a conventional protection device shown for comparison, and FIG. 3 (b)
Fig. 3 (c) is a circuit diagram of a protection device according to the related art.
Arrangement diagram of the protection device on a semiconductor integrated circuit, FIG. 3 (d) are a protected MI by the parasitic resistance R _S of the power supply shown in (b)
FIG. 4 is a characteristic diagram of a voltage applied to a gate insulating film of an S • FET.

In FIG. 3 (a), the first constant current limiting resistor is R
_P1, and the first constant voltage clamping element CL, the parasitic resistance of the power supply connected to the first constant voltage clamping element CL and the R _S. On the other hand, in FIG. 3B, in addition to these elements, a second current limiting resistor R _P2 , a second constant voltage clamp element CL2, and a parasitic resistance R _S ′ of the power supply are provided. ing. The first constant voltage clamp element CL and the second constant voltage clamp element CL2 are respectively provided with separate power supply wirings (resistors R _S1 ,
R _S ′), the voltage generated when a current flows from the first constant voltage clamp element CL to the power supply line R _S1 can be clamped by the second constant voltage clamp element CL2. As a result, it is not necessary to apply an excessive voltage to the gate insulating film of the MIS • FET.

In FIG. 3 (c), on the semiconductor integrated circuit,
It shows how the elements shown in (b) are arranged. A large number of input terminals 1 are arranged on the chip in accordance with the number of input signals, and each of the input terminals 1 is connected to a constant voltage clamp element CL through a resistor _RP1 . The power supply wiring of the constant voltage clamp element is connected from the power supply terminal 8 to all the clamp elements. However, as shown in the figure, the value of the parasitic resistance of the power supply differs depending on the position of the clamp element. In FIG. 3 (c), M1 was protected by a conventional method.
MISFET, and M2 is a MISFET protected by the method of the related art.

Among the curves ,, of FIG. 3 (d), is a curve showing the characteristics of a conventional protective device, which is a case where the value of the input resistor R _P is relatively large. This voltage is calculated by the equation (1)
Similarly, is expressed by the following equation.

This voltage increases as the parasitic resistance R _S of the power supply increases, but if the input resistance R _P1 is large, the voltage applied to the input terminal drops considerably at the input resistance R _P1 , so the gate insulation not exceed the breakdown voltage V _B of the film. Also, in the figure, the input resistance _RP1 is small, for example, a special resistor can not be used for the convenience of normal circuit operation,
In this case, R _P1 is only the connection parasitic resistance. When the parasitic resistance R _{S of the} power supply is small, the breakdown voltage V _B of the insulating film is not exceeded, but when the parasitic resistance R _S is large, the breakdown voltage is exceeded. That is, in the case of a protection element located far from the power supply terminal 8 and having a large parasitic resistance R _S , the protection function is not sufficient.

Next, the figure shows the voltage applied to the gate insulating film when the related technology is used. In this related technology, the second
Since the constant voltage clamp element CL2 is used, and since this clamp element CL2 uses a power supply line different from that of the first constant voltage clamp element CL, the second constant voltage clamp element CL2 is used.
Is applied to the gate insulating film of the protected MIS / FET, and as a result, the insulating film does not break down.
That is, as shown in FIG.
The clamp voltage V _{C of} 2 keeps a substantially constant value regardless of the parasitic resistance R _{S of the} power supply.

FIG. 1 is a circuit diagram of a protection device, a layout diagram on a semiconductor substrate, and an internal waveform diagram showing a first reference example of the present invention. In FIG. 1, MO is used as the first constant voltage clamp element.
The figure shows a case where an S-FET is used and a diode is used as a second constant voltage clamp element.

In FIG. 1A, reference numeral 1 denotes an input terminal (node D);
Reference numeral 2 denotes a protection resistor, 3 denotes a node E, and 4 denotes a MOS FET, which is a first constant voltage clamp element using surface breakdown.
5 is a protected MIS • FET, 6 is a terminal connected to the power supply wiring of the first constant voltage clamp element 4, and 7 is a parasitic resistance of a ground wiring connected to the bypass element. 101 is a second protection resistor, 102 is a diode as a second constant voltage clamp element, 103 is a ground terminal (node G), 8 is a terminal connected to the power supply wiring of the second constant voltage clamp element 102, 9 is MIS
This is the parasitic resistance of the ground wiring connected to FET5. Also, 30
Is a second node F.

On the semiconductor chip, as shown in FIG. 1B, the power supply or ground wiring of the protection element 4 and the power supply or ground wiring of the internal circuit including the protected MIS • FET 5 are separated from the ground wiring. . That is, the ground wiring of the MOS • FET4, which is the first constant voltage clamp element, is connected to the ground terminal 103 (node G) via the parasitic resistance 7, while the ground of the second constant voltage clamp element including the MIS • FET5 is grounded. The wiring is connected to ground terminal 103 (node G) via parasitic resistances 9 and 9 '.

The operation and effect of the present embodiment will be described with reference to FIGS.

Now, when the static electricity to the terminal 1 is applied, the current I _D of the input node D is mainly protective resistor 2, flows to the first constant-voltage clamping element 4, and through the parasitic resistor 7 ground terminal 103 (See FIG. 1 (d)). In this case, the potential of the node E is clamped with respect to the node G, but since the potential of the node G rises due to the resistance 7 and the current, the potential of the node G is sufficiently small to protect the gate insulating film. It cannot be suppressed to voltage. That is, as shown in FIG. 1 (c), the moment the potential V _G of the node G is electrostatically applied are elevated than the ground potential, but this value decreases with the passage of time, a certain amount of time not below the Tata not the breakdown voltage V _B.

However, in the present embodiment, the diode 102 is connected as the second constant voltage clamp element, and this diode 102
There because they are connected to different power supply wiring and the MOS · FET 4, it is possible to clamp the potential of the node F to the sufficiently small potential (see V _F of FIG. 1 (c)). At this time, the current limiting resistor 101 limits the current flowing through the diode 102 and the resistor 9, the operation to suppress an increase in the potential of the node F (see I _F of FIG. 1 (d)).

FIG. 4 is a circuit diagram of a protection device showing a second reference example of the present invention.

In this reference example, a parasitic MO is used as the first bypass element.
S-FET31 is used. The second bypass element is the diode 102 as in the previous example. That is, MOS ・ FET31
The gate and source are connected to operate as a diode, and the potential applied to input terminal 1 is applied to the gate to
Controls the current passing through the MOSFET 31. As described above, in the present embodiment, regardless of the type of the first bypass element, the destruction of the gate insulating film of the MIS • FET 5 is prevented by inserting the second bypass element 102 between the node 30 and the node 8. Can be prevented.

FIG. 5 is a circuit diagram of a protection device showing a third reference example of the present invention, and shows a case where the present invention is applied to input / output terminals for inputting or outputting data. 108
Is an output circuit section, 110 is an internal circuit section including an input circuit, 104 and 105 are MOS / FETs forming a push-pull circuit, and other symbols the same as those in FIG. 4 represent the same elements and components. 1 is an input terminal, 106 and 107 are MOS-FETs 104 and 105
And outputs data by charging / discharging an external capacitive load (not shown). MOS ・ FET5
This is a MOSFET for inputting data.

Here, when static electricity is applied to the terminal 1, the current is MOS
-Discharge through FET4 and further through node 6. In the first and second embodiments, it is possible to reduce the current flowing through the parasitic resistance 7 of the ground wiring by increasing the protection resistance 2.
Although it is possible to make the voltage applied to the gate oxide film of the MIS • FET 5 relatively small, in the case of the third reference example shown in FIG. 5, protection is required to ensure the TTL interface during data output. The resistance 2 cannot be added. In addition, during a normal circuit operation, a large current flows through the MOS-FET 104, so that noise is generated by the parasitic resistor 7, and this noise adversely affects the internal circuit. In order not to be affected by this, as shown in the figure, the output circuit unit 108 and the internal circuit unit 110 including the input circuit are arranged at a distance,
In addition, it is common to use ground wiring and power supply wiring. Under such circumstances, static electricity is applied to the input terminal 1 without applying this embodiment to the input / output pins.
, The voltage applied to the gate oxide film of the MIS • FET 5 increases. Therefore, for the input / output pins, the MIS-FET 5
Protection of the gate oxide film is further required than in the first and second embodiments.

FIG. 6 is a circuit diagram of a protection device showing a fourth reference example of the present invention.

In this reference example, MO is used as the second constant voltage clamp element.
S ・ FET110 is used. That is, the gate and the source of the MOS-FET are connected, and this is operated as a diode. Further, in the present embodiment, since the MOS-FET utilizing surface breakdown is used as the bypass element, the breakdown voltage is smaller than when a diode is used, and the voltage applied to the gate oxide film of the MIS-FET 5 is reduced. It is possible to make it smaller.

FIG. 7 is a circuit diagram of a protection device according to a fifth embodiment of the present invention.

In this reference example, the constant voltage clamp element is
This shows a case where it is provided on the power supply terminal side like ET34. In this case, when static electricity is applied to the input terminal 1, current flows not only to the parasitic resistance 7 on the ground wiring side but also to the parasitic resistance 35 on the power supply wiring side. At this time, a potential difference occurs and the node
The potential of 36 rises, and this rise in potential destroys the gate oxide film of the P-type MOSFET 31 having the power supply potential as the substrate potential. Therefore, as shown in FIG.
By inserting 1 between the gate electrode and the source electrode of the MOSFET 31 through the protection resistor 101, the voltage applied to the gate oxide film of the MOSFET 31 can be reduced, and the electrostatic breakdown voltage can be increased.

FIG. 8 is a circuit diagram of a protection device showing a sixth embodiment of the present invention.

In the reference example of FIG. 7, the input protection resistor 2 can be inserted. However, in the reference example of FIG. 8, as in the case of FIG. Cannot be used. Therefore, when the second constant voltage clamp element is not provided, the current flowing through the parasitic resistances 7 and 35 increases, and the voltage applied to the gate insulating films of the MOS FETs 32 and 5 increases. As shown in FIG. 8, if a protection resistor 101 and diodes 102 and 111 are inserted, a MOS
The voltage applied to the gate oxide films of the FETs 32 and 5 can be reduced.

FIG. 9 is a layout diagram of a protection circuit on a semiconductor substrate according to a seventh embodiment of the present invention.

A terminal 103 for supplying a ground potential and a terminal 108 for supplying a power supply voltage are arranged on the substrate. These terminals supply the power supply potential and the ground potential to the protection element and the internal circuit, respectively, as shown in FIG. ing. Here, protection element 3
4 and 4 and NMOS FETs 105 and 104 constituting the output buffer are 1
They are arranged in groups 112 in groups. Further, as the internal circuit, a circuit group formed in a region separate from the aggregate 112 is arranged. In this reference example, input terminal 1
When static electricity is applied to the NMOS, a large current flows through the NMOS-FETs 104 and 105, so by arranging the clamp element in the same region as the NMOS-FET of the output buffer, the given area can be used effectively. . In addition, since the protection resistor 101 is connected to the diodes 102 and 111 connected in front of the MOS FETs 5 and 31, only a small current flows and a small area is required. In the circuit region, the allowable area is often small, but in this embodiment, a protection element having a large electrostatic breakdown voltage can be manufactured while effectively using the small area. In the figure, reference numerals 7 and 9 denote parasitic resistances of ground wirings provided separately for the two clamp elements, and reference numerals 33 and 35 denote parasitic resistances of power supply wirings provided separately.

FIG. 10 is a sectional view on a semiconductor chip showing an example of a constant voltage clamp element according to the present invention.

In the figure, 113 is an n-type substrate, 114 is a p-type well, 115,
117 and 119 are n-type high-concentration impurity layers, 116 is a p-type high-concentration impurity layer, 118 is a conductive layer, and 118, 117 and 119 form a parasitic MOS • FET having a gate, a source and a drain, respectively. Normally, node 8 is fixed to the ground potential and node 32 is fixed to the power supply potential.

Now, when a potential is applied to the input terminal 112, the current is in the region 1
The current flows from 19 to 117.In addition, since the high-concentration impurity layer 119, the p-type well 114, and the base 113 form an npn bipolar structure, a current flows from the terminal 112 to the base 113 by a vertical bipolar operation. Flows from the region 115 to the terminal 32. Therefore, this element is connected not only to the terminal 112 but also to the terminal 3
2 also acts as a constant voltage clamp. A circuit using this element will be described with reference to FIG.

FIG. 11 is a circuit diagram of a protection device according to the first embodiment of the present invention, in which the elements shown in FIG. 10 are used as constant voltage clamp elements 120 and 121 for protecting gates. . With the structure shown in Fig. 10, MI
A constant voltage clamp element is formed between the source terminal 8 of the S-FET 5 and the source terminal 32 of the MIS-FET 31 so that the voltage applied to the parasitic resistances 7 and 35 is not applied to the gate insulating films of the MIS-FETs 5 and 31. . That is, regions 119 and 1 in FIG.
14 and 113 constitute the bipolar transistor 121 of FIG. 11, and the regions 119, 118 and 117 form the MOS / FE of FIG.
It composes T120.

FIG. 12 is a sectional view on a semiconductor chip showing a second embodiment of the present invention.

In FIG. 12, 210 is a semiconductor substrate, 211 is a first region of the first conductivity type, 228 is a second region of the first conductivity type, and 214 is a third region of the second conductivity type for constituting a constant voltage clamp element. region,
226 is a fourth region of the second conductivity type, and 203 is a current limiting resistor.

In this embodiment, the first conductivity type is p-type and the second conductivity type is
The conductivity type is n-type. As a first constant voltage clamp element, the regions 214, 223, and 222 are drain, gate,
Uses MOS-FET as source, p-type well 211
Formed within. The p-type well 211 is connected to the pad 208 for applying a ground potential through ohmic electrodes 213 and 216. A parasitic resistance 206 is inevitably present in the wiring during this time.

On the other hand, in the p-type well 228, there is an n-type layer 226,
228 and 226 form a pn junction and form a second constant voltage clamp element. Further, in the same well 228, a protected MOSFET having the regions 217, 218, and 219 as a drain, a gate, and a source, respectively, is formed. Note that p
224 and 221 in the mold wells 211 and 228 are gate oxide films of the MOS-FET. The p-well 228 is connected to the ground pad 208 through ohmic junctions 225, 227, 220. At this time, the parasitic resistance 207 necessarily exists in the ground wiring.

Reference numerals 209 and 203 denote current limiting resistors, respectively, which are made of a resistor such as polycrystalline silicon or a doped semiconductor or silicide.

Now, when static electricity is applied to the pad 201, the current becomes 209
→ 214 → 211 → 222 → 206 → 208
Flows to At this time, the potential difference between the regions 214 and 222 is kept almost constant because the constant voltage clamp element using the MOS-FET is used. However, the presence of the parasitic resistor 206 causes the current to flow therethrough, thereby increasing the potential at the point C. As a result, the potential at the point A changes to the gate oxide film 221.
Rise to an extent that cannot be protected. Therefore, an excessive voltage is not applied to the gate oxide film 221 by lowering the node voltage at the point B by clamping the voltage by the diode 226 provided in the separate well 228 via the second current limiting resistor 203. To do. At this time, the current limiting resistor
203 serves to limit the current flowing through the second constant voltage clamp element and reduce the voltage generated by the parasitic resistance inside the clamp element. If excessive noise is input to the input pin 201 during normal operation, the current due to the noise mainly flows through the region 214 due to the current limiting resistor 203, and is formed in the well 228. There is no malfunction of the internal circuit.

FIG. 13 is a circuit diagram and a plan layout diagram of a protection device according to a third embodiment of the present invention.

In FIG. 13, reference numeral 229 denotes a MOSFET which is a first constant voltage clamp element, 230 denotes a diode which is a second constant voltage clamp element, and 231 denotes a protected MOSFET. Dashed lines 232 and 23
The regions surrounded by 3 indicate that they are created in different regions in the semiconductor. Therefore, regions 232,23
3 is connected to a wiring for fixing each to a predetermined potential.
There are 207.

In the present embodiment, a diode 230 formed in the same region is provided to protect the gate oxide film of the MOSFET 231 in order to reduce the voltage generated in the parasitic resistance existing in the ground wiring of the ground resistor 207.

FIG. 14 is a sectional view on a semiconductor chip showing a fourth embodiment of the present invention.

In this embodiment, as the second constant voltage clamp element, a MOS FET having the regions 234, 235, and 237 as a drain, a gate, and a source, respectively, is used. This MOSFET corresponds to 238 in FIG. 14 (b). As a result, as in the embodiment of FIG. 12, the voltage generated in the parasitic resistor 206 is not directly applied to the protected MOS-FET, so that the protected MOS-FET can be protected from electrostatic breakdown. That is, when a MOSFET having a gate grounded is used as the second constant voltage clamp element as in the present embodiment, breakdown occurs at a lower voltage than when a diode is used. That is, since the clamp voltage is low, further effects can be expected.

FIG. 15 is a sectional view and a circuit diagram of a semiconductor chip showing an eighth embodiment of the present invention.

In the present embodiment, a diode 239 includes a p-type semiconductor region 231 and an n-type semiconductor region 229 as a second constant voltage clamp element.
Is formed by In this case, it is conceivable that the potential at the point B also increases due to the current flowing through the parasitic resistance 271 of the power supply connected to the well 231. However, since the current limiting resistance 203 exists, the first The current flowing through the constant voltage clamp element 232 is small, and the rise in the potential at the point B can be suppressed to a small value. At this time, most of the electric charge flowing into the terminal 201 passes through the MOSFET 229 and the ground terminal 208.
Is bypassed. Therefore, the voltage applied to the gate of the protected MOSFET 231 can be sufficiently reduced.

FIG. 16 is a sectional view and a circuit diagram on a semiconductor chip showing a ninth embodiment of the present invention.

This embodiment shows a case where a MOS FET is used instead of the diode of the second constant voltage clamp element in FIG. As a result, the clamp voltage can be lowered and the effect can be further improved. In FIG. 16 (a), a MOS-FET as a first constant voltage clamp device is formed in the regions 214, 223, 222 of the first well 211, and a second constant voltage clamp device is formed in the regions 234, 235, 236 of the second well 231. A certain MOSFET is formed, and regions 219 and 2 of the third well 212 are formed.
A protected MOSFET is formed at 18,217.

FIG. 17 is a sectional view and a circuit diagram on a semiconductor chip showing a fifth embodiment of the present invention.

The protected element is an nMOS-FET and pMOS-FET
It shows the case of FET. In FIG.
PMOS • FET of a CMOS circuit, 229 and 256 are nMOS • FETs that are constant voltage clamp elements, 242 is a power supply terminal, 243 and 244 are parasitic resistances parasitic to the power supply terminal, and 238 is an nMOS • FET that is a second constant voltage clamp element. . In FIG. 7A, reference numerals 245 and 252 denote gate electrodes of MOS FETs 256 and 257, 246 and 253 denote gate oxide films of MOS FETs 256 and 257, 247, 249 and 250 denote n-type impurity regions, and 248, 251 and 254 denote n-type impurity regions. 201 is an input terminal, 208 is a power supply terminal, and 242 is a ground terminal. In this embodiment, the nMOS • FET2 shown in FIG.
The region 258 where the 58 is formed and the region 259 where the nMOS • FET 259 are formed are formed in different regions. As the first constant voltage clamp element, MOS ・ FET on the ground potential side
229, and a MOSFET 256 in the order of the power supply potential.
On the other hand, a larger parasitic capacitance exists between the power supply terminal 242 and the ground terminal 208 due to a circuit in the chip. Therefore, for high-speed phenomena such as when static electricity is applied,
242 and the terminal 208 are equivalent to the conductive state. Therefore, when static electricity is applied to the input terminal 201, the current
Since both 29 and 256 flow and a potential difference is generated between the parasitic resistances 206 and 243, this potential is applied to the gate oxide films of the MOSFETs 257 and 231. By lowering the voltage, the gate oxide films of the MOSFETs 257 and 231 are protected from destruction.

FIG. 18 is a sectional view on a semiconductor chip and a circuit diagram showing a sixth embodiment of the present invention.

In this embodiment, the protection element is used for a data input / output terminal of a CMOS circuit. In FIG. (B), 268,269
Is an nMOS / FET for outputting data to the input / output terminal 201
And outputs data according to output signals applied to the input terminals 266 and 267. On the other hand, pMOS-FET257 and nMOS-
The circuit including the FET 259 is a circuit for inputting a signal given to the terminal 201. A signal is input from terminal 255. In FIG. 7A, regions 214, 259, and 261 are the drain, gate, and source of the MOSFET 269, and regions 265, 263, and 262
Are the drain, gate and source of the MOSFET 268. In the case of a terminal that outputs data as in this embodiment, it is very difficult to use the current limiting resistor 209 at the input as in the above-described embodiment in order to secure an input / output interface. Therefore, when static electricity is applied to the terminal 201, a very large current flows through the parasitic resistances 206 and 243 through the MOSFETs 268, 269, 256, and 229. Therefore, the potential rise at the power supply terminal 242 and the ground terminal 208 is also large. Therefore, in this embodiment, the current limiting resistor 203
By providing the MOS-FET 238 as the second constant voltage clamp element, a large voltage is prevented from being applied to the gate insulating films of the MOS-FETs 257 and 231.

FIG. 19 is a diagram of an electrostatic breakdown test result showing the seventh embodiment of the present invention.

FIG. 7A shows the test method. First, the chip is charged through a 100 MΩ resistor to the device.
This charging is performed in the stray capacitance between the chip and the ground. The value of this stray capacitance is usually in the range of 1 to 10 pF. The charged device is discharged from the test pin by closing the switch. This test method is usually called the charged device method,
Although the energy of static electricity is small due to small capacity, there is no resistance at the time of discharging, so that a large current flows at the moment when the switch is closed. Therefore, in the present invention, the effect of the charged device method is particularly remarkable.

FIG. 6B shows the result of applying the present embodiment to the data input / output pins. The first current limiting resistor is not particularly connected to these protection elements, but only has a parasitic resistance. Here, the data of the pins 1, 2, and 4 are data when the present invention is not applied, that is, when there is no second constant voltage clamp element.
Pins indicate cases where the present invention is applied. Also, a pin location close to the terminal V _SS applying the ground potential as the pin number is small. In the figure (b), the pin number
With respect to the pin of 1,2,4, the following voltage gate insulating film 2000V and is broken, and, farther from the V _SS terminal, shows weak. The pin No. 3 to which the present invention was applied was not broken at 3000 V, indicating the effectiveness of the present invention.

In the embodiments described above, the inserted current limiting resistor 9 is not always an indispensable requirement. If the resistor is not provided, the effect of the present invention is remarkable.

As described above, in each embodiment of the present invention, when static electricity is applied to the input pin of the integrated circuit, the static electricity is bypassed by the first constant voltage clamp element, and the static electricity is connected to the first constant voltage clamp element. The potential difference generated in the parasitic resistance inevitably in the power supply wiring can be reduced by the second constant voltage clamp element. Therefore, if the parasitic resistance of the power supply wiring is large, and if a current limiting resistor cannot be inserted between the first constant voltage clamp element and the input pin due to the circuit operation, the potential difference generated in the parasitic resistance increases. According to the invention, the influence can be prevented. According to the present invention, in particular, in the case of a data input / output pin into which a current limiting resistor cannot be inserted, electrostatic breakdown can be prevented with respect to static electricity having a voltage twice or more as compared with the conventional method.

〔The invention's effect〕

As described above, according to the present invention, even when there is no current limiting resistor to be connected to the input terminal, the electrostatic breakdown voltage can be sufficiently increased. It is possible to protect.

[Brief description of the drawings]

FIG. 1 is a circuit diagram, layout diagram and internal characteristic diagram of a protection element on a semiconductor chip showing a first reference example of the present invention, and FIG. FIG. 3 is a circuit diagram, a chip layout diagram and an internal voltage characteristic diagram for comparing the related art with the related art, and FIG. 4 is a protection on a semiconductor chip showing a second embodiment of the present invention. FIG. 5 is a circuit diagram showing a third embodiment of the present invention, FIG. 6 is a circuit diagram showing a fourth embodiment, and FIG. 7 is a fifth embodiment of the present invention. FIG. 8 is a circuit diagram showing a sixth embodiment of the present invention, FIG. 9 is a layout diagram on a semiconductor chip showing a seventh embodiment of the present invention, FIG.
FIG. 11 is a cross-sectional view of a protection element on a semiconductor chip showing the present invention. FIG. 11 shows a first embodiment of the present invention, a circuit diagram showing an application of FIG. 10, and FIG. FIG. 13 is a circuit layout diagram and a layout diagram showing a third embodiment of the present invention, and FIG. 14 is a cross-sectional view showing a fourth embodiment of the present invention. FIG. 15 is a sectional view and a circuit arrangement diagram showing an eighth embodiment of the present invention, and FIG. 16 is a sectional view and a circuit arrangement diagram showing a ninth embodiment of the present invention. 17 is a sectional view and a circuit arrangement diagram showing a fifth embodiment of the present invention, FIG. 18 is a sectional view and a circuit arrangement diagram showing a sixth embodiment of the present invention, and FIG. It is an explanatory view of the result of the electrostatic breakdown test showing the 7th example. 1,201: input terminal, 2,101,209: protection resistor, 4: MO for bypass
S ・ FET, 7,9,33,35,206,207,271,243,244: Parasitic resistance parasitic to ground wiring and power supply wiring, 5,231,257: Protected MOS
-FET, 102, 123: bypass diode, 31: parasitic MOS-FET for bypass, 211: first region, 228, 231: second region, 214:
Third area, 226,234,229: fourth area.

Continuing on the front page (72) Inventor Toshio Sasaki 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-57-12547 (JP, A) JP-A-62-65360 (JP, A) JP-A-62-30361 (JP, A)

Claims (2)

(57) [Claims] A first constant voltage clamp element connected to the input terminal; a current limiting resistor having one end connected to the input terminal; and a second constant voltage connected to the other end of the current control resistor. A semiconductor integrated circuit device including a clamp element and a protected element protected by the second constant voltage clamp element, wherein the semiconductor integrated circuit device includes a semiconductor substrate containing a predetermined impurity and a semiconductor substrate including a predetermined impurity. A first conductivity type formed separately from each other by introducing an impurity into the semiconductor substrate, the first constant voltage clamp element including a first region and a second region different from the semiconductor substrate; And at least a portion thereof is formed by a third region of the second conductivity type formed in the first region.
The constant voltage clamp element and the protected element are
And at least a portion of the second constant voltage clamp element is formed by a fourth region of the second conductivity type formed in the second region, and the first and second constant voltage clamp elements are formed in the second region. Wherein each of the constant voltage clamp elements is connected to a ground potential wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein said first region and said second region are connected to a predetermined operating potential via first and second ohmic contact means, respectively. A semiconductor integrated circuit device.