JPH01120040A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH01120040A JPH01120040A JP62277715A JP27771587A JPH01120040A JP H01120040 A JPH01120040 A JP H01120040A JP 62277715 A JP62277715 A JP 62277715A JP 27771587 A JP27771587 A JP 27771587A JP H01120040 A JPH01120040 A JP H01120040A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- bump
- layer
- electrode
- aluminum electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 29
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000000470 constituent Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- QGVYLCICHZYPJA-UHFFFAOYSA-N [Cr].[Cu].[Au] Chemical compound [Cr].[Cu].[Au] QGVYLCICHZYPJA-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- JUWSSMXCCAMYGX-UHFFFAOYSA-N gold platinum Chemical compound [Pt].[Au] JUWSSMXCCAMYGX-UHFFFAOYSA-N 0.000 description 1
- FHUGMWWUMCDXBC-UHFFFAOYSA-N gold platinum titanium Chemical compound [Ti][Pt][Au] FHUGMWWUMCDXBC-UHFFFAOYSA-N 0.000 description 1
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000003923 scrap metal Substances 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
Landscapes
- Heating, Cooling, Or Curing Plastics Or The Like In General (AREA)
- Testing Of Balance (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
本発明は、半導体装置に於けるバンプ電極構造に関する
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bump electrode structure in a semiconductor device.
従来の半導体装置に於ける一般的なバンプ電極構造は、
バンプ電極層をアルミニウム電極の上面中央部且つ前記
第２の絶縁膜上に延在して設けられている為、該アルミ
ニウム電極中央部と該アルミニウム電極の上面周辺部上
に設けられた該第２の絶縁膜との段差が、該バンプ電極
層にパターニングされ、該バンプ電極層上面が凹状の構
造となっている。The general bump electrode structure in conventional semiconductor devices is
Since the bump electrode layer is provided extending over the central portion of the upper surface of the aluminum electrode and the second insulating film, the bump electrode layer is provided extending over the central portion of the upper surface of the aluminum electrode and the peripheral portion of the upper surface of the aluminum electrode. The bump electrode layer is patterned to have a step with the insulating film, and the upper surface of the bump electrode layer has a concave structure.
従来のバンプ電極構造に於ては、上部が凹構造となって
いる為、バンプ実装に於て、対向する基板側のボンディ
ング用フィンガーが、バンプ電極層上面の外周周辺部に
接触する構造となり、バンプｆ！！１極とフィンガーと
の接触面積が低下することによる密着性不良の問題があ
る。又、実装時のフィンガーからの熱及び圧力のストレ
スが、バンプ電価外周部に極部的に集中する為、パフ１
ｗｉ極下の、構成材料の破壊をもたらすといった問題が
ある。In the conventional bump electrode structure, the upper part has a concave structure, so during bump mounting, the bonding fingers on the opposing substrate side come into contact with the outer periphery of the top surface of the bump electrode layer. Bump f! ! There is a problem of poor adhesion due to a decrease in the contact area between one pole and the finger. In addition, the heat and pressure stress from the fingers during mounting is concentrated locally on the outer periphery of the bump, so the puff 1
However, there is a problem in that it leads to destruction of the constituent materials.
本発明は、この様な問題点を解決するもので、その目的
とするところは、従来のバンプｆｆｌ極構造に於けるバ
ンプ、電極層下の絶縁膜等による段着を、バンプ電極領
域の外側に設け、バンプｆｆｌ極上面の平坦化構造をと
ることにより、実装時のバンプ電極とフィンガーとの接
触面積を増やし密行強度の大幅な向上を提０（するとと
もに、実装時のバンプへの熱及び圧力ストレスが均一と
なる構造による。バンプ下構成材料の破壊防止を提供す
ることにある。The present invention is intended to solve these problems, and its purpose is to replace the bumps and insulating films under the electrode layers in the conventional bump ffl pole structure with the steps outside the bump electrode area. By adopting a flattened structure on the top surface of the bump ffl, the contact area between the bump electrode and the finger during mounting is increased, and the close contact strength is significantly improved. and a structure in which the pressure stress is uniform.The purpose is to prevent destruction of the constituent material under the bump.
本発明の半導体装置は、半導体基板上に設けられた第１
の絶縁膜と該第１の絶縁股上に設けられたアルミニウム
電極ｉ極と、該第１の絶縁膜上より該アルミニウム電極
の上面周辺部上に延在して設けられた第２の絶縁膜と、
該アルミニウム電極の上面中央部に設けられた第１の金
属膜層と、該第１の金屑膜層上のバンブ電極層とを有す
ることを特徴とする半導体装置。The semiconductor device of the present invention includes a first semiconductor device provided on a semiconductor substrate.
an insulating film, an aluminum electrode i-pole provided on the first insulating crotch, and a second insulating film extending from above the first insulating film onto a peripheral portion of the upper surface of the aluminum electrode. ,
A semiconductor device comprising: a first metal film layer provided at the center of the upper surface of the aluminum electrode; and a bump electrode layer on the first scrap metal film layer.
（２） 半導体基板上に設けられた第１の絶縁膜と該第
１の絶縁股上に設けられたアルミニウム電極と、該第１
の絶縁股上より該アルミニウム電極の上面周辺部に延在
して設けられた第２の絶縁膜と、該アルミニウム電極の
上面中央部且つ該第２の絶縁股上に延在して設けられた
第１の金屑膜層と、該第１の金屑膜層及び該アルミニウ
ム電極が接触している領域の内側且つ該第１の金属膜層
上のバンブ？ｌ！極層とを育することを特徴とする。(2) a first insulating film provided on a semiconductor substrate; an aluminum electrode provided on the first insulating crotch;
a second insulating film extending from the insulating crotch to the periphery of the upper surface of the aluminum electrode, and a first insulating film extending from the center of the upper surface of the aluminum electrode to the second insulating crotch. A bump on the first metal film layer and inside a region where the first scrap gold film layer and the aluminum electrode are in contact with each other. l! It is characterized by growing the polar layer.
以下、本発明について、実施例に基づき詳細に説明する
。Hereinafter, the present invention will be described in detail based on examples.
第１図は、アルミニウム電極２上中央部に例えばチタン
−白金−金等の金Ｒｍｍ４を形成し、更に金層膜層４上
にバンプ電極届５を設けた一実施例である。FIG. 1 shows an embodiment in which gold Rmm4, such as titanium-platinum-gold, is formed on the central part of the aluminum electrode 2, and a bump electrode 5 is further provided on the gold film layer 4.
第２図は、アルミニウム電極２上中央部且つ絶縁ｖ！：
３上に延在して金層膜層４を設け、バンプ電価５を、ア
ルミニウム電極２と金屑膜層４の接触領域より内側に設
けた一実施例である。FIG. 2 shows the upper center part of the aluminum electrode 2 and the insulation v! :
This is an embodiment in which a gold film layer 4 is provided extending over the aluminum electrode 2 and the bump voltage 5 is provided inside the contact area between the aluminum electrode 2 and the gold scrap film layer 4.
第１図、第２図ともに、アルミニウム電極２の上面周辺
部に設けられた絶縁膜３の領域より内側の平坦領域上に
バンプ電価５を設けることを特徴とする。Both FIG. 1 and FIG. 2 are characterized in that the bump voltage 5 is provided on a flat region inside the region of the insulating film 3 provided around the upper surface of the aluminum electrode 2.
第３図は、本発明のバンプ電極構造に於ける実装伏囮を
示した実施例である。FIG. 3 is an embodiment showing a mounting cover in the bump electrode structure of the present invention.
第４図は、従来のバンブＴ１極構造を示す。FIG. 4 shows a conventional bump T1 pole structure.
第５図は、従来のバンプ電極構造於ける実装状態を示す
。FIG. 5 shows a mounting state of a conventional bump electrode structure.
上述の如く、本発明によれば、バンプ電価上面の平坦化
構造をとることができ、実装時のバンプ電価と実装フィ
ンガーとの接触面積増加による密着強度の大幅な向上を
もたらすとともに、実装時の熱及び圧力ストレスに対す
るバンプ下構成材料の破壊防止をもたらすものである。As described above, according to the present invention, it is possible to have a structure in which the upper surface of the bump voltage is flattened, which significantly improves the adhesion strength by increasing the contact area between the bump voltage and the mounting finger during mounting, and also improves the bonding strength during mounting. This prevents the constituent material under the bump from being destroyed by the heat and pressure stress caused by the bump.
第１図、第２図は、本発明の半導体装置であるバンプ電
極構造断面図。
第３図は、本発明のバンプ電極構造の半導体装置を実装
した時の構造断面図。
第４図は、従来のバンプ電極構造断面図。
第５図は、従来のバンプ電極構造の半導体装置を実装し
た時の構造断面図。
１・・・５ｉＯｚ、ＳｉＮ等の絶縁膜。
２・・・アルミニウム電極。
３・・・Ｓ １０ ｔ 、Ｓ ｉＮ等の絶縁膜。
４・・・チクノー白金−金、クロム−銅−金、チタン−
パラジウム−金等の金層膜層。
５・・・バンプ電価。
６・・・実装基板側のポンデイン用フィンガー。
以 上
填１０ 寛２０
第３図
第４図 第５図FIGS. 1 and 2 are cross-sectional views of bump electrode structures of the semiconductor device of the present invention. FIG. 3 is a cross-sectional view of the structure when the semiconductor device having the bump electrode structure of the present invention is mounted. FIG. 4 is a sectional view of a conventional bump electrode structure. FIG. 5 is a structural sectional view when a semiconductor device with a conventional bump electrode structure is mounted. Insulating film of 1...5iOz, SiN, etc. 2...Aluminum electrode. 3... Insulating film such as S 10 t or SiN. 4...Chikuno platinum-gold, chromium-copper-gold, titanium-
Gold layer film layer such as palladium-gold. 5...Bump electric value. 6...Pondein finger on the mounting board side. That's all for now. 10 Kan 20 Figure 3 Figure 4 Figure 5
Claims (2)
の絶縁膜上に設けられたアルミニウム電極と、該第１の
絶縁膜上より該アルミニウム電極の上面周辺部上に延在
して設けられた第２の絶縁膜と、該アルミニウム電極の
上面中央部に設けられた第１の金属膜層と、該第１の金
属膜層上のバンプ電極層とを有することを特徴とする半
導体装置。(1) A first insulating film provided on a semiconductor substrate and a first insulating film provided on a semiconductor substrate;
an aluminum electrode provided on an insulating film; a second insulating film provided extending from above the first insulating film onto a peripheral portion of the upper surface of the aluminum electrode; and a central portion of the upper surface of the aluminum electrode. 1. A semiconductor device comprising: a first metal film layer provided on a semiconductor device; and a bump electrode layer on the first metal film layer.
の絶縁膜上に設けられたアルミニウム電極と、該第１の
絶縁膜上より該アルミニウム電極の上面周辺部上に延在
して設けられた第２の絶縁膜と、該アルミニウム電極の
上面中央部且つ該第２の絶縁膜上に延在して設けられた
第１の金属膜層と、該第１の金属膜層及び該アルミニウ
ム電極が接触している領域の内側且つ該第１の金属膜層
上のバンプ電極層とを有することを特徴とする半導体装
置。(2) a first insulating film provided on a semiconductor substrate;
an aluminum electrode provided on an insulating film; a second insulating film provided extending from above the first insulating film onto a peripheral portion of the upper surface of the aluminum electrode; and a central portion of the upper surface of the aluminum electrode. and a first metal film layer provided extending over the second insulating film, inside a region where the first metal film layer and the aluminum electrode are in contact with the first metal film; 1. A semiconductor device comprising a bump electrode layer on top of the bump electrode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62277715A JPH01120040A (en) | 1987-11-02 | 1987-11-02 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62277715A JPH01120040A (en) | 1987-11-02 | 1987-11-02 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01120040A true JPH01120040A (en) | 1989-05-12 |
Family
ID=17587309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62277715A Pending JPH01120040A (en) | 1987-11-02 | 1987-11-02 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01120040A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
| US6525422B1 (en) * | 1997-01-20 | 2003-02-25 | Sharp Kabushiki Kaisha | Semiconductor device including bump electrodes |
| US6940166B2 (en) | 2003-01-22 | 2005-09-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for designing the same |
| US7446399B1 (en) | 2004-08-04 | 2008-11-04 | Altera Corporation | Pad structures to improve board-level reliability of solder-on-pad BGA structures |
-
1987
- 1987-11-02 JP JP62277715A patent/JPH01120040A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6525422B1 (en) * | 1997-01-20 | 2003-02-25 | Sharp Kabushiki Kaisha | Semiconductor device including bump electrodes |
| US6933607B2 (en) | 1997-01-20 | 2005-08-23 | Sharp Kabushiki Kaisha | Semiconductor device with bumps on electrode pads oriented in given direction |
| US7005741B2 (en) | 1997-01-20 | 2006-02-28 | Sharp Kabushiki Kaisha | Liquid crystal display device and/or circuit substrate including bump electrodes and electrode pads |
| US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
| US6929978B2 (en) | 1999-03-05 | 2005-08-16 | Altera Corporation | Method of fabricating an integrated circuit package utilizing a conductive structure for improving the bond strength between an IC package and a printed circuit board |
| US6940166B2 (en) | 2003-01-22 | 2005-09-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for designing the same |
| US7446399B1 (en) | 2004-08-04 | 2008-11-04 | Altera Corporation | Pad structures to improve board-level reliability of solder-on-pad BGA structures |
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