JPH01117344A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH01117344A JPH01117344A JP62275517A JP27551787A JPH01117344A JP H01117344 A JPH01117344 A JP H01117344A JP 62275517 A JP62275517 A JP 62275517A JP 27551787 A JP27551787 A JP 27551787A JP H01117344 A JPH01117344 A JP H01117344A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- aluminum
- electrode
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052782 aluminium Inorganic materials 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 239000000463 material Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に於ける、バット電極構造及びバ
ンプ電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a butt electrode structure and a bump electrode structure in a semiconductor device.
従来の半導体装置に於ける一般的なパッド電極構造及び
バンプ電極構造は、アルミニウム電極下に、ｓｉＯ＊の
材質的に脆い絶縁膜を設けた構造をとっている。The general pad electrode structure and bump electrode structure in conventional semiconductor devices have a structure in which an insulating film of SiO*, which is a fragile material, is provided under an aluminum electrode.
従って、従来のパッド電極及びバンプ電極構造は於ては
、実装時に熱及び圧力ストレスによりバブト電極下の絶
縁膜に微小クラックが生じ、これが電気的特性不良をも
たらすといった、品質上重大な問題がある。Therefore, in the conventional pad electrode and bump electrode structure, micro-cracks occur in the insulating film under the bump electrode due to heat and pressure stress during mounting, which leads to poor electrical characteristics, which is a serious quality problem. .
本発明は、この様な問題点を解決するもので、その目的
とするところは、従来のパッド電極及びバンプ電極に於
ける、アルミニウム電極下の絶縁膜の下に例えばアルミ
ニウム金属等の材質的に軟らかい膜を設けることにより
、実装時のストレスを吸収させ、絶縁膜等のクラック防
止を提供することにある。The present invention is intended to solve these problems, and its purpose is to provide a material such as aluminum metal under the insulating film under the aluminum electrode in conventional pad electrodes and bump electrodes. By providing a soft film, the stress during mounting can be absorbed and cracks in the insulating film can be prevented.
本発明の半導体装置は、
（１） 半導体基板上に設けられた第１の絶縁膜と、該
第１の絶縁膜上に設けられた、例えばアルミニウム膜等
から成る第１の島状膜と該第１の絶縁膜上且つ該第１の
島状膜上に延在して設けられた第２の絶縁膜と、該第２
の絶縁股上に設けられたアルミニウム電極と、該アルミ
ニウム電極の上面周辺部より該第２の絶縁膜上に延在し
て設けられた第３の絶縁膜とを、有することを特徴とす
る。The semiconductor device of the present invention includes: (1) a first insulating film provided on a semiconductor substrate; a first island-like film made of, for example, an aluminum film, provided on the first insulating film; a second insulating film provided extending over the first insulating film and the first island-like film;
It is characterized by having an aluminum electrode provided on the insulating crotch of the aluminum electrode, and a third insulating film provided extending from the upper surface periphery of the aluminum electrode onto the second insulating film.
（２） 半導体基板上に設けられた第１の絶縁膜と、該
第１の絶縁膜上に設けられた、例えばアルミニウム膜等
から成る第１の島状膜と該第１の絶縁膜上且つ該第１の
島状膜上に延在して設けられた第２の絶縁膜と、該ｉ２
の絶縁膜上に設けられたアルミニウム電極と、該アルミ
ニウム電極の上面周辺部より該第２の絶縁膜上に延在し
て設けられた第３の絶縁膜と、該アルミニウム電極上面
中央部より該第３の絶縁膜上に延在して設けられた第２
の金＠膜層と、該第２の金ｒＡ膜層上に設けられた、バ
ンプ電ＩＭ Ｆ３とを存することを特徴とする。(2) a first insulating film provided on a semiconductor substrate; a first island-shaped film made of, for example, an aluminum film provided on the first insulating film; and a first insulating film provided on the first insulating film; a second insulating film extending and provided on the first island-like film, and the i2
an aluminum electrode provided on the insulating film; a third insulating film provided extending from the upper surface peripheral portion of the aluminum electrode onto the second insulating film; The second insulating film is provided extending over the third insulating film.
and a bump electrode IMF3 provided on the second gold rA film layer.
以下、本発明について、実施例に基づき詳細に説明する
。Hereinafter, the present invention will be described in detail based on examples.
第１図は、アルミニウム電ｗＡ４下の、絶縁膜２及び絶
縁膜１の間に、例えばアルミニウム膜やポリイミド膜等
を島状に設けた、パッド電極構造の一実施例である。FIG. 1 shows an example of a pad electrode structure in which, for example, an aluminum film, a polyimide film, or the like is provided in an island shape between an insulating film 2 and an insulating film 1 under an aluminum electrode wA4.
第２図は、第１図に於ける内容を、バンプ電極構造に適
用した実施例である。FIG. 2 shows an example in which the contents of FIG. 1 are applied to a bump electrode structure.
第３図は、従来のパッド電極構造を示す。FIG. 3 shows a conventional pad electrode structure.
第４図は、従来のバンプｆｌｔ 極構造を示す。FIG. 4 shows a conventional bump flt pole structure.
第５図は、従来のパッド電極構造に於ける実装状態を示
す。FIG. 5 shows a mounting state of a conventional pad electrode structure.
上述の如く、本発明によれば、アルミニウム電極下の絶
縁膜の下に、実装時Ｑ熱及び圧力ストレスの吸収、緩和
材料を設けることで、実装工程に於ける、アルミニウム
電極下の絶縁膜等のクラック発生による品質トラブルの
防止をもたらすものである。As described above, according to the present invention, by providing a material for absorbing and relieving Q heat and pressure stress during mounting under the insulating film under the aluminum electrode, the insulating film, etc. under the aluminum electrode during the mounting process is provided. This prevents quality problems caused by cracks.
第１図は、本発明の半導体装置であるパッド電極断面図
。
第２図は、本発明の半導体装置であるバンプ電極断面図
。
第３図は、従来の半導体装置であるパッド電極断面図。
ｍ４図は、従来の半導体装置であるバンプ電極断面図。
第５図は、従来の半導体装置であるパッド１！極のボン
ディング後の断面図。
１．２、ｄ−・ＳｉＯｘ、ＳｒＮ系絶縁膜。
４・・・アルミニウム電極。
５・・・アルミニウム、ポリイミド等の島状膜。
６゛・・・バンプ下金層。
７・・・バンプ電極。
８・・・実装用ボンディングワイヤー
以 上
第１図
Ｉｎ３図
７八レアｔ９
′！２図
第４図FIG. 1 is a sectional view of a pad electrode that is a semiconductor device of the present invention. FIG. 2 is a sectional view of a bump electrode that is a semiconductor device of the present invention. FIG. 3 is a sectional view of a pad electrode in a conventional semiconductor device. Figure m4 is a cross-sectional view of a bump electrode of a conventional semiconductor device. FIG. 5 shows pad 1! of a conventional semiconductor device. Cross-sectional view of the pole after bonding. 1.2, d-SiOx, SrN-based insulating film. 4...Aluminum electrode. 5... Island-shaped film made of aluminum, polyimide, etc. 6゛...Bump lower gold layer. 7...Bump electrode. 8...Mounting bonding wire or more Figure 1 In 3 Figure 7 8 Rare t9'! Figure 2 Figure 4
Claims (2)
の絶縁膜上に設けられた例えばアルミニウム膜等から成
る第１の島状膜と、該第１の絶縁膜上且つ該第１の島状
膜上に延在して設けられた第２の絶縁膜と、該第２の絶
縁膜上に設けられたアルミニウム電極と、該アルミニウ
ム電極の上面周辺部より該第２の絶縁膜上に延在して設
けられた第３の絶縁膜とを有することを特徴とする半導
体装置。(1) A first insulating film provided on a semiconductor substrate and a first insulating film provided on a semiconductor substrate;
a first island-like film made of, for example, an aluminum film, provided on the insulating film; and a second insulating film provided on the first insulating film and extending over the first island-like film. an aluminum electrode provided on the second insulating film; and a third insulating film provided extending from a peripheral portion of the upper surface of the aluminum electrode onto the second insulating film. A semiconductor device characterized by:
１の絶縁膜上に設けられた、例えばアルミニウム膜等か
ら成る第１の島状膜と該第１の絶縁膜上且つ該第１の島
状膜上に延在して設けられた第２の絶縁膜と、該第２の
絶縁膜上に設けられたアルミニウム電極と、該アルミニ
ウム電極の上面周辺部より該第２の絶縁膜上に延在して
設けられた第３の絶縁膜と、該アルミニウム電極上面中
央部より該第３の絶縁膜上に延在して設けられた第２の
金属膜層と、該第２の金属膜層上に設けられたバンプ電
極層とを有することを特徴とする半導体装置。(2) a first insulating film provided on a semiconductor substrate; a first island-shaped film made of, for example, an aluminum film provided on the first insulating film; and a first insulating film provided on the first insulating film; a second insulating film provided extending over the first island-like film; an aluminum electrode provided on the second insulating film; a third insulating film extending over the insulating film; a second metal film layer extending over the third insulating film from the center of the upper surface of the aluminum electrode; 1. A semiconductor device comprising: a bump electrode layer provided on a second metal film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62275517A JPH01117344A (en) | 1987-10-30 | 1987-10-30 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62275517A JPH01117344A (en) | 1987-10-30 | 1987-10-30 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01117344A true JPH01117344A (en) | 1989-05-10 |
Family
ID=17556570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62275517A Pending JPH01117344A (en) | 1987-10-30 | 1987-10-30 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01117344A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH031538A (en) * | 1989-05-29 | 1991-01-08 | Sony Corp | Semiconductor device |
| KR100336769B1 (en) * | 1999-11-04 | 2002-05-16 | 박종섭 | Chip size package and the manufacturing method |
| JP2003031579A (en) * | 2001-07-18 | 2003-01-31 | Denso Corp | Sensor and manufacturing method therefor |
| JP2005347672A (en) * | 2004-06-07 | 2005-12-15 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
-
1987
- 1987-10-30 JP JP62275517A patent/JPH01117344A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH031538A (en) * | 1989-05-29 | 1991-01-08 | Sony Corp | Semiconductor device |
| KR100336769B1 (en) * | 1999-11-04 | 2002-05-16 | 박종섭 | Chip size package and the manufacturing method |
| JP2003031579A (en) * | 2001-07-18 | 2003-01-31 | Denso Corp | Sensor and manufacturing method therefor |
| JP2005347672A (en) * | 2004-06-07 | 2005-12-15 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
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