JPH01115163A - Vertical MOS field effect transistor - Google Patents
Vertical MOS field effect transistorInfo
- Publication number
- JPH01115163A JPH01115163A JP62272506A JP27250687A JPH01115163A JP H01115163 A JPH01115163 A JP H01115163A JP 62272506 A JP62272506 A JP 62272506A JP 27250687 A JP27250687 A JP 27250687A JP H01115163 A JPH01115163 A JP H01115163A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- vertical
- effect transistor
- field effect
- mos field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000005684 electric field Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 4
- 239000012808 vapor phase Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/118—Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、主に電力用スイッチング素子として応用され
る。高信頼性の縦型絶縁ゲート電界効果トランジスタ（
以下、縦型ＭＯ８ＦＥＴと記す）に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is mainly applied as a power switching element. Highly reliable vertical insulated gate field effect transistor (
The present invention relates to a vertical MO8FET (hereinafter referred to as a vertical MO8FET).
従来の技術
縦型ＭＯ８ＦＥＴは、近年特に電力用素子を中心として
急速に利用されつつある。従来の縦型ＭＯ８ＦＥＴのチ
ップ周辺部分は、第３図に示すような断面構造であり、
図示する縦型ＭＯＳＦＥＴがＮチャンネル形であるもの
として以下に詳しく説明する。BACKGROUND OF THE INVENTION Vertical MO8FETs are rapidly being used in recent years, particularly in power devices. The chip peripheral area of a conventional vertical MO8FET has a cross-sectional structure as shown in Figure 3.
A detailed description will be given below assuming that the illustrated vertical MOSFET is an N-channel type.
この縦型Ｍ ＯＳ Ｆ Ｅ Ｔは、ドレイン領域１を形
成する低濃度Ｎ型シリコン半導体基板中の少なくとも三
部分に分離されてチャンネル領域形成用のＰ型拡散領域
２が形成され、このＰ型拡散領域の中にＮ型ソース領域
３が形成されるとともにドレイン領域１をはさんで相対
するソース領域３間のシリコン基板表面にゲート酸化膜
４が形成され、このゲート酸化膜４上にゲート電極５が
形成されている。さらに、ゲート電極５と化学的に気相
成長させた層間絶縁膜６を介して、またソース領域３お
よびＰ型拡散領域２にまたがってソース電極７が形成さ
れた構造となっている。This vertical MOS FET is separated into at least three parts in a low concentration N-type silicon semiconductor substrate forming a drain region 1, and a P-type diffusion region 2 for forming a channel region is formed. An N-type source region 3 is formed in the region, and a gate oxide film 4 is formed on the surface of the silicon substrate between the source regions 3 facing each other with the drain region 1 in between. is formed. Further, a source electrode 7 is formed across the gate electrode 5 and the source region 3 and the P-type diffusion region 2 via an interlayer insulating film 6 which is chemically grown in a vapor phase.
この構造の縦型ＭＯ８ＦＥＴでは、Ｐ型拡散領域２とゲ
ート酸化膜４との界面にチャンネルができ、電子はソー
ス領域３からこのチャンネルを通ってドレイン領域１の
表面部に達し、ここから裏面に設けたドレイン電極８に
向かって流れる。７また、チップ周辺部の構造は、ドレ
イン領域１の上に熱酸化によって形成された酸化膜９が
あり、更にその上に層間絶縁膜６を形成した時に同時に
形成される化学的気相成長による酸化膜１０が付着形成
された構造となっている。つまり、従来の縦型ＭＯＳＦ
ＥＴのチップ周辺部は、ドレインの低濃度Ｎ型シリコン
半導体基板上に熱酸化により形成された、酸化膜と化学
的な気相成長により形成された酸化膜の二層構造になっ
ているわけである。In the vertical MO8FET with this structure, a channel is formed at the interface between the P-type diffusion region 2 and the gate oxide film 4, and electrons pass from the source region 3 through this channel to the front surface of the drain region 1, and from there to the back surface. It flows toward the provided drain electrode 8. 7 In addition, the structure of the chip periphery is such that there is an oxide film 9 formed by thermal oxidation on the drain region 1, and an oxide film 9 is formed by chemical vapor deposition at the same time as the interlayer insulating film 6 is formed on top of the oxide film 9. It has a structure in which an oxide film 10 is deposited. In other words, conventional vertical MOSF
The periphery of the ET chip has a two-layer structure: an oxide film formed by thermal oxidation on the low concentration N-type silicon semiconductor substrate of the drain, and an oxide film formed by chemical vapor deposition. be.
発明が解決しようとする問題点
縦型ＭＯ８ＦＥＴにおいて、チャンネル形成用のＰ型拡
散領域とドレインの低濃度Ｎ型シリコン半導体基板で構
造されるダイオードに逆方向電圧が印加された場合、チ
ップ内部のＭＯ８ＦＥＴ部分では、三部分に分割された
Ｐ型拡散領域から、それぞれドレインの低濃度シリコン
半導体基板に向かって空乏層が広がるため、表面の電界
は互いに打消し合い緩和される。しかし、チップの周辺
部分においては、空乏層は、一方向にのみ広がるため、
印加電圧の増大とともに表面の電界も大きくなっていく
。しかも、チップ周辺部の低濃度Ｎ型シリコン半導体基
板上に形成された絶縁膜のうち一層目の熱酸化膜は、構
造的に安定であるため強度な電界に対しても比較的安定
であるが、二層目の化学的気相成長によって形成された
絶縁膜は、環境変化に対して、特に温度と電界に対して
イオンの移動や分極作用が生じ易く、不安定である。こ
の結果、高温において長時間逆方向電圧を印加した場合
、耐圧の低下やリーク電流の増大が生ずるという問題点
があった。Problems to be Solved by the Invention In a vertical MO8FET, when a reverse voltage is applied to a diode constructed of a P-type diffusion region for forming a channel and a low concentration N-type silicon semiconductor substrate for a drain, the MO8FET inside the chip Since the depletion layer spreads from the P-type diffusion region divided into three parts toward the low concentration silicon semiconductor substrate of the drain, the electric fields at the surface cancel each other out and are relaxed. However, in the peripheral area of the chip, the depletion layer only spreads in one direction.
As the applied voltage increases, the electric field on the surface also increases. Furthermore, the thermal oxide film, which is the first layer of the insulating film formed on the low concentration N-type silicon semiconductor substrate around the chip, is structurally stable and therefore relatively stable against strong electric fields. The second insulating film formed by chemical vapor deposition is unstable due to environmental changes, particularly temperature and electric fields, which tend to cause ion movement and polarization. As a result, when a reverse voltage is applied for a long time at a high temperature, there is a problem in that the breakdown voltage decreases and the leakage current increases.
本発明は、このような問題を解決するもので、縦型ＭＯ
ＳＦＥＴにおける逆方向電圧印加時での信頼性を向上す
ることを目的とするものである。The present invention solves these problems, and is aimed at solving vertical MO
The purpose of this is to improve the reliability when applying a reverse voltage to the SFET.
問題点を解決するための手段
本発明の縦型ＭＯＳＦＥＴは上記の問題点を排除するも
のであって、チップ周辺部において、層間絶縁膜形成時
に同時に形成されてしまう二層目の化学的気相成長で形
成された絶縁膜を意識的に除去し、−層目の熱酸化膜の
み残した構造のものである。Means for Solving the Problems The vertical MOSFET of the present invention eliminates the above-mentioned problems, and the second layer of chemical vapor phase that is formed at the same time as the interlayer insulating film is formed in the chip peripheral area. It has a structure in which the insulating film formed by growth is intentionally removed, leaving only the -th layer thermal oxide film.
作用
この構造によれば、逆方向電圧印加時に強電界がかかる
チップ周辺部において低濃度シリコン半導体基板の上は
、構造的に非常に安定な熱酸化膜のみで覆われているた
め、強度な電界に対して安定であり、信頼性の向上が得
られる。Effect: According to this structure, in the chip peripheral area where a strong electric field is applied when a reverse voltage is applied, the top of the low-concentration silicon semiconductor substrate is covered only with a structurally very stable thermal oxide film, so that a strong electric field is not generated. It is stable against various conditions and improves reliability.
実施例
本発明の縦型ＭＯ８ＦＥＴの実施例について第１図に示
したＮチャンネル型縦型ＭＯＳＦＥＴの断面構造を参照
して説明する。Embodiment An embodiment of the vertical MOSFET of the present invention will be described with reference to the cross-sectional structure of the N-channel vertical MOSFET shown in FIG.
各部分の名称及び動作原理は、先に説明した従来例のも
のと同一であるが、チップ周辺部はドレインの低濃度Ｎ
型シリコン半導体基板１の上に熱酸化により形成した厚
み１．２μの酸化膜９のみがあり、層間絶縁膜６を化学
的気相成長によって形成した時に同時形成される絶縁膜
を除去した構造となっている。The names and operating principles of each part are the same as those of the conventional example described above, except that the peripheral part of the chip has a low concentration of N at the drain.
This structure has only an oxide film 9 with a thickness of 1.2 μm formed by thermal oxidation on the type silicon semiconductor substrate 1, and an insulating film formed at the same time when the interlayer insulating film 6 is formed by chemical vapor deposition is removed. It has become.
発明の効果
以上のように本発明によれば、強電界が加わるチップ周
辺部は、安定な熱酸化膜のみで覆われ、逆方向電圧印加
時における信頼性が大幅に向上される。第２図に本発明
の詳細な説明するため、高温逆バイアス試験の結果を従
来例装置のそれとくらべて経時特性図で示す。結果は、
試９時間に対する耐圧劣化を、試験数３０からの百分率
（％）で示した。図かられかるように、本発明法で得た
縦型ＭＯ８ＦＥＴの信頼性は高い。Effects of the Invention As described above, according to the present invention, the peripheral area of the chip to which a strong electric field is applied is covered only with a stable thermal oxide film, and the reliability when applying a reverse voltage is greatly improved. In order to explain the present invention in detail, FIG. 2 shows the results of a high temperature reverse bias test in a time-dependent characteristic diagram in comparison with that of a conventional device. Result is,
The deterioration in pressure resistance over 9 hours of testing is expressed as a percentage (%) from 30 tests. As can be seen from the figure, the reliability of the vertical MO8FET obtained by the method of the present invention is high.
第１図は本発明による縦型ＭＯＳＦＥＴの断面図、第２
図は高温逆バイアス試験の経時特性図、第３図は従来の
縦型Ｍ ＯＳ Ｆ Ｅ Ｔの断面図である。
１・・・・・・ドレインの低濃度Ｎ型シリコン半導体基
板、２・・・・・・チャンネル領域形成用のＰ型拡散領
域、３・・・・・・Ｎ型ソース領域、４・・・・・・ゲ
ート酸化膜、５・・・・・・ゲート電極、６・・・・・
・化学的に気相成長させた層間絶縁膜、７・・・・・・
ソース電極、８・・・・・・ドレイン電極、９・・・・
・・熱酸化により形成された酸化膜、１０・・・・・・
層間絶縁膜と同時に形成される化学的気相成長による絶
縁膜。Figure 1 is a sectional view of a vertical MOSFET according to the present invention, Figure 2 is a cross-sectional view of a vertical MOSFET according to the present invention;
The figure is a time-lapse characteristic diagram of a high temperature reverse bias test, and FIG. 3 is a cross-sectional view of a conventional vertical MOSFET. 1... Low concentration N-type silicon semiconductor substrate for drain, 2... P-type diffusion region for forming a channel region, 3... N-type source region, 4... ...Gate oxide film, 5...Gate electrode, 6...
・Interlayer insulating film grown in chemical vapor phase, 7...
Source electrode, 8...Drain electrode, 9...
...Oxide film formed by thermal oxidation, 10...
An insulating film formed by chemical vapor deposition at the same time as an interlayer insulating film.
Claims (1)
により形成された酸化膜のみが形成されていることを特
徴とする縦型ＭＯＳ電界効果トランジスタ。A vertical MOS field effect transistor characterized in that only an oxide film formed by thermal oxidation is formed on a low concentration semiconductor substrate in a peripheral area of a semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62272506A JPH01115163A (en) | 1987-10-28 | 1987-10-28 | Vertical MOS field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62272506A JPH01115163A (en) | 1987-10-28 | 1987-10-28 | Vertical MOS field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01115163A true JPH01115163A (en) | 1989-05-08 |
Family
ID=17514852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62272506A Pending JPH01115163A (en) | 1987-10-28 | 1987-10-28 | Vertical MOS field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01115163A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1182706A2 (en) * | 1991-08-28 | 2002-02-27 | Advanced Power Technology Inc. | IGBT process and device |
-
1987
- 1987-10-28 JP JP62272506A patent/JPH01115163A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1182706A2 (en) * | 1991-08-28 | 2002-02-27 | Advanced Power Technology Inc. | IGBT process and device |
| EP1182706A3 (en) * | 1991-08-28 | 2003-10-08 | Advanced Power Technology Inc. | IGBT process and device |
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