JPH01105577A - Manufacturing method of thin film transistor matrix panel - Google Patents
Manufacturing method of thin film transistor matrix panelInfo
- Publication number
- JPH01105577A JPH01105577A JP62262426A JP26242687A JPH01105577A JP H01105577 A JPH01105577 A JP H01105577A JP 62262426 A JP62262426 A JP 62262426A JP 26242687 A JP26242687 A JP 26242687A JP H01105577 A JPH01105577 A JP H01105577A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin film
- film transistor
- electrode
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000011159 matrix material Substances 0.000 title claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 17
- 229910052723 transition metal Inorganic materials 0.000 claims description 11
- 150000003624 transition metals Chemical class 0.000 claims description 11
- 239000010408 film Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 229910021350 transition metal silicide Inorganic materials 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- VLTRZXGMWDSKGL-UHFFFAOYSA-N perchloric acid Chemical compound OCl(=O)(=O)=O VLTRZXGMWDSKGL-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 241000238413 Octopus Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- FZIZEIAMIREUTN-UHFFFAOYSA-N azane;cerium(3+) Chemical compound N.[Ce+3] FZIZEIAMIREUTN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010411 cooking Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- GOUZWOPDZOFEKT-UHFFFAOYSA-N dichloromethane;nitric acid Chemical compound ClCCl.O[N+]([O-])=O GOUZWOPDZOFEKT-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔概 要〕
本発明は薄膜トランジスタマトリクスパネルの製造方法
に関し、
ａ−Ｓｉ：Ｈ層を形成する際に、下地層を予め段差のな
い平坦な面としておくことによって、薄膜トランジスタ
の信頼性及びトランジスタの特性を向上させることを目
的とし、
絶縁性基板（１）上に第１のａ −Ｓ ｉ ： ＨＪＩ
１（６）を形成し、該第１のａ−Ｓｉ：Ｉ（ｐｉの所望
区域を選択的に遷移金属と反応させることにより、前記
第１のａ−Ｓｉ：ＲＮの所望区域を前記遷移金属の珪化
物層からなり画素電極を含む下部電極（２）に形成し、
次いで第２のａ −Ｓ ｉ ： ＨＪｉ（７）、ゲート
絶縁膜（４）、及び上部電極（５）を積層する工程を含
むよう構成した。[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing a thin film transistor matrix panel, and the present invention relates to a method for manufacturing a thin film transistor matrix panel. For the purpose of improving the reliability of the transistor and the characteristics of the transistor, a first a-S i :HJI
1(6) and selectively reacting the desired areas of the first a-Si:I(pi with the transition metal). A lower electrode (2) including a pixel electrode is formed of a silicide layer of
Next, the structure included a step of laminating a second a-S i :HJi (7), a gate insulating film (4), and an upper electrode (5).
本発明は薄膜トランジスタマトリクスパネルの製造方法
、即ちアモルファスシリコン層を動作半導体層として用
いたスタガード型の１１膜トランジスタによって駆動す
る液晶表示装置の製造方法に関する。The present invention relates to a method of manufacturing a thin film transistor matrix panel, that is, a method of manufacturing a liquid crystal display device driven by a staggered 11-film transistor using an amorphous silicon layer as an active semiconductor layer.
現在簿膜トランジスタは安価で大面積のものが作成可能
のため、液晶デイスプレィ等に多く用いられている。At present, thin film transistors are widely used in liquid crystal displays and the like because they are inexpensive and can be manufactured with a large area.
第４図に従来の薄膜トランジスタの断面構造を示す。同
図に示す薄膜トランジスタを作成するには、まずガラス
基板等の絶縁性基板１上にソース電極とこれに接続する
画素電極、及びドレイン電極等の下部電極２を形成し、
しかる後動作半導体層であるアモルファスシリコン（ａ
−Ｓｉ：Ｈ）Ｎ３．ゲート絶縁膜４．及びゲート電極で
ある上部電極５を形成する。FIG. 4 shows a cross-sectional structure of a conventional thin film transistor. To create the thin film transistor shown in the figure, first, a source electrode, a pixel electrode connected thereto, and a lower electrode 2 such as a drain electrode are formed on an insulating substrate 1 such as a glass substrate.
After that, amorphous silicon (a
-Si:H)N3. Gate insulating film 4. And an upper electrode 5 which is a gate electrode is formed.
このようにａ−Ｓｉ：ＨＩＪ３等は、段差のある下部電
極２の上に形成されているのでこれまた当然段差が生じ
、そのため下部電極２と上部電極５との間に短絡が生じ
、また段差の所でａ−Ｓｉ：ＨＦＪ３の抵抗が高くなっ
て、トランジスタ特性を悪化させる。In this way, a-Si:HIJ3 etc. are formed on the lower electrode 2 which has a step, so naturally a step also occurs, which causes a short circuit between the lower electrode 2 and the upper electrode 5, and also a step. At this point, the resistance of the a-Si:HFJ3 increases, deteriorating the transistor characteristics.
このように従来の薄膜トランジスタの形成方法では、上
部電極５と下部電極２間の短絡や、ａ −５ｉ：Ｈ１ｉ
３の抵抗が高くなるという問題があった。In this way, in the conventional method of forming a thin film transistor, a short circuit between the upper electrode 5 and the lower electrode 2 or a −5i:H1i
There was a problem that the resistance of No. 3 became high.
′本発明はａ−Ｓｉ：Ｈ層を形成する際に、下地層を予
め段差のない平坦な面としておくことによって、薄膜ト
ランジスタの信頼性及びトランジスタの特性を向上させ
ることを目的とする。'An object of the present invention is to improve the reliability of a thin film transistor and the characteristics of the transistor by preparing the base layer as a flat surface with no steps before forming the a-Si:H layer.
本発明の要旨を第１図により説明する。 The gist of the present invention will be explained with reference to FIG.
まず絶縁性基板１上に第１のａ−Ｓｉ：Ｈ層６を形成し
、これの所望部分を選択的に遷移金属と反応させて、遷
移金属の珪化物（シリサイド）層からなる下部電極２を
形成する。この後余分な遷移金属を除去して、同図に見
られるように、画素電極及びこれに接続するソース電極
等からなる下部電極２と第１のａ−Ｓｉ：Ｈ層６からな
り表面が平坦化された下地層が得られる。First, a first a-Si:H layer 6 is formed on an insulating substrate 1, and a desired portion of this layer is selectively reacted with a transition metal to form a lower electrode 2 made of a transition metal silicide layer. form. After that, the excess transition metal is removed, and as shown in the figure, the lower electrode 2 consists of the pixel electrode and the source electrode connected thereto, and the first a-Si:H layer 6 has a flat surface. A hardened base layer is obtained.
このように第１のａ−Ｓｉ：Ｈ層６の一部を化成して下
部電極２を形成することにより、平坦な下地層を形成し
、その上に、第２のａ−Ｓｉ：Ｎ１７、ゲート絶縁膜４
．及び上部電極５を形成する。By chemically converting a part of the first a-Si:H layer 6 to form the lower electrode 2 in this way, a flat base layer is formed, and the second a-Si:N17, Gate insulating film 4
．． and the upper electrode 5 is formed.
第１のａ＝ｓｉｓＨ層６は、絶縁性基板ｌ上に堆積され
たものであるから、−様な厚さに形成されている。上記
下地層はこれの所望部分を化成して下部電極２を形成し
たものであるので、これの厚さも全域にわたってほぼ一
様であり、その表面 。Since the first a=sisH layer 6 is deposited on the insulating substrate l, it is formed to have a thickness similar to -. Since the lower electrode 2 is formed by chemically converting a desired portion of the base layer, the thickness of the base layer is approximately uniform over the entire area, and the thickness of the base layer is approximately uniform over the entire surface.
はほぼ平坦なものとなる。is almost flat.
従って第２のａ−３ｔ：Ｈ層７等の上層膜は、この平坦
な下地層の上に積層することができ、従来のような段差
が存在することによる悪影響を除去できる。Therefore, the upper layer film such as the second a-3t:H layer 7 can be laminated on this flat underlayer, and the adverse effects caused by the presence of the conventional step can be eliminated.
以下本発明の一実施例を第２図（ａ）〜（ｄ）及び第３
図（ａ）〜（ｄ）により説明する。なお、第３図の（ａ
）〜（ｄ）は第２図の＋８）〜（ｄ）のＡ−Ａ矢視部を
示す要部断面図である。An embodiment of the present invention will be described below in Figs. 2(a) to (d) and 3.
This will be explained with reference to figures (a) to (d). In addition, (a
) to (d) are main part sectional views taken along the line A-A of +8) to (d) in FIG. 2.
まず両図の（ａ）に示すように、ガラス基板のような絶
縁性基板１上に、第１のａ−ＳｉｓＨ層６を凡そ１００
人の厚さに堆積し、□次いでクロム（Ｃｒ）のような遷
移金属を、凡そ５００〜１０００人の厚さに蒸着し、こ
れを所定のパターンに従って選択的に除去することによ
り、下部電極２形成領域の上層に遷移金属Ｎ８を形成す
る。以上でドレイ電極、ソース電極及びこれと接続する
画素電極のパターンが形成される。First, as shown in FIGS.
□ Next, a transition metal such as chromium (Cr) is deposited to a thickness of approximately 500 to 1000 nm, and then selectively removed according to a predetermined pattern to form the lower electrode 2. A transition metal N8 is formed in the upper layer of the formation region. With the above steps, patterns of a drain electrode, a source electrode, and a pixel electrode connected thereto are formed.
次いで両図の（ｂ）に示すように、約２００℃で凡そ１
時間加熱処理を加えて、遷移金属層８とその下部の第１
のａ−−Ｓｉ：Ｈ層６とを反応させることにより、珪化
物（シリサイド）Ｎを形成する。Then, as shown in (b) of both figures, at about 200℃
The transition metal layer 8 and the first layer below the transition metal layer 8 are
By reacting with the a--Si:H layer 6, silicide N is formed.
このシリサイド層は低抵抗であるので、これを下部電極
２として使用する。９れでドにイン電極。Since this silicide layer has low resistance, it is used as the lower electrode 2. In-electrode at 9.
ソース電極および画素電極等が形成された。A source electrode, a pixel electrode, etc. were formed.
次に両図の（Ｃ）に示す如く、上記工程において第１の
ａ−３ｔ電ＨＪ！Ｊ６上に残留した濯移金属８の不要部
を、エツチングで除去する。このエツチング液としては
、使用する遷移金属が例えばＣｒの場合には、硝酸第２
セリウムアンモン（Ｃｅ（ＳＯオ）２・２（ＮＨ＊）ｚ
・ＳＯ４・２１１ｔＯ）と過塩素酸（ＨＣｊ！ａ）等を
用いることができる。本工程において、シリサイドとな
った下部電極２は上記エツチング液に反応しないので、
除去されずに残留する。Next, as shown in (C) of both figures, in the above process, the first a-3t electric HJ! The unnecessary portion of the rinsing metal 8 remaining on J6 is removed by etching. When the transition metal used is, for example, Cr, the etching solution may be dichloromethane nitric acid.
Cerium ammonium (Ce(SOO)2.2(NH*)z
・SO4・211tO) and perchloric acid (HCj!a) can be used. In this step, the lower electrode 2 that has become silicide does not react with the etching solution, so
remains without being removed.
このようにして下部電極２とその間を第１のａ−Ｓｉ：
Ｈ１’！！６で充填した形状の、表面が平坦な下地層が
形成される。なお同図のＥは画素電極を示す。In this way, the lower electrode 2 and the first a-Si:
H1'! ! A base layer having a shape filled with 6 and having a flat surface is formed. Note that E in the figure indicates a pixel electrode.
以上の如く形成したことにより、本実施例の画素電極Ｅ
は透明であり、また、ソース電極およびドレイン電極は
表面が平坦に形成される。By forming as described above, the pixel electrode E of this example
is transparent, and the source electrode and drain electrode are formed with flat surfaces.
この下地層の上に、第２のａ−３ｔ：）ＩＦＪ７゜ゲー
ト絶縁膜４を連続的に積層し、更にその上に上部電極５
を形成して、両図の（ｄ）に示す薄膜トランジスタが完
成する゛。On this base layer, a second a-3t:) IFJ7° gate insulating film 4 is continuously laminated, and an upper electrode 5 is further layered on top of this.
The thin film transistor shown in (d) of both figures is completed.
上述したように本実施例では、−下部電極２を含む下地
層の表面が平坦化されるので、このあと積層する各層も
平坦化され、従来のように段差の存在による種々の問題
が解消する。As described above, in this embodiment, since the surface of the base layer including the lower electrode 2 is flattened, each layer to be laminated thereafter is also flattened, and various problems caused by the presence of steps, which were conventional, are solved. .
またここで珪化物が形成可能な遷移金属として、Ｃｒ、
Ｍｏ、Ｎｉ、Ｗ、Ｐｔ、Ｔｉ、ｖ、Ｚｒ。In addition, as transition metals capable of forming silicides, Cr,
Mo, Ni, W, Pt, Ti, v, Zr.
Ｎｂ、Ｈｆ、Ｐｄ、Ｒｈ、Ｇｏ等を用いることができる
。Nb, Hf, Pd, Rh, Go, etc. can be used.
以上説明した如く本発明によれば、下部電極と上部電極
間の短絡発生が防止され、更にトランジスタ特性及び信
顛性を大幅に向上させることができる。As described above, according to the present invention, short circuits between the lower electrode and the upper electrode can be prevented, and the transistor characteristics and reliability can be significantly improved.
第１図は本発明の原理説明図、
第２図（ａ）〜（ｄ）及び第３図（ａ）〜（ｄ）は本発
明一実施例をその製造工程の順に示す説明図で、第３図
（ａ）〜（ｄ）は第２図（ａ）〜（ｄ）のＡ−Ａ矢視部
所面を示し、第４図は従来の薄膜トランジスタの説明図
である。
図において、１は絶縁性基板、２は下部電極、４はゲー
ト絶縁膜、５は上部電極、６は第１のアモルファスシリ
コン（ａ−Ｓｉ ： Ｈ） Ｎ、 ７は第２のアモルフ
ァスシリコン層、８は遷移金属［ヲノト名ηＵ月、ｌＩ
ｉ！ Ｊ！’ Ｆ、乞り月図第１図
手発明−炊例の引けは計りｑｍ
第２図
半発明−だ特例の＠ｌガ３上ｔｉ蛸ｍ
第３図FIG. 1 is an explanatory diagram of the principle of the present invention. FIGS. 2 (a) to (d) and 3 (a) to (d) are explanatory diagrams showing one embodiment of the present invention in the order of its manufacturing process. 3(a) to 3(d) show the view taken along the line A-A in FIGS. 2(a) to 3(d), and FIG. 4 is an explanatory diagram of a conventional thin film transistor. In the figure, 1 is an insulating substrate, 2 is a lower electrode, 4 is a gate insulating film, 5 is an upper electrode, 6 is a first amorphous silicon (a-Si:H)N, 7 is a second amorphous silicon layer, 8 is a transition metal [wonoto name ηU month, lI
i! J! 'F, begging moon diagram Figure 1 Manual invention - The closing of the cooking example is a measure qm Figure 2 Half invention - Special case @lga 3 upper ti octopus Figure 3
Claims (1)
形成し、該第１のａ−Ｓｉ：Ｈ層の所望区域を選択的に
遷移金属と反応させることにより、前記第１のａ−Ｓｉ
：Ｈ層の所望区域を前記遷移金属の珪化物層からなり画
素電極を含む下部電極（２）に形成し、次いで第２のａ
−Ｓｉ：Ｈ層（７）、ゲート絶縁膜（４）、及び上部電
極（５）を積層する工程を含むことを特徴とするスタガ
ード型の薄膜トランジスタマトリクスパネルの製造方法
。forming a first a-Si:H layer (6) on an insulating substrate (1) and selectively reacting desired areas of the first a-Si:H layer with a transition metal; first a-Si
: A desired area of the H layer is formed on the lower electrode (2) comprising the transition metal silicide layer and including the pixel electrode, and then the second a
- A method for manufacturing a staggered thin film transistor matrix panel, comprising the step of laminating a Si:H layer (7), a gate insulating film (4), and an upper electrode (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26242687A JPH0824188B2 (en) | 1987-10-16 | 1987-10-16 | Method of manufacturing thin film transistor matrix panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26242687A JPH0824188B2 (en) | 1987-10-16 | 1987-10-16 | Method of manufacturing thin film transistor matrix panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01105577A true JPH01105577A (en) | 1989-04-24 |
| JPH0824188B2 JPH0824188B2 (en) | 1996-03-06 |
Family
ID=17375618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26242687A Expired - Fee Related JPH0824188B2 (en) | 1987-10-16 | 1987-10-16 | Method of manufacturing thin film transistor matrix panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0824188B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5250451A (en) * | 1991-04-23 | 1993-10-05 | France Telecom Etablissement Autonome De Droit Public | Process for the production of thin film transistors |
| JPH09172185A (en) * | 1996-11-27 | 1997-06-30 | Nec Corp | Forward stagger type thin film transistor |
-
1987
- 1987-10-16 JP JP26242687A patent/JPH0824188B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5250451A (en) * | 1991-04-23 | 1993-10-05 | France Telecom Etablissement Autonome De Droit Public | Process for the production of thin film transistors |
| JPH09172185A (en) * | 1996-11-27 | 1997-06-30 | Nec Corp | Forward stagger type thin film transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0824188B2 (en) | 1996-03-06 |
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