JPH01103364A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain an excellent synthesized picture without generating any blank by applying insertion synthesis while placing priority over a smaller area designated by a means designating an area and a picture to be supplied in applying insertion synthesis. CONSTITUTION:In fitting a color picture data from a video processor 3 to a video processing unit 12 in a color reader 1 is applied to a position designated with area by a digitizer 16. When the area designated by the digitizer 16 is larger, the small area of a color picture outputted from the processor 3 has priority and the picture is inserted only to the range and an original 999 is printed out to the outside area. When the area designated by the digitizer 16 is smaller than the effective area of the video picture, it has priority and the picture is limited to the range. In synthesizing the two pictures, no blank is produced and excellent synthesis is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and particularly to an image processing apparatus capable of synthesizing a plurality of images.

[Conventional technology]

2. Description of the Related Art Image compositing apparatuses that create an image by composing a plurality of images are conventionally known.

[Problem to be solved by the invention]

When combining image data in a designated area in the above-described apparatus, it has been considered to automatically fit the image data into a desired area by scaling the image data.

However, in the above-mentioned apparatus, if the image data to be synthesized is smaller than the specified area, a blank area will occur if the image data to be synthesized is smaller than the designated area, so the synthesis method is still insufficient. The problem was that this was not always the case.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and provide a novel image processing device that can synthesize a plurality of images favorably.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides means for specifying an area in which an image is to be fitted, a means for supplying an image to be fitted in the area, and an area specified by the specifying means and a supplying means for supplying the image. and a means for inlaying and compositing a small area of the image with priority.

[Effect]

In the above configuration, the compositing means performs compositing, giving priority to a smaller area among the area specified by the specifying means and the image supplied by the supplying means.

Shiiha 1 〔Example〕 The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a color image forming system to which the present invention is applied. As shown in the figure, this system has an upper digital color image reading device (hereinafter referred to as a color reader) 1, a lower portion a digital color image printing device (hereinafter referred to as a color printer) 2, and a video processing device 3. This color reader 1 reads color image information of a document for each color using color separation means and a photoelectric conversion element such as a CCD, which will be described later, and converts it into an electrical digital image signal. Further, the color printer 2 is an electrophotographic laser beam color printer that reproduces a color image in each color according to the digital image signal, and records the image by transferring it to recording paper multiple times in the form of digital dots. The video processing device 3 is a device for converting an analog video signal from an externally connected video device into a digital image signal and inputting it to the color reader 1.

First, the configuration of the color reader I will be explained. 999 is an original, 4 is a platen glass on which the original is placed, and 5 is a rod array for collecting the reflected light image from the original that has been exposed and scanned by the halogen exposure lamp IO, and inputting the image to the 1-magnification full color sensor 6. It is a lens, 5, 6.7. 10 as a document scanning unit 11, which performs exposure scanning in the direction of arrow A1. The color-separated image signals obtained by reading every l line without exposure scanning are amplified to a predetermined voltage by the sensor output signal amplification circuit 7, and then inputted to the video processing unit via the signal line 501 and subjected to signal processing. Ru. 5
01 is a coaxial cable to ensure faithful transmission of signals. A signal 502 is a signal line that supplies drive pulses for the same-magnification full-color sensor 6, and all necessary drive pulses are generated within the video processing unit 12. Reference numeral 8.9 denotes a white plate and a black plate for white level correction and black level correction of the image signal, and by irradiating them with a halogen exposure lamp 1O, a signal level of a predetermined density can be obtained, and the video signal. Used for white level correction and black level correction.

Reference numeral 13 denotes a control unit having a microcomputer, which controls the display on the operation panel 20, the manual control of keys, and the video processing unit 12 via a bus 508.
control, position sensor Sl.

The position of the document scanning unit 11 is determined by the signal line 509 by S2.
The stepping motor drive circuit 15 pulse-drives the stepping motor 14 for moving the scanning body 11 via the signal line 503, and the 0N10FF of the halogen exposure lamp 10 by the exposure lamp driver 21 via the signal line 504. It performs all controls of the color league unit l, such as control, light amount control, and control of the digitizer 16, internal keys, and display unit via the signal line 505. A color image signal read by the above-mentioned exposure scanning unit 11 during original exposure scanning is input to the video processing unit 12 via the middle circuit 7 and the signal line 501.

Next, details of the document scanning unit 11.degree. video processing unit 12 described above will be explained using FIG.

The color image signal input to the video processing unit 12 is processed by the sample hold circuit S/H43 to produce G (green) signal.
, B (blue), and R (red). The separated color image signal is subjected to analog processing in an analog color signal processing circuit 44 and then A/D converted.
It becomes a digital color image signal. In this embodiment, the color reading sensor 6 in the document scanning unit 11 is configured in a staggered manner divided into five areas as shown in FIG. This corrects the reading position deviation between the channel and the remaining 1 and 3.5 channels. The positional deviation correction flow signal from the FiFo memory 46 is input to the black correction circuit/white correction circuit, and the signal corresponding to the reflected light from the above-mentioned white board 8 and black board 9 is used to correct the color reading sensor 6. dark time unevenness,
The unevenness of the light amount of the halogen exposure lamp 10 and the sensitivity variation of the sensor are corrected. The color image data proportional to the input light amount of the color reading sensor 6 is converted by a logarithmic conversion circuit 86 to match the relative luminous characteristics of the human eye, and is then converted into a color image signal from the video interface 101 and a color image signal from the original scanning unit 11. The signal is input to a switching circuit 100 that switches color image signals.

Here, the import of color image data from the video processing device 3 to the video processing unit 12 in the color reader 1 in this embodiment will be explained.

Settings for such capture are performed by the digitizer described below. FIG. 3 is an external view of the digitizer 16. The key 427 is an entry key for setting the inset composition mode, which will be described later.The coordinate detection plate 420 is a coordinate position detection plate for specifying an arbitrary area on the document or setting the magnification. 421 specifies its coordinates.

The coordinate detection plate 420 indicates the size when recorded on a recording material such as paper from a video processing device, with 100% and 2 in the upper right corner.
There are three types of display: 00% and 400%.

To perform inset synthesis of images from the video processing device 3, after pressing the inset synthesis key 427 in FIG. 3, the point pen 421 is used to indicate the inset position.

This inset area refers to, for example, the shaded area in Fig. 4, which means that a signal such as timing chart 5YNC in Fig. 4 is transmitted line by line in the sub-scanning direction A-H. It is distinguished from the area of Note that C in FIG. 4 indicates the size of the entire document, and the shaded area is the area specified by the digitizer. The 5YNC signal 104 passes through the video interface 101 shown in FIG. 2 and is sent to the video processing device 3.

In addition to this 5YNC signal, the old video interface 1 sends the FREEZE signal 102 and VCL to the video processing device 3.
Output K103. A timing chart of these control lines is shown in FIG. That is, FREEZE signal 1
The 02 and 5YNC signals 104 are generated by pressing the start button on the operation unit 20, and as shown in FIG.
The EZE signal 102 becomes "1" by pressing the start button, and the 5YNC signal 104 becomes "1" in a range corresponding to the area specified by the digitizer 16.

However, if the number of copies is one or more and an error such as a paper jam occurs during copying, and the error is cleared and the copy button is pressed, the FREEZ signal 102 will be A.
active is not “1”, 5YNC104 and V
Only CLK 103 is output to interface 101. In this embodiment, full color printing is performed by repeating the color process shown in FIG. 5 104, and the colors of this print are shown in the figure.

Next, the operation of this embodiment configured as described above will be explained using the flowchart of the controller (CPU) shown in FIG. 11.

When the power is turned on, the controller 13 opens the operation panel 20.
and reads the operated keys onto the digitizer 16 (
#01). If there is a key operated, determine whether that key is a key that instructs to start copying (#03), and if it is a key that instructs to start copying, go to #05, otherwise go to #23
Branch to.

Here, we will first explain steps #23 and subsequent steps assuming that a key other than the copy start key is turned on.

In #23, the instruction of the area where the inset composition should be performed is the third one.
Determine whether or not the switch 427 shown in the figure is instructed, and if the instruction is made, the instructed area should be memorized #2
5) If the number of prints has not been specified, it is determined whether the number of prints has been specified (#27).

As a result of the determination, if the number of prints has been set, write the set number to the register (#29),
If the setting has not been made, processing corresponding to other key manual operations is performed (#31).

Next, a case where copy start is instructed in #03 will be explained. When the start of copying is instructed, first determine whether or not the error flag is set (#05).
If there is no error flag, the FRE described above in FIG.
Generate EZE signal 102 (#07).

As a result, image data is written into a memory 303 within the video processing device, which will be described later with reference to FIG. Next, the error flag is reset (, #09). In order to drive the scanner, an instruction is given to the stepping motor drive circuit 15 shown in FIG. 1 to start driving. As a result, the scanner starts moving, and HSYNC, V
CLK, each signal processing circuit shown in FIG. 1 is operated, and each color component of the full color is sequentially outputted to the color conversion circuit 50 shown in FIG. It is supplied to the printer 2. color printer 2
rotates a drum 716, which will be described later, in response to image signals sequentially sent from the video processing unit 12, and returns an ITOP signal (image leading edge signal) to the unit 12 every rotation.

In this embodiment, full-color printing is performed using four colors of Y, M, C, and Bk, and the drum 7 is used for color printing of -
16 four rotations are required.

Therefore, in #13, it is necessary to determine whether or not the ITOP signal has come 4 times (#13), and until the ITOP signal has come 4 times, it is necessary to determine whether an error has occurred on the printer side (#14).
), if there is no error, return to #13; if an error occurs, set the error flag once, stop driving the scanner, and determine whether the error has been cleared (#21). . When it is detected that ITOP has come four times in #13, it is considered that one sheet has been printed, so the number of sheets register should be decremented.
7), determine whether the content has become “θ” and set it to “0”.
”, return to ■, and if not 10'', return to #
Return to ll and continue the copy operation again.

In the embodiment shown in the flowchart described above, if an error occurs in the color printer due to a paper jam or other cause while copying multiple sheets (#14), the flow will resume after the error is cleared. Since the value returns to 0, the next copy operation will not be performed unless the copy start key is turned on.

Also, since the error flag is set once in #19, even if you turn on the copy start key after returning to the above-mentioned ■, the flow will branch from #05 to #ll, so the freeze signal in #07 will not occur. , it is possible to prevent new image signals from being written to the memory 303.

Therefore, the image data that was frozen before the error occurred is held in the memory 303, and the memory 303
It is possible to prevent other data from being written by mistake.

VCLK 103 is an image data synchronization signal within the video processing unit 12, and this signal is sent to the video processing device 3. Video processing device 3 sends color image signals 105, 106, 107 synchronized with VCLK 103 and an EN signal 108 indicating the effective area of this signal to video interface 101. When this EN signal 108 is O, the switching circuit 108 selects the color image signal from the logarithmic conversion circuit 86 and outputs it to the subsequent circuit, and when it is l, it selects the color image signal from 101 to the video interface. Output to the subsequent circuit.

Although it is possible to use the aforementioned 5YNC 104 as a control signal for switching the switching circuit 100, in this embodiment, the 5YNC 104 is not used and the switching circuit 100 is switched using the EN signal from the video processing device 3. Because of this, the following effects are achieved.

That is, when the switching circuit 100 is switched using the 5YNC signal described above, when the response of the video processing device 3 is slow, the color image signal 105. 106. The switching circuit 100 is switched before the switching circuit 107 is output, and therefore, at the time of switching the switching circuit 100, in other words, a black mark is generated at the end of the image switching composition. Accordingly, since the switching circuit 100 is switched by the EN signal from the video interface 101, the occurrence of such black sushi can be prevented.

Note that when the video processing device 3 performs image processing such as edge enhancement using a plurality of pixels, the response of the video processing device 3 becomes particularly slow.

Next, a detailed circuit diagram of the switching circuit 108 is shown in FIG.

The circuit diagrams 113 to 118 are data selectors such as 74LS157 (model name), which have two-person data, and select one of the two-person data in accordance with the signal 112 at the select terminal S. When signal 112 is 0, selector output OUT Y570. Y on the M571 and C572 lines. 120. Mo121. When Co122 is selected and signal 112 is 1, Y'105. M'
106°C' 107 is selected. In addition to the aforementioned EN signal 108, this selection signal 112 also applies to the controller 1.
It is controlled by signals 110, 111 from 3.

Depending on the settings of the signals 110 and 111, the switching circuit 100 has three functions: dedicated for video image signals, dedicated for reflective original (original for copying) images, and for inset synthesis.

This function is shown in the table below.

That is, if the signals 110 and 111 are set to 0, the digitizer 16
The reflective original is trimmed according to the area designated by , and color correction, masking, gamma conversion, etc. are controlled in accordance with the EN signal so that color correction, masking, gamma conversion, etc. can be performed satisfactorily according to the nature of the image to be imaged. Further, this EN signal 108 is used for color correction, which will be described later.
It is also connected to a masking circuit 48 and a gamma conversion circuit 52.

Next, return to FIG. 2 to continue the explanation. The signal from the switching circuit 11O is input to the black extraction UCR circuit 47 to generate a black component signal, and the black component signal is subtracted from the color signals 570.571.572. The color correction/masking circuit 48 performs color correction of the color separation filter of the color reading sensor 6 (shown in the first diagram) and the color image signal of the video processing device 3.

Here, the operation of the color correction/masking circuit 48 will be explained.

Masking correction is well known in which color correction is performed by calculating a linear equation for each color for each color component image data Yi, Mi, and Ci.

Since the color correction/masking circuit 48 in this embodiment makes the coefficient value variable with respect to the input image, the coefficient value can be set by the CPU via the data bus.

In this embodiment, the first matrix coefficient M8. Any coefficient of the second matrix coefficient M2 can be set via a bus connected to the controller 13.

The coefficients M are assigned to correct the color separation filter in the document scanning unit 11, and the coefficients M2 are assigned to correct the video processing device 3.

The switching of these two coefficients M, . . . M2 is selected by the EN signal 108, which is a signal from the video interface lot. That is, in the case of a color image signal from the original scanning unit 11, the coefficient of M1 is selected, and in the case of a signal from the video processing device 3, the coefficient of M2 is selected, and color correction is performed. The output of the color correction/masking circuit 48 is input to the color conversion circuit 5o, but in this embodiment, the function of this color conversion circuit 5o is ignored.

52 is the color balance of the output image in this system,
This is a gamma conversion circuit for controlling color shading, and basically converts data using an LUT (look-up table).
UT data is rewritten. In addition, the RAM of this embodiment
52 includes yellow, magenta, cyan, black, and M.
ONO and 5 ways, less (both 2 types (Fig. 6(b) A
and B), region A has a gamma characteristic of A, region B
has a gamma characteristic of B and is configured so that it can be obtained as a single print.

This switching between areas A and B is performed by an EN signal 108 from the video interface 101.

Further, the gamma conversion RAM 52 is configured to change characteristics for each color individually, and is rewritten from the controller 13 in association with operations from the liquid crystal touch panel keys on the scanning panel.

A scaling control circuit 53 and a 5-line buffer 54 scale the output signal of the gamma conversion circuit 52, and a filter circuit 55 performs edge emphasis and zooming (smoothing).
processing is performed. The output of the filter circuit 55 passes through a printer interface circuit 56 to the color printer 2.
is input.

As described above, in this system, the color image information from the video processing device 3 is inserted into the area specified by the digitizer 16, and the document scanning unit 11 and the video processing device 3 each perform optimal color correction and gamma correction. I do.

Next, the configuration of the video processing device 3 will be explained using FIG. 7.

In Fig. 7, 300 is a composite signal such as NTS.
The video signals input as C signals are R and G.

An NTSC decoder 301 converts the R and G signals from the RGB input a or the NTSC decoder 300 into B signals.

A switching circuit 302 selects one of the B signals, and the switching circuit 302 selects the signal selected by the switching circuit 301 as R and G, respectively.

B A/D converter that performs A/D conversion separately, 303 is A/D
This is a memory into which signals A/D converted by the converter 302 are written, and has a capacity for at least one frame of each of RGB. 304 is a digital filter that applies edge enhancement or smoothing to the signal read from the memory 303; 305 is a filter 30;
4, and 306 is a complementary color conversion table that converts the RGB signals interpolated by the interpolation circuit 305 into Y, M, and C signals corresponding to their complementary colors.

A memory control circuit 308 controls read, write, and refresh operations of the memory 303 and its addresses. The control circuit 308 puts the memory 303 into a write state in response to the FREEZE signal input via the interface 307.

Note that the control circuit 308 receives a V synchronization signal VDTV on the TV side.
Field discrimination signal FLDTV364 generated from 363.5YNC circuit 321, output 5YN of switching circuit 309
The output of the C detection circuit 310 and the output of the enlargement ratio selection switch 322 are input. In addition, the control circuit 308 is the 5Y
An area signal 366, which is a signal triggered by the NC signal and indicates an effective area of the memory 303, is generated. The switching circuit 309 is connected to the TV side clock C/TTV36.
1. The H synchronization signal HDTV362, VCLK103 on the interface side, and the aforementioned 5YNC104 are input, and when the presence of 5YNC is detected by the 5YNC detection circuit 310, VCLK103.5YNC104 is selected, and the absence of 5YNC is detected. CKT when
Select V, HDTV.

311 is a gate for performing a logical operation on the area signal 366 and 5YNC 104; 312 is a filter 304; a delay circuit for compensating for the delay caused by data latching in the expansion interpolation circuit 305; A delay circuit 313 has a delay time of 5H, and a delay circuit 314 has a delay time of 7 pixels.

315 is an AND gate.

316 to 318 are delay circuits for compensating for the time delay due to the expansion interpolation operation performed by the expansion interpolation circuit 305, 316 has a delay time corresponding to IH, and 317 has a delay time of 1
It has a delay time corresponding to a pixel. 318 is a delay circuit for compensating for delays caused by data latching in the complementary color conversion table 306 described above.

Furthermore, each of the delay circuits 312, 313, 314, 316, and 317 described above are the DVCK367 and DVH8368i described above.
,: more driven. When the magnification rate is changed by the selection switch 322, the period of DVCKSDVH3 changes accordingly, and therefore the delay time of each of the above-mentioned delay circuits also changes.

Reference numeral 320 is an AND gate that outputs the logical product of the aforementioned 5YNC 104 and the output ENI of the delay circuit 318.

Next, the operation of the embodiment configured as above will be explained. The video processing device 3 receives the input RG by the signal of FREEZE 102 sent from the video processing unit 2.
B signal a or NTSC signal NTSC decoder 30
One of the RGB signals 355 to 357 obtained by decoding with 0 is selected by the switching circuit 301, and the CKTV signal 36 obtained by the 5YNC circuit 321 is digitized by the A/D converter 302 according to the timing.
In this embodiment, the number of pixels written in the GB memory 303 is 640×480 pixels. RGB memory 3
The memory control circuit 308 controls the timing of read, write, and refresh operations of 03. When the 5YNC signal 104 is not input from the video processing unit 12, the 5YNC detection circuit 310 determines that there is no 5YNC,
The synchronization switching circuit 309 receives the synchronization signal on the TV side, that is, CKT.
Select V361 and HDTV362. When the 5YNC signal 104 is input from the video processing unit 12, the synchronization switching circuit 309 switches between V CL K 103 and 5YNC.
104, and the RGB memory 303 inputs VCLK103.5YNC104 (
7) Read out at timing.

The magnification ratio of the video image to be inserted into the reflective original 999 and synthesized is fixed to three types: 100%, 200%, and 400%, and is selected by the magnification selection switch 322. This signal enters the memory control circuit 308 and the RGB memory 308
Controls the reading of 3. In the case of 200%, pixels on the same line are read out twice, and in the case of 400%, the pixels in the same line are read out four times. Also, 100%, 200%,
A memory control circuit 308 synchronizes the RGB memory 303, filter circuit 304, and enlargement interpolation circuit 305 at each enlargement rate of 400%. DVCK365,D
VH3366+: This is done by synchronizing.

The signal read out from the RGB memory 303 is filtered by a filter circuit 304 using a 5×7 pixel matrix calculation, edge emphasis or smoothing is performed, and an enlargement interpolation circuit 305 converts the signal by 200% and 40%.
Interpolation at 0% enlargement is performed, and complementary color conversion table 30
6, the R, G, and B signals are C107 and M2, respectively.
The signals are converted into O3 and Y2O2 signals and passed through the reader interface circuit 307 to the video processing unit 12. In this embodiment, each RGB data read from the RGB memory 303 is processed in a so-called pipeline structure passing through a filter circuit 304, an enlarged interpolation circuit 305, and a complementary color conversion table 306, so that the data is input by each circuit. There is a time delay between when the data is output and when it is output. That is, as described above, since the video processing device 3 processes a plurality of stairs, a certain amount of time is required from when an instruction is given to output an image to when the image is actually output. In this embodiment to match this delay time, E
The N signal 10B is generated. Delay circuit 31
2,314° 317, 318, delay circuits 313, 315 in the line direction and gates 315, 318 provide a delay equal to the delay time in each circuit 303, 304° 305, 306, and each signal of C107, M2O3, Y105 E according to the period when valid image data is output.
N signal 108 outputs a valid signal.

In this example, the mesh ratio (the aspect ratio of one pixel) of the video image is 1:1, so the pixels are 640×480. Then, image data is output to enlarge this at a rate of 100%, 200%, or 400%. At this time, interface 3
There is no guarantee that the 5YNC signal 104 input to 07 will be input as a signal equal to the size of the enlarged image data. For this purpose, the memory control circuit 308 that controls the RGB memory 303 uses the 5YNC signal 104 to determine the size of the image to be read, 640 x 480 pixels (or 1280 x 960 pixels when enlarged by 200%, 400%
Image area signal 3 indicating 2560x1920 pixels when enlarged
Outputs 66. And this area signal 366 and 5YNC
The output ENI signal 37 is logically ANDed with the signal 104 by the gate 311 and simultaneously delayed by each delay circuit.
1 (output of the delay circuit 319) and the 5YNC signal 104 are ANDed by the gate 320. By this, 5
When the area of the YNC signal, that is, the area to be inset is larger than the output area of the image, the area of the EN signal 108 is limited by the image area signal 366, and conversely, when the area of the 5YNC signal 104 is small, the area of the image is Even if there is still a surplus, it is forcibly limited to the 5YNC signal area.

These operations are shown in FIGS. 8(a) and 8(b). In Fig. 8, (a) shows that the time span of the 5YNC signal is larger than that of the area signal, that is, when the area to be fitted is larger than the size of the image to be fitted, and (b) shows that the 5YNC signal is fitted in the opposite direction. 5YNC signal 104, area signal 366, ENo signal 370, EN signal 108, and image data 105 to 107 are shown when the area to be inserted is larger than the image to be fitted.

The time indicated as D in FIGS. 8(a) and 8(b) indicates the time delayed by the delay means consisting of 212 to 318 in FIG.

As described above, the filter circuit 304 has a window of 5 line pixels, and calculates the value of each pixel within this window to form a filter. This reduces the effective screen area by one to several lines, but this is hardly a problem. Delay circuit 316 for enlarged interpolation circuit 305
．． The same applies to gate 317 and gate 318.

Next, referring to FIG. 9, an explanation will be given on a print image output after image composition. The digitizer 16 marks the area where the video image will be inserted at two points a.

Specified by b. 5Y according to this designated area
An NC signal 104 is output from the video processing unit 12 to the video processing device 3. In the video processing device 3,
Video image C107, M2O3°Y105 signals are outputted to this area to the video processing unit 12.

At this time, when the area specified by the digitizer 16 is large as shown in FIG. 9(a), E
The video processing device 3 outputs the N signal 108, and the video processing unit 12 inserts a video image only in the area of this EN signal 108, and prints the original 999 placed on the color reader l in the area outside of the area. On the contrary, Figure 9 (b
), the area a- designated by the digitizer 16
When b is smaller than the effective area of the video image, 5YNC
A signal 104 defines an area for inset synthesis. As a result, the video image is inserted into the hatched area and synthesized.

Further, the RGB memory 303 of this embodiment is, for example, a D-RAM.
Because it uses memory like
A video signal (RGB or N
When writing the TSC signal) to the RGB memory 303 or retaining the written data, a refresh signal is generated according to the timing of the HDTV signal 362,
When the 5YNC signal 104 is input from the video processing unit 12 and the memory is being read, the 5YNC signal 1
A refresh signal is generated according to the timing of 04. At this time, HDTV signal 362 and 5YNC signal 1
Since the period of 04 is greatly different (in this example,
(The period of the HDTV signal 362 and the period of the 5YNC signal 104 are about four times different), and the number of refreshes per time is changed for each.

Next, the first section regarding the configuration of the memory control circuit 308 described above will be described.
This will be explained in detail using Figure 2.

In Figure 12, SCK (SLECTFD CLO
CK) SH3 (SLECTED HORIZONTAL
5IGNAL) is a signal that is switched by the aforementioned switching circuit 309 and input to the memory control circuit 308.

370 is a frequency divider whose frequency division ratio changes depending on the setting of the enlargement ratio setting switch 322 shown in FIG.
Similar to 370, 372 is a frequency divider whose frequency division ratio for dividing SH8 changes. 374 is a quaternary counter that counts the output of the frequency divider 370, 376 is a counter that counts addresses in the main scanning direction, 378 is a counter that counts addresses in the sub-scanning direction, and 380 is a counter that counts the output of the counter 376 and the area value 382. Comparator to compare with exit, 384
is a comparator that compares the output of the counter 378 and the output of the area value 386. Note that 382 and 386 are respectively image memory 3.
A value corresponding to the number of pixels in the horizontal and vertical directions of 03 is set in advance.

Therefore, when either of the outputs of the comparators 380 and 384 becomes L level, the output of gate 388 also becomes L level, and the area signal also becomes L level.

390 is the first output from the 2-bit output of the quaternary counter 374.
This is a logic circuit that generates the signals (B), (C), and (D) shown in Figure 3 (a). Note that (B) is RAS (
Row Address 5trobe), (C) is C
AS (ColumnAddress 5trobe)
, (D) are signals for switching a selector 391, which will be described later. 391 is the counter 3 in response to the above-mentioned (D) signal.
A selector 392 switches the output of one of the output counters 378 of 76 and outputs it as a memory address, and 392 is used for the above-mentioned (B) and (C) signals or the refresh signals (C) and (D) shown in FIG. 13(b). This is a selector that outputs a signal to the memory 303. 393 is a D-F that takes in the SH8 signal from the switching circuit 309 via the inverter 397.
F, and its output is connected to the enable terminal of the quaternary counter 395. 395 is a quaternary counter that counts the SCK signal from the switching circuit 309;
4 is calculated from the 2-bit output of the counter 395 in FIG.
) is a logic circuit that generates the signals (C) and (D) shown in FIG. 396 is a counter that is enabled according to the output of the quaternary counter 395, and is a counter that is enabled according to the output of the 5YNC detection circuit 3.
32 when it is detected that there is 5YNC by 10.
" is set, and when it is detected that there is no 5YNC, "8" is set, and the counter counts down in response to the SCK signal, and the counter output is the D-FF.
It is connected to the clear terminal of 393. anime) 3
98,400 and the inverter 399 are the controller 13
JK-F in response to the write/read signal R/W from the 5YNC circuit 321 shown in FIG.
Switch whether or not to enable F368. 40
1 is an OR gate that takes the OR of the output Q or π/W of the JK-FF 368 and inputs it to the enable terminal of the counter 378.

The operation of the memory control circuit 308 configured as above will be explained.

First, a case where a write instruction is issued from the controller 13 will be described. In this case, the R/W signal from the controller 13 is at H level, the counter 378 is enabled, and the output Q of the JK-FF 368 is determined according to the level of the FLD signal. JK-FF36B
indicates the vertical address of the memory 308 along with the counter 378, the output of the JK-FF 368 shows the least significant bit of the vertical address, and the output of the counter 378 shows the
Other bits are assigned respectively. Therefore, when the FLD signal is at L level, that is, in an odd field, the output Q of the JK-FF is fixed at H level, and only odd-numbered addresses are output as vertical addresses.

Conversely, when the FLD signal is at H level, that is, in an even field, the output Q of the JK-FF 368 is fixed at L level, and only even-numbered addresses are output as vertical addresses.

On the other hand, a horizontal address is generated by a frequency dividing circuit 370, a quaternary counter 374, and a counter 376.

The horizontal and vertical addresses generated in this way are stored in the logic circuit 39.
0 is selected by the selector 391 and output as a memory address. In synchronization with the horizontal and vertical addresses generated in this way, RAS and CAS are
The data is generated and written as shown in Figure (a). still,
In this case, the selector 392 outputs the signal on the logic 390 side to the memory 303.

Next, a case where a signal for reading is generated from the controller 13 will be described.

In such a case, the π/W signal becomes L level, and the JK-F
The output of F368 does not depend on the FLD signal, and is J K -FF
368 and counter 378 constitute one counter. Therefore, unlike when writing, the vertical address is incremented by "l".

Also, during reading, when the SH3 signal falls and the blanking period for reading begins, the output of D-FF393,
That is, the access/refresh signal is inverted to H level, and the memory 303 enters a refresh state.

In this case, the selector 392 selects RASγ and CASγ (FIG. 13(b)) created in the logic circuit 394 for refresh.
) is output to the memory 303.

As a result, the memory 303 automatically performs a refresh operation.

In this case, the counter 396 also includes the 5YNC detection circuit 3.
A value corresponding to the signal from 1O is set.

As this value, for example, "32" is set when the presence of 5YNC is detected by the 5YNC detection circuit, and "8" is set when it is detected that there is no 5YNC.

This is because, as described above, the periods of the HDTV signal 362 and the 5YNC signal 104 are greatly different, so it is necessary to change the timing of the refresh operation.

Further, during reading, the frequency division ratios of the frequency dividers 370 and 372 are set according to the enlargement magnification, and during enlargement, the period of the pulses output to the counters 376 and 378 is increased. Also, the area specified value from the digitizer is 382,3
A region signal 366 is output from gate 388 in response to a comparison of the value from 86 and the output from counter 376.degree. 378.

Next, the configuration of the color printer 2 that prints the image signal processed by the video processing unit 12 as described above will be explained as follows.
This will be explained using figures. In FIG. 1, 711 is a scanner, which includes a laser output unit that converts an image signal from the color reader 1 into an optical signal, a polygon mirror 712 of a polyhedron (for example, an octahedron), a motor (not shown) that rotates this mirror 712, and It includes an F/θ lens (imaging lens) 713 and the like. 714 is a reflecting mirror that changes the optical path of the laser beam, and 715 is a photosensitive drum. The laser beam emitted from the laser output section is reflected by a polygon mirror 712, passes through a lens 713 and a mirror 714, and is directed to a photosensitive drum 715.
The surface of the document is scanned linearly (raster scan) to form a latent image corresponding to the original image.

In addition, 717 is a primary charger, 718 is a full exposure lamp,
723 is a cleaner section that collects residual toner that has not been transferred; 724 is a pre-transfer charger; these members are arranged around the photosensitive drum 715.

726 is a developer unit that develops an electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure, and 731Y (for yellow), 731M (for mazetan), 731C (for cyan), and 731Bk are photosensitive and Developing sleeve 730Y that directly develops in contact with the drum 715
, 730M, 730C, and 7308 are toner hoppers that hold spare toner; 732 is a screw that transports the developer; and these sleeves 731Y to 73
1Bk, the toner hoppers 730Y to 7308 and the screw 732 constitute a developer unit 726, and these members are arranged around the rotation axis P of the developer unit. For example, when forming a yellow toner image, yellow toner development is performed at the position shown in this figure, and when forming a magenta toner image, the developing unit 726
is rotated around the axis P in the figure, and the developing sleeve 731M in the magenta developing device is disposed at a position in contact with the photoreceptor 715. Cyan and black development operate in the same way.

Further, 716 is a transfer drum that transfers the toner image formed on the photosensitive drum 715 onto paper, 719 is an actuator plate for detecting the moving position of the transfer drum 716, and 720 is a drum that is in close proximity to this actuator plate 719. 725 is a transfer drum cleaner, 727 is a paper pressing roller, 728 is a static eliminator, and 729 is a transfer charger. These members 71
9.720.725° 727, 729 are transfer rollers 71
It is arranged around 6.

On the other hand, 735 and 736 are paper feed cassettes that store paper (paper sheets), 737 and 738 are paper feed rollers that feed paper from the cassettes 735 and 736, and 739.740.741
is a timing roller that takes the timing of paper feeding and conveyance, and the paper fed and conveyed via these is guided by a paper guide 749 and wound around the transfer drum 716 while the leading edge is carried by a gripper to be described later, forming an image. Shift to process.

Further, 550 is a drum rotation motor, which rotates the photosensitive drum 715.
and the transfer drum 716 are rotated synchronously. 750 is a peeling claw that removes the paper from the transfer drum 716 after the image forming process is completed, 742 is a conveyor belt that conveys the removed paper, and 743 is an image fixing unit that fixes the paper that has been conveyed by the conveyor belt 742. The image fixing section 743 has a pair of heat pressure rollers 744 and 745.

With the above configuration, first, the photosensitive drum 71 is
A Y latent image is formed on the developing unit 731Y.
The image is developed by , and then transferred to the paper on the transfer drum, and then the developing unit 726 rotates around the axis P in the figure. Next, an M latent image is formed on the photosensitive drum by laser light, and the same operation is performed thereafter. This action is C, B
The same process is repeated for k, and when the image forming process is completed, the paper is peeled off by the peeling claw 750, and the image is fixed in the image fixing section 743, and the color image is printed on the screen in the embodiment described above. The digitizer shown in FIG. 3 was used as means for specifying the area into which the image should be fitted, and the video processing device 3 was used as means for supplying an image of a predetermined size to be fitted into the area.

In addition, the means for combining the area specified by the digitizer and the image from the video processing device 3 by preferentially fitting a smaller area between the area specified by the specifying means and the area of the image supplied by the supplying means. The switching circuit 100 is controlled so that the image from the video processing device is synthesized only in the smaller of the areas.

〔Effect of the invention〕

As described above, according to the present invention, when a plurality of images are combined, it is possible to perform a good combination without creating a blank area.

[Brief explanation of the drawing]

Figure 1 shows a color image forming system to which the present invention is applied.
2 is a block diagram showing the configuration of the document scanning unit 11° video processing unit 12 shown in FIG. 1; FIG. 3 is an external view of the digitizer 16 shown in FIG. 1; FIG. 4 is a diagram showing the inset area, and FIG. 5 is a diagram showing the FREEZE signal 102°VCLK output from the video interface 101 to the video processing device 3.
103,5 A timing chart showing the YNC signal 104, FIG. 6 is a diagram showing two types of gamma characteristics of the RAM 52 shown in FIG. 2, and FIG. 7 is a block diagram showing the configuration of the video processing device 3 shown in FIG. 1. 8(a) and 8(b) are timing charts for explaining the operation of the video processing device 3 shown in FIG. 7, and FIG. 9(a) and (b) are screen synthesis using the device of this embodiment. 10 is a block diagram showing the internal configuration of the switching circuit shown in FIG. 2, and FIG. 11 shows the operation of the controller 13 shown in FIG. 1. A timing chart for explanation; FIG. 12 is a block diagram showing the configuration of the memory control circuit 308 shown in FIG. 8; FIGS. 13(a) and (b) are operation of the memory control circuit 308 shown in FIG. 12. 2 is a timing chart for explaining. 1... Color reader, 2...
・・・・・・・・・・・・Color printer, 13・・・・
···········controller.

Claims (1)

[Claims] (1) Means for specifying an area in which an image should be fitted, means for supplying an image to be fitted into said area, giving priority to a smaller area between the area specified by said specifying means and the image supplied by said supplying means. 1. An image processing apparatus comprising: means for inlaying and compositing.