JP2862237B2 - Storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a storage device, and in particular, to a refresh operation with a predetermined synchronization.
It relates to a storage device that requires a work. [Prior art] Conventionally, refresh operation is performed at a predetermined cycle such as a DRAM.
For storage devices that require operation, refresh operation
Synchronization signal from a clock generator, for example,
It was configured so that the information held in the storage did not disappear. [Problems to be Solved by the Invention] However, in the above-mentioned DRAM, some problems cause a problem.
The reference signal generated for performing the flush operation is
Is switched to another reference signal that is asynchronous with the signal of
The refresh interval is long before and after the switch.
Information may become unstable and destroyed
There was a problem that it would also be done. An object of the present invention is to solve such a problem. <Means for Solving the Problems> The storage device of the present invention is designed to solve the above-described problems.
Image memory that requires a refresh operation at a predetermined cycle (actual
In the embodiment, storage using (corresponding to the memory 303 in FIG. 7)
An apparatus for synchronizing with an image signal to be written to the image memory,
Sync signal for refresh operation to the image memory
The write synchronization system that occurs (the switching described in FIG.
Of the RGB or NTSC signal switched by the
HDTV signal 362 based on one of the respective synchronization signals
Refresh signal of the memory 304 in accordance with the timing of
The output refresh signal of the D-FF393 shown in FIG. 12 is generated.
Circuit), an image signal from the image memory at a given timing.
When reading the signal, the
Generate synchronization signal for refresh operation to memory
Readout synchronization system (also with reader interface 307
Notes based on SYNC104 timing given via
Circuit for generating a refresh signal of the memory 304), switching between the write synchronous system and the read synchronous system
When the image memory is continuously refreshed for a predetermined period or more,
Means to prevent the lock operation from being performed (also see FIG. 12).
In response to the signal from the SYNC detection circuit 310 shown in FIG.
32 is set when it is detected that
A counter to which 8 is set when detected,
Has counter 396) to determine refresh timing
It is characterized by doing. Embodiment The present invention will be described below in detail with reference to the drawings. FIG. 1 shows a color image forming system to which the present invention is applied.
1 shows an example of a schematic internal configuration. This system is as shown
Upper digital color image reading device (hereinafter referred to as color
1) and a digital color image pudding at the bottom
Printer (hereinafter referred to as a color printer) 2 and a printer.
And a video processing device 3. This color reader 1 will be
Original by using the color separation means described above and a photoelectric conversion element such as a CCD
Color image information for each color
To an image signal. The color printer 2 is
Color image according to the digital image signal
It is transferred to recording paper multiple times in digital dot form
Electrophotographic laser beam color pudding for recording
It is. The video processing device 3 is an externally connected video
Converts analog video signals from equipment to digital image signals.
In other words, it is a device for inputting to the color reader 1.
You. First, the configuration of the color reader 1 will be described. 999 is Hara
Manuscript, 4 is platen glass on which the original is placed, 5 is halogen
Reflected light image from document scanned by exposure lamp 10
To collect the image and input the image to the 1 × full color sensor 6
Rod array lenses, and 5, 6, 7, and 10 are original scanning units.
Exposure scanning is performed in the direction of arrow A1 as a unit 11 integrally.
Color obtained by scanning each line while exposing and scanning
The decomposed image signal is obtained by a sensor output signal amplification circuit 7.
After being amplified to a constant voltage, the video processing
The signal is input to the nit and processed. 501 is a signal faithful
It is a coaxial cable for ensuring transmission. Signal 502 is
A signal for supplying a drive pulse for the 1: 1 full-color sensor 6
Line and the required drive pulse is in the video processing unit 12.
Are all generated. 8, 9 are white level correction of image signal, black
White and black plates for level correction, halogen
By irradiating with the exposure lamp 10
The signal level can be obtained, and the white level of the video signal can be compensated.
Used for positive and black level correction. 13 is a control unit with a micro computer
Which is connected to the operation panel 20 by the bus 508.
Display, key input control and control of video processing unit 12
The original scanning unit 11 is controlled by the position sensors S1 and S2.
Is detected via signal lines 509 and 510, and
Stepping motor 14 for moving scanning body 11
Stepping motor drive circuit 15, which drives the pulse
Halo by exposure lamp driver 21 via Route 504
ON / OFF control of the exposure lamp 10, light intensity control, signal line 505
Control of digitizer 16 and internal keys, display unit, etc.
All controls of the color reader unit 1 are performed. Document exposure
At the time of scanning, it is read by the exposure unit 11 described above.
The color image signal obtained through the amplification circuit 7 and the signal line 501
Input to the video processing unit 12. Next, referring to FIG.
The details of the video processing unit 12 will be described. The color image signal input to the video processing unit 12 is
G (green), B at sample / hold circuit S / H43
(Blue) and R (red). Isolated
The color image signal is sent to an analog color signal processing circuit 44.
A / D conversion after analog processing
-It becomes a color image signal. In this embodiment, the original scanning unit
As shown in FIG.
FiFo memory because it is configured in a zigzag pattern divided into regions
46, using 2,4 channels that are pre-scanning and 1,
It corrects the reading position shift of 3,5 channels. FiF
o The position-corrected signal from the memory 46 is
Road / white correction circuit, the white plate 8 and the black plate
9 using a signal corresponding to the reflected light from
The darkness of the sensor 6 and the light amount of the halogen exposure lamp 10.
And variations in sensor sensitivity. Color reading
Color image data proportional to the amount of light input to the
Logarithmic conversion circuit 86 to match the relative visual characteristics of the eyes
After conversion from video interface 101
Color image signal and color image from document scanning unit 11
The signal is input to a switching circuit 100 for switching signals. Here, the video processing device 3 in this embodiment
-Color image data to video processing unit 12 in reader 1
Data acquisition will be described. The settings for such capture are provided by the digitizer described below.
Done by FIG. 3 is an external view of the digitizer 16.
You. A key 427 sets an inlay composite mode described later.
The coordinate detection plate 420 is
To specify an arbitrary area or set the magnification
The point pen 421 has its coordinates
Is specified. The coordinate detection plate 420 is written on paper from a video processing device.
The size when recorded on the recording material is 100% at the upper right, 200
% And 400% are displayed. The inset synthesis of the image from the video processing device 3 is the third
After pressing the inset composite key 427 in the figure, point pen 4
The position to be fitted is indicated by 21. This inset area
Refers to, for example, the shaded portion in FIG.
In the section of the scanning direction A → B, the tie of FIG.
It is distinguished from other areas by signals like ming chart sync.
You. In FIG. 4, C indicates the size of the entire document,
The assigned part is the part specified by the digitizer.
You. The SYNC signal 104 corresponds to the video interface shown in FIG.
Through the source 101 to the body processing device 3. In addition to this SYNC signal, the video interface 101
Outputs a FREEZE signal 102 and VCLK 103 to the video processing device 3.
You. Fig. 5 shows the timing chart of these control lines.
Show. That is, the FREEZE signal 102 and the SYNC signal 104 are operated.
Generated by pressing the start button of part 20,
As shown in the figure, the FREEZE signal 102
And SYNC signal 104 is generated by digitizer 16
Becomes "1" in a range corresponding to the designated area. However, if the number of copies is one or more,
After an error such as
When the copy button is pressed, the FREEZ signal 102 is Active
It does not become “1” and only SYNC104 and VCLK103
This is output to AIDS 101. In this embodiment, FIG.
By repeating the color process shown in
Color print is performed.
The colors are shown in the figure. Next, the operation of the present embodiment configured as described above
Flow chart of controller (CPU) shown in Fig. 11
This will be described. When the power is turned on, the controller 13
And read the operated key on the digitizer 16 (# 0
1). If there is an operated key, that key starts copying
It is determined whether the key is an instruction key (# 03), and a copy start is designated.
If it is the key to indicate, go to # 05, otherwise go to # 23
You. Here, first, keys other than the copy start key are turned on.
The following description will be made on the basis of # 23. In # 23, the indication of the area where the inlay synthesis should be performed is the third
It is determined whether or not it has been instructed by the switch 427 shown in the figure.
When instructed, the designated area is stored (# 2
5) When not instructed, the number of prints is specified.
It is determined whether or not it has been (# 27). As a result of the determination, the pudding
If the number of sheets has been set, the set number
Write to the register (# 29), if not set
Performs a process corresponding to another key input (# 31). Next, when the start of copying is instructed in # 03
explain. When instructed to start copying, first
It is determined whether or not an error flag is set (# 05).
If there is no error flag, the FREEZE signal
No. 102 is generated (# 07). This will be described later with reference to FIG.
Image data is written to the memory 303 in the video processing device
Be included. Next, the error flag is reset (# 0
9). In order to drive the scanner, the steps shown in FIG.
An instruction to start driving is given to the taping motor drive circuit 15.
As a result, the scanner starts to move, and occurs accordingly.
In synchronization with HSYNC and VCLK, each signal processing circuit shown in FIG.
Path, and each color component of the full color
It is output to the color conversion circuit 50 shown in FIG.
After being processed, it is supplied to the color printer 2. Color
Linter 2 is an image sent sequentially from the video processing unit 12
The drum 716, which will be described later, is rotated in response to the
Every time, the ITOP signal (image leading end signal) is returned to the unit 12.
In this embodiment, full-color printing is performed with four colors of Y, M, C, and Bk.
Is performed, and one color print is performed four times on the drum 716.
Rotation is required. Therefore, it is determined whether the ITOP signal has come four times in # 13.
(# 13) Until the ITOP signal comes four times, the printer side
To determine whether an error has occurred (# 14).
If not, return to # 13.If an error occurs,
-Set the flag once, stop driving the scanner,
It is determined whether or not the error has been canceled (# 21). #
One sheet when it is detected that ITOP has come four times in 13.
It is considered that the print has been completed.
The star is decremented (# 17), and its content becomes “0”
And returns to “0” when it becomes “0”.
If not, return to # 11 and continue the copy operation again
You. In the embodiment shown in the flowchart described above,
Indicates that color copying is in progress while multiple copy operations are being performed.
If an error has occurred due to a paper jam or other
(# 14), the flow returns to after the error is cleared
Unless the copy start key is turned on, the next copy operation
Is not done. Also, the error flag is set once in # 19.
Then return to the above and turn on the copy start key
Also, since the flow branches from # 05 to # 11, the flow in # 07
No release signal is generated, and a new image signal is
Writing can be prevented. Therefore, free to memory 303 before error occurs
Stored image data is stored in the memory 303.
It is possible to prevent other data from being written accidentally.
I can do it. VCLK103 synchronizes image data in video processing unit 12.
This signal is sent to the video processing device 3.
You. The video processing device 3 is a color image synchronized with VCLK103.
Signals 105, 106, 107 and EN signal 1 indicating the effective area of this signal
08 and to the video interface 101. This EN signal 1
When 08 is 0, the switching circuit 108 outputs the color from the logarithmic conversion circuit 86.
-Select the image signal, output it to the circuit at the subsequent stage, and
If the color image signal from 101 is
And outputs it to the subsequent circuit. The control signal for switching the switching circuit 100 is described above.
Although it is conceivable to use SYNC104 of
In addition, the E from the video processing device 3 without using the SYNC 104
Since the switching circuit 100 is switched using the N signal,
The following effects are obtained. That is, switching of the switching circuit 100 using the SYNC signal described above.
Is performed, the response of the video processing device 3 is slow.
Color image signal 105,1 from video interface 101
Switching of switching circuit 100 is performed before 06 and 107 are output
Therefore, when the switching circuit 100 is switched,
In other words, the black streak at the end of the image
However, according to this embodiment, the video interface
Switch the switching circuit 100 with the EN signal from AIDS 101
To prevent such black streaks from occurring.
I can do it. Note that the video processing device 3 uses a plurality of pixels to
Video processing when image processing such as azalea enhancement is performed
The response of the device 3 will be particularly slow. Next, a detailed circuit diagram of the switching circuit 108 is shown in FIG. This
In the circuit diagram of 113-118, data like 74LS157 (model name)
Selector, which has two input data and
Select one of the two input data according to the child S signal 112
I do. When the signal 112 is 0, the selector output OUT Y570, M57
1, Y for C572 line ₀ 120, M ₀ 121, C ₀ 122 is selected
When the number 112 is 1, Y'105, M'106, and C'107 are selected.
The selection signal 112 is a control signal other than the EN signal 108 described above.
It is controlled by signals 110 and 111 from the controller 13. By setting the signals 110 and 111, the switching circuit 100
Dedicated to image signal, Reflected document (document for copying), Image only, Inset
It has three functions for synthesis only. This function is shown in the table below.
You. That is, if the signals 110 and 111 are set to 0, it is specified by the digitizer 16.
The reflected document is trimmed by the specified area, and EN
Color correction, masking, gamma conversion, etc. according to the signal
Control is performed so as to be able to perform satisfactorily according to the properties of the image to be performed.
Also, this EN signal 108 is used for color correction and masking times to be described later.
Path 48 and a gamma conversion circuit 52. Next, returning to FIG. 2, the description will be continued. From switching circuit 110
Is input to the black extraction UCR circuit 47 to generate a black component signal.
And the black component signal is subtracted from the color signals 570, 571, 572
Is done. The color correction / masking circuit 48
Color separation filter and video processing device
The color correction of the color image signal of the device 3 is performed. Here, the operation of the color correction / masking circuit 48 will be described.
Will be described. For each color component image data Yi, Mi, Ci, Masking correction that calculates the primary expression of each color and performs color correction
Is well known. The color correction / masking circuit 48 in this embodiment is
To make the numerical value variable for the input image,
It can be set by the CPU via the data bus. In this embodiment, the first matrix coefficient M ₁ , The second matri
Matrix coefficient M _Two Connected to the controller 13
It can be set from the specified bus. M ₁ Coefficient of the color separation filter in the original scanning unit 11
For correction, M _Two Are assigned for correction of the video processing device 3.
Have been. These two coefficients M ₁ , M _Two Switching of the video interface
Select by EN signal 108, which is a signal from Ace 101
Is done. That is, the color image from the original scanning unit 11
M for image signal ₁ Coefficient from the video processing device 3
M for issue _Two Are selected, and color correction is performed. color
The output of the correction / masking circuit 48 is input to the color conversion circuit 50.
However, in the present embodiment, the function of the color conversion circuit 50 is
It is through. 52 is the color balance of the output image in this system,
A gamma conversion circuit for controlling color shading.
In general, data change by LUT (lookup table)
In other words, the LUT of the LUT is
Data is rewritten. In the RAM 52 of the present embodiment,
Yellow, Magenta, Cyan, Black, and Mono
And at least two types (FIGS. 6 (b) A and B).
Area A is a gamma characteristic of A, and area B is a gamma of B
It can be obtained as a single print with characteristics
It has such a configuration. Switching between the areas A and B is performed by the video interface 101.
This is performed by the EN signal 108 from. Also, the gamma conversion RAM 52 has a special feature for each color.
LCD panel on the scanning panel
Controller 13 in association with operation from touch panel keys
Rewritten from A gamma control circuit 53 and a 5-line buffer 54
The output signal of the conversion circuit 52 is scaled and further filtered.
Processing for edge enhancement and smoothing (smoothing) at 55
Is performed. The output of the filter circuit 55 is
The signal is input to the color printer 2 through the turface circuit 56.
You. As described above, in this system, the digitizer 16
From the video processing device 3 at the position specified by the
In addition to embedding the image information, the original scanning unit 11
Optimal color correction and gamma correction for each of the video processing devices 3
I do. Next, the configuration of the video processing device 3 will be described with reference to FIG.
Will be explained. In FIG. 7, reference numeral 300 denotes a composite signal such as an NTSC signal.
NTS that converts video signals input as signals into R, G, B signals
C decoder, 301 is RGB input a or NTSC decoder 300
A switching circuit for selecting any of the R, G, B signals,
The signals selected by the conversion circuit 301 are A / D separately for R, G, and B, respectively.
A / D converter for conversion, 303 is A / D conversion by A / D converter 302
Is the memory to which the written signal is written, at least RG
Each of B has a capacity for one frame. 304
Is edge-enhanced for signals read from memory 303.
Digital filter for smoothing or smoothing, 305
Using the signal filtered by the filter 304
An enlargement interpolation circuit 306 for enlarging an image
The interpolated RGB signals are converted to Y, M, C signals corresponding to the complementary colors.
It is a complementary color conversion table to be converted. 308 is a memory 303 for reading, writing, and refreshing.
A memory control circuit for controlling the operation and its address.
You. The control circuit 308 receives an input via the interface 307.
Memory 303 into the write state in response to the FREEZE signal
You. Note that the control circuit 308 has a TV-side V synchronization signal VDTV363, SY
Field discrimination signal FLDTV364 generated from NC circuit 321;
Output of switching circuit 309 Output of SYNC detection circuit 310, selection of magnification
The output of the switch 322 is input. The control circuit 308
This signal is triggered and generated by the SYNC signal described above.
To generate an area signal 366 indicating the effective area of the memory 303.
You. Clock C / TTV361 on TV side, H synchronization
The signal HDTV362, VCLK103 on the interface side,
SYNC 104 is input and SYNC detection circuit 310
Select VCLK103 and SYNC104 when it is detected
If it is detected that there is no SYNC, select CKTV or HDTV.
Select. 311 is for performing a logical operation between the area signal 366 and the SYNC 104
Gate, 312 in the filter 304 and the enlargement interpolation circuit 305
Delay times to compensate for delays due to data latches.
Roads, 313 to 315 are the filters performed by the filter 304 described above.
Delay circuit to compensate for the time delay due to
313 has a delay time of 5H and 314 has a delay of 7 pixels
Have time. 315 is an AND gate. 316-31
8 is based on the enlargement interpolation operation performed by the enlargement interpolation circuit 305 described above.
316 is a 1H
317 has a delay time of one pixel
ing. 318 is the data in the aforementioned complementary color conversion table 306.
This is a delay circuit to compensate for delay due to
You. Note that the delay circuits 312, 313, 314, 316, and 317 are described above.
DVCK367 and DVHS368. Selection sweets
If the enlargement ratio changes due to 322, DVCK, DVH
Since the period of S also changes, the delay time of each
Will change. 320 is the logic between the SYNC104 and the output EN1 of the delay circuit 318
An AND gate that outputs the product. Next, the operation of the embodiment configured as described above will be described.
I do. The video processing device 3 transmits the video data from the video processing unit 2.
The input RGB signal a or
Is decoded from the NTSC signal b by the NTSC decoder 300.
One of the obtained RGB signals 355 to 357 is selected by the switching circuit 301.
CKTV signal 361 obtained by the SYNC circuit 321
Digitized by the A / D converter 302 by
In this embodiment written to the B memory 303, the number of pixels of the memory is
640 × 480 pixels. Reading and writing of RGB memory 303
The timing of each of the read and refresh operations is controlled by a memory.
This is performed by the control circuit 308. SYNC signal from video processing unit 12
When the signal 104 is not input, the SYNC detection circuit 310 has no SYNC
The synchronization switching circuit 309 determines that the synchronization signal on the TV side, that is, CKTV3
Select 61 and HDTV362. S from video processing unit 12
When the YNC signal 104 is input, the synchronization switching circuit 309 outputs VCLK 103 and
And SYNC104, and the RGB memory 303 is the interface
Input at the timing of VCLK103 and SYNC104.
Will be issued. Enlargement of video image to be embedded in reflection original 999
The rate is fixed at 100%, 200%, and 400%.
Selected by switch 322. This signal is
Enters the control circuit 308 to control reading of the RGB memory 303.
You. In case of 200%, read the pixel of the same line twice
Then, in the case of 400%, pixels on the same line are read four times
You. RGB memory at 100%, 200% and 400% magnification
Synchronization of 303, filter circuit 304, expansion interpolation circuit 305
Is generated by the memory control circuit 308. DVCK365, DVHS
This is done by synchronizing to the 366. The signal read from the RGB memory 303 is a filter circuit
304 using a 5 × 7 pixel matrix operation
Rutta is applied and edge enhancement or smoothing is performed.
And the magnification interpolation circuit 305
Interpolation is performed, and the R, G, B signals are
Signals are converted to C107, M106, and Y104 signals, respectively.
-Video processing unit through the interface circuit 307
Handed to 12 In this embodiment, the data is read from the RGB memory 303.
RGB data is filtered by the filter circuit 304 and the enlargement interpolation circuit.
305, a so-called pipeline passing through the complementary color conversion table 306
The data is processed by the structure,
There is a time delay between input and output
I will. That is, as described above, a plurality of video processing devices 3 are provided.
After the image output is instructed to perform the process of
A certain amount of time is required until the data is output. This delay
In this embodiment for adjusting the time, the EN signal 108 is
It is made to generate. Delay circuits 312,314,317,318,
With line-direction delay circuits 313,315 and gates 315,318
The same as the delay time in each circuit 303, 304, 305, 306
Delay, and the C107, M106, and Y105 signals
The EN signal 108 outputs a valid signal according to the output period.
Power. In the smell of this embodiment, the video image mesh ratio (1
640 x 480 pixels to make the aspect ratio of pixels 1: 1
I have. And this is 100% or 200% or 400%
Output pixel data to enlarge at any ratio of
doing. At this time, the S input to the interface 307
A signal whose YNC signal 104 is equal to the size of the enlarged image data
There is no guarantee that it will be entered as a number. For this reason, RGB
The memory control circuit 308 that controls the memory 303
The size of the image to be read, 640 x 480
Raw (or 1280 x 960 pixels at 200% magnification, 2560 at 400% magnification)
An image area signal 366 indicating (× 1920 pixels) is output. Soshi
Lever region signal 366 and SYNC signal 104 are gated by gate 311
Theoretical value and simultaneously delayed by each delay circuit
Output ENI signal 371 (output of delay circuit 319) and SYNC signal 104
Are ANDed by the gate 320. This allows SYN
Output of the image of the C signal area, that is, the area where
When it is larger than the force area, EN is enabled by the image area signal 366.
The area of the signal 108 is limited, while the area of the SYNC signal 104 is small.
At the time, even if there is still image area, SYNC is forcibly
It is limited to the signal area. Regarding these operations, the eighth
(A) and (b) of FIG. (A) in FIG.
When the time width of the SYNC signal is larger than that of the
Should fit rather than the size of the image to fit
If the area is larger, (b) will fit in the opposite way
If the area to be larger than the image to be fitted
SYNC signal 104, area signal 366, ENo signal 370, EN
A signal 108 and image data 105 to 107 are shown. The time indicated as D in FIGS. 8 (a) and (b)
FIG. 7 shows delays by delay means 212 to 318.
Time. In the filter circuit 304, as described above, 5 lines × 7 pixels
A plain window is provided and the value of each pixel in this window is
This constitutes a filter. The active screen area is
The area is reduced by one to several lines, but this is almost always a problem.
There is no title. Delay circuits 316 and 317 for the expansion interpolation circuit 305 and
And the gate 318. Next, the image is output after the image synthesis is performed using FIG.
This will be described on a print image. By digitizer 16
Specify the area where the video image is to be fitted using two points a and b.
You. According to this designated area, the SYNC signal 104
The data is output from the processing unit 12 to the video processing device 3. Bi
In the video processing device 3, the video image C10
7, M106, Y105 Output each signal to video processing unit 12.
You. At this time, as shown in FIG.
Indicates the effective area of the video image when the area is large
The video processing device 3 outputs an EN signal 108, and the video processing unit 3
In the nit 12, a video image is formed only in the area of the EN signal 108.
The area outside is fitted on the color reader 1
And print the original 999. Conversely, as shown in FIG. 9 (b)
Thus, the area ab specified by the digitizer 16 is a video image.
When smaller than the effective area of the image, the SYNC signal 104
The area to be fitted and synthesized is defined. This result wasps
The video image is embedded and synthesized in the
You. The RGB memory 303 of the present embodiment is, for example, a D-RAM.
Since the memory is used, keep the stored contents
Therefore, an operation called refresh is required. Normal
When the memory contents are retained or when the FREEZE signal 102
Video signal (RGB or NTSC signal)
Retains data when writing to or writing to the 303
When refreshing, according to the timing of the HDTV signal 362.
Create a SH signal, and send a SYNC signal 10 from the video processing unit 12.
4 is input and the memory is being read, the SYNC signal
No signal for refresh is created according to the timing of
ing. At this time, the cycle of HDTV signal 362 and SYNC signal 104 is
Because of the great difference (in this embodiment, the HDTV signal 362
Cycle and the cycle of the SYNC signal 104 are different about 4 times)
Each time, the number of refreshes per time is changed. Next, the twelfth configuration of the memory control circuit 308 described above will be described.
This will be described in detail with reference to the drawings. In FIG. 12, SCK (SLECTFD CLOCK) SHS (SLECTED H
ORIZONTAL SIGNAL) is switched by the switching circuit 309 described above.
This is a signal input to the memory control circuit 308. 370
Corresponds to the setting of the enlargement ratio setting switch 322 shown in FIG.
The frequency divider that divides the SCK changes the frequency division ratio.
Similarly, this is a frequency divider whose frequency division ratio for dividing the SHS changes. Three
74 is a quaternary counter that counts the output of the frequency divider 370, 376
Is a counter for counting addresses in the main scanning direction, 378
Is a counter that counts addresses in the sub-scanning direction, 380
Is the ratio comparing the output of the counter 376 to the exit of the domain value 382
The comparator 384 compares the output of the counter 378 with the output of the area value 386.
It is a comparator to compare. 382 and 386 are image memory 303 respectively
The value corresponding to the number of pixels in the horizontal and vertical directions is preset
Have been. Therefore, either output of comparator 380 or 384 is L level
, The output of the gate 388 is also at L level and the area
The signal also becomes L level. 390 is the output of 2 bits of the quaternary counter 374.
Generate the signals of (B), (C) and (D) shown in (a)
It is a logic circuit. (B) shows RAS (Row Address Str)
obe), (C) is CAS (Colum Address Strobe), (D)
Is a signal for switching a selector 391 described later. 391
Is the output count of the counter 376 in accordance with the aforementioned (D) signal.
Switch the output of any of the
The selector 392 outputs the signals (B) and (C) described above.
No. or for refreshment (C) shown in FIG. 13 (b),
(D) A selector that outputs a signal to the memory 303. 393
Outputs the SHS signal from the switching circuit 309 via the inverter 397.
This is a D-FF to be taken in, and its output is
Connected to enable terminal. 395 is the switching circuit 309
A quaternary counter that counts these SCK signals.
FIG. 13B shows the 2-bit output of the counter 395.
This is a logic circuit for generating the signals (C) and (D).
396 is enabled according to the output of the quaternary counter 395
Counter, SYNC detected by SYNC detection circuit 310
Is detected, “32” is set and SYNC is disabled.
Is detected, “8” is set and the SCK signal
Is a counter that counts down according to the
The counter output is connected to the clear terminal of D-FF393.
AND gate 398,400 and inverter 399 are controllers
The write / read signal / W from 13 and shown in FIG.
JK-FF368 is enabled according to the FLD signal from the SYNC circuit 321.
Switch whether or not to use 401 is the output Q of JK-FF368
Or take OR of / W and enable counter 378
This is an OR gate input to the terminal. The operation of the memory control circuit 308 configured as above
Will be described. First, when a write instruction is given from the controller 13,
The case will be described. This signal is sent from controller 13
/ W signal is at H level and the counter 378 is enabled.
And the output Q of JK-FF368 becomes FLD signal level.
Decide according to JK-FF368 and counter 378
The vertical address of the memory 308 is shown, and JK-FF368
The output of the least significant bit of the vertical address, counter 378
The other bits are assigned to the output of
You. Therefore, the FLD signal is at L level, that is, an odd field.
Output, the output Q of JK-FF is fixed at H level,
Only odd-numbered addresses are output as direct addresses.
It is. Conversely, if the FLD signal is at H level,
In this case, the output Q of JK-FF368 is fixed at L level,
Only the even-numbered addresses are output as vertical addresses.
It is. On the other hand, frequency divider 370, quaternary counter 374, counter 376
Generates a horizontal address. The horizontal and vertical addresses generated in this way are stored in the logic circuit 39.
Select by the selector 391 according to the output of 0
Output as readdress. Horizontal generated this way
RAS and CAS are synchronized with the vertical address as shown in Fig. 13 (a).
And writing is performed. In this case, select
392 outputs the signal on the logic 390 side to the memory 303.
You. Next, a signal for reading is generated from the controller 13.
Will be described. In such a case, the / W signal becomes L level, and JK-FF36
8 output does not depend on FLD signal, JK-FF368 and counter 378
Constitutes one counter. Therefore, the book
Unlike when writing, the vertical address is incremented by "1".
Is mentioned. When reading, the SHS signal falls and the read
During the blanking period, the output of D-FF393,
▲ ▼ / refresh signal is inverted to H level and
The moly 303 is in a refreshing state. In this case selector 3
92 is a RAS built in the logic circuit 394 for refreshing
γ and CASγ (shown in FIG. 13 (b)) are output to the memory 303.
It becomes like. This will automatically refresh the memory 303
Perform a shuffle operation. Also, in this case, the counter 396 receives the signal from the SYNC detection circuit 310.
The value corresponding to the signal is set. For example,
If the SYNC detection circuit detects that SYNC is present,
When it is detected that “32” does not exist, “8” is set.
It is. This is because the HDTV signal 362 and the SYNC signal 104
Due to the greatly different periods, the refresh operation
This is because there is a need to change the imaging. At the time of reading, the frequency division ratio of the frequency dividers 370 and 372 is
The value is set according to the enlargement magnification.
The period of the pulses output to the counters 376 and 378 is increased. Ma
Area specified value from the digitizer
From the gate 388 according to the comparison of the output from the counters 376 and 378
An area signal 366 is output. Next, it was processed by the video processing unit 12 as described above.
First, the configuration of the color printer 2 for printing image signals will be described.
This will be described with reference to the drawings. In FIG. 1, reference numeral 711 is a scyana.
Yes, converts image signals from color reader 1 to optical signals
Laser output section, polyhedral (eg octahedral) polygon
Mirror 712, a motor that rotates this mirror 712 (not shown)
Shown) and an f / θ lens (imaging lens) 713 and the like. 7
14 is a reflection mirror that changes the optical path of laser light, and 715 is photosensitive
It is a drum. The laser light emitted from the laser output section is
The light is reflected by the Ligon mirror 712, and the lens 713 and the mirror 71
4 scans the surface of the photosensitive drum 715 linearly
And a latent image corresponding to the original image is formed. Also, 717 is a primary charger, 718 is an overall exposure lamp, 723
Is a cleaner section for collecting the residual toner not transferred,
724 is a pre-transfer charger, and these members are the photosensitive drum 7
It is located around 15. 726 is laser exposed
Developing the electrostatic latent image formed on the surface of the photosensitive drum 715
731Y (for yellow), 731M
(For magenta), 731C (for cyan), 731Bk for photosensitive drum 7
730Y, 730M, 73
0C, 730Bk is a toner hopper that holds spare toner,
Reference numeral 732 denotes a screw for transferring the developer.
Sleeve 731Y ~ 731Bk, toner hopper 730Y ~ 730Bk
And screw 732 make up the developing unit 726
These members are arranged around the rotation axis P of the developing unit.
It is arranged. For example, forming a yellow toner image
The yellow toner development at the position shown in
When forming a toner image on the
Rotate around the axis P in the figure and move it to the position
The developing sleeve 731M in the magenta developing device is provided.
The development of cyan and black operates similarly. Reference numeral 716 denotes a toner image formed on the photosensitive drum 715.
719 is a transfer drum for transferring to paper, and 719 is a transfer drum 716.
Actuator plate for detecting the moving position of
The proximity of this actuator plate 719 causes the transfer
Detects that the ram 716 has moved to the home position
Position sensor, 725 is transfer drum cleaner, 727
Is a paper holding roller, 728 is a static eliminator, and 729 is a transfer charger.
Yes, these members 719, 720, 725, 727, 729
It is located around 16. On the other hand, 735 and 736 are paper cassettes for storing paper (sheets).
737, 738 are for feeding paper from cassettes 735, 736.
Paper rollers, 739, 740, 741 timing for paper feed and transport
Timing roller that feeds paper through these
The conveyed paper is guided by the paper guide 749 and the leading end is described later.
Wrapping around the transfer drum 716 while being carried by the gripper,
The process proceeds to the image forming process. Reference numeral 550 denotes a drum rotation motor which rotates with the photosensitive drum 715.
The photo drum 716 is rotated synchronously. 750 completes image formation process
Later, the peeling claw that removes the paper from the transfer drum 716, 742
Conveyor belt for transporting removed paper, 743 for transport
Image fixing unit that fixes paper conveyed by belt 742
The image fixing unit 743 includes a pair of heat pressure rollers 744 and 74.
With 5. According to the above configuration, first, the photosensitive drum 71 is
5, a Y latent image is formed on the developing unit 731Y.
And then transferred to the paper on the transfer drum.
Then, the developing unit 726 is rotated about the axis P in the figure.
You. Next, an M latent image is formed on the photosensitive drum by laser light.
Then, the same operation is performed. This operation is applied to C and Bk.
The same procedure is repeated, and when the image forming process is completed,
The paper is peeled by the release claw 750 and set by the image fixing unit 743.
Then, the printing of the color image is completed. In the embodiment described above, the refresh is performed at a predetermined cycle.
R, G, and B memories 303 are required to operate, and
A first synchronizing signal for generating a synchronization signal for a flash operation.
The synchronization system is a SYNC circuit 321, which is asynchronous with the first synchronization system.
System control pallet shown in Fig. 2 for the synchronous system 2
The first synchronizing system and the second synchronizing system
Control is performed when switching is performed by the switching circuit 309 shown in FIG.
Means are composed of counters 396,395 and D-FF393. The present invention is not limited to this.
Switch the cycle of the synchronization signal itself when switching
You may be able to. <Effect of the Invention> As described above, according to the present invention, the refresh operation is performed.
Synchronous reading and writing for image memory that requires
When switching the synchronization system, furthermore, the image data from the memory
During the read operation, the memory refresh operation
Operation is performed reliably, and the image information stored in the memory is destroyed.
Read and write image signals stably without
It can be carried out.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a schematic internal configuration of a color image forming system to which the present invention is applied, and FIG. 2 is a diagram showing a configuration of a document scanning unit 11 and a video processing unit 12 shown in FIG. FIG. 3 is an external view of the digitizer 16 shown in FIG. 1, FIG. 4 is a diagram showing an inset area, and FIG. 5 is a FREEZE signal 102 output from the video interface 101 to the video processing device 3. , VCLK103, SYNC signal 104
FIG. 6 is a diagram showing two types of gamma characteristics of the RAM 52 shown in FIG. 2, FIG. 7 is a block diagram showing a configuration of the video processing device 3 shown in FIG. 1, and FIG. (A) and (b) show the video processing device 3 shown in FIG.
FIGS. 9 (a) and 9 (b) are diagrams for explaining a print image output after the screen composition is performed by the apparatus of the present embodiment, and FIG. 10 is a timing chart for explaining the operation of FIG. FIG. 11 is a block diagram showing the internal configuration of the switching circuit shown in FIG. 11, FIG. 11 is a timing chart for explaining the operation of the controller 13 shown in FIG. 1, and FIG. 12 is a block diagram of the memory control circuit 308 shown in FIG. 13 (a) and 13 (b) are block diagrams showing the configuration, and FIGS. 13 (a) and 13 (b) show the memory control circuit 30 shown in FIG.
8 is a timing chart for explaining the operation of FIG. 1 ... color reader, 2 ... color printer, 13 ... controller.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasumichi Suzuki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) References JP-A-60-107796 (JP, A) JP-A-53 -109445 (JP, A) JP-A-58-159292 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 11/40-11/409

Claims (1)

(57) [Claims] A storage device using an image memory that requires a refresh operation in a predetermined cycle, comprising: a write synchronization system that generates a synchronization signal for a refresh operation to the image memory in synchronization with an image signal to be written to the image memory; When reading an image signal from the image memory at a given timing, a read synchronous system for generating a synchronous signal for a refresh operation to the memory while the read is being performed, the write synchronous system, and the read synchronous system A switching device for preventing a refresh operation from being performed continuously for a predetermined period or more in the image memory.