JPH01102659A - Ram write/read arbitrating system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] When a microcomputer controls the operation of a system by writing data to a RAM, data can be written to/read from the RAM without affecting the system in operation. Regarding the RAM write/read arbitration method, with the aim of reducing the scale of the circuit that implements the RAM write/read arbitration method, we have developed a RAM that writes and reads system control data corresponding to the input drive address, and a a first data holding memory that temporarily stores read data using a first clock; a second data holding memory that temporarily stores data to be written to the RAM or data read from the RAM; and a second data holding memory that temporarily stores a set address. an address holding memory, a comparing means for comparing the set address and the drive address, and when the first clock, a second clock generated from the first clock, and the output of the comparing means reach a predetermined state; write/read arbitration means for sending a signal to the RAM and a second data holding memory, and when a match output due to address matching is sent from the comparing means, data corresponding to the drive address at the time of sending the match output; is read from the RAM and held in the first data holding memory, and then the data held in the second data holding memory is written to the RAM using a signal from the write/read arbitration means; Alternatively, data corresponding to the drive address at the time of sending out the coincidence output is read from the RAM and written into the second data holding memory.

[Industrial application field]

Related to a RAM write/read arbitration method that allows data to be written/read from RAM without affecting the system in operation when a microcomputer controls system operation by writing data to RAM. It is.

For example, data 1. A large number of data such as data 2... have been written, and the system is in time slot 1.
The system may perform different operations depending on the time slot, such as controlling the system operation using data 1 in time slot 2 and controlling system operation using data 2 in time slot 2.

Of the data currently written to RAM, 9, for example, data 2.
If it is necessary to control the system by rewriting the data 2' to data 2', this must be done while the system is operating, but at this time, it is necessary to simplify the circuit that performs the write/read arbitration operation.

[Conventional technology]

FIG. 6 is a block diagram of a conventional example, and FIG. 7 is an explanatory diagram of the operation of FIG. 6. Below is address A of RAM 6.

The data D written to the data 0. 6 will be explained with reference to FIG. 7.

In addition, CLK-1 in Fig. 6 is the system clock, CL
K-2 is a clock whose phase is delayed by 3, for example, 2 periods, with respect to the system clock.

In addition, there is a flip-flop for holding addresses (see below).

It is assumed that address A@ is held in FF (abbreviated as FF) 3, and rewrite data 0' is written in data holding FF 5. Furthermore, since the RAM stores data that controls the operation of the system in each time-divided time slot as described above, what about this RAM? IAP-RAM
First, the address from the system counter (not shown)
5 is added to the MAP-RAM 6 through the selector 4, and the data Ds is read from there.

Since it is written to FF7 at CLK-2, the system operation is controlled by data D5 of FF7.

That is, since the arbitration timing determination circuit 1 determines when writing is completed and drives the selector 4 to select the address holding FPa side as shown by the dotted line, the address ^8 from this FF3 and the write time determination circuit The write enable signal from 2 and the data DIlf written to FF5 are added to the MAP-RAM 6, and the data DIlf is added to the MAP-RAM 6.
As shown in the figure, data D at address A8 is rewritten to data D8g.

When the arbitration timing determination circuit 1 determines that the rewriting is complete, the selector 4 is returned to its original state and the address A6 is set to MAP-R.
Since it is added to AM 6, data D6 is read from address ^6, and the system operates based on this data.

[Problem that the invention seeks to solve]

Here, arbitration timing determination circuit 1, write timing determination circuit 2
．． The selector 4 is required, but since it is necessary to switch addresses, there is a problem that the circuit scale increases when there are many addresses.

[Means for solving problems]

The above problems are solved by the RAM write/read arbitration system shown in FIG.

Here, 12 is RAh for writing and reading out the system control data corresponding to the input drive address;
13 is a first data holding memory that temporarily stores data read from the RAM using the first clock, and 13 is a second data holding memory that temporarily stores data written to the RAM or data read from the RAM. be.

Further, 10 is an address holding memory for temporarily storing a set address, 9 is a comparing means for comparing the set address and the driving address, and 8 is a comparison means for comparing the set address and the drive address, and 8 is a second clock generated from the first clock. write/read arbitration means that sends a signal to the RAM and the second data holding memory when the clock of the memory and the output of the comparison means reach a predetermined state.

Then, by providing these, when a match output due to address match is sent from the comparing means, data corresponding to the drive address at the time of sending out the match output is read from the RAH,
After being held in the first data holding memory, the data held in the second data holding memory is written to the RAM using a signal from the write/read arbitration means 9 or the coincidence output is sent. The data corresponding to the drive address at the time is read from the RAM and written into the second data holding memory.

[Effect]

When the present invention is reading data written to RAM and controlling the system, in order to write data to RAM without affecting the operation of the system in operation, the write address (hereinafter referred to as , a predetermined address), write data is written in advance into the second data holding memory 13 and held therein.

Then, the comparison means 9 compares the drive address and the set address, and when they match, a matching output is sent to the write/read arbitration means 8, and data is read from the RAM 12 using the first clock. This data is temporarily held in the first data holding memory and is used to control the operation of the system.

On the other hand, when the first clock, the second clock generated from the first clock, and the coincidence output from the write/read arbitration means 8 reach a predetermined state, an enable signal is sent to the RAM 12 and the second data holding memory 13. , the data temporarily held in the second data holding memory 13 is written to the RAM.

The system is controlled by the data written at the next drive address.

Furthermore, when reading data from the RAM, an enable signal is applied to the second data holding memory 13 by the coincidence output from the write/read arbitration means 8, so that the RAM
12 data are written into the second data holding memory 13.

In these cases, a comparator is used instead of the selector used in the conventional example to switch addresses.

Even if the number of addresses increases, the circuit scale becomes smaller.

Furthermore, when multiple RAMs are used, the circuit size is reduced by sharing a comparator, a second data holding memory, etc.

〔Example〕

FIG. 2 is a block diagram for implementing the present invention, FIG. 3 is an explanatory diagram of the operation of FIG. 2, FIG. An explanatory diagram of the operation is shown. Further, the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG.

Here, the NAND gates 81.82 are the constituent parts of the write/read arbitration means 8, and the FFs 91.93. Comparators 92°94 and inverters 95 to 97 are components of the comparison means 9, RAM address holding FF10I is a component of the address holding memory 10, and data holding FFs 131.13
2 indicates a component of the second data holding memory 13. Note that the same reference numerals indicate the same objects throughout the figures.

The operation shown in FIG. 2 will be described below with reference to FIG. 3 when writing/reading data at address A3. Here, as shown in Figure 3, CLK-2 is C
It is assumed that the MAP-RAM drive address is delayed by % CLK from LK-1 and is synchronized with the falling edge of CLK-2. still,
*Q in the sentence indicates the inverted level of Q.

(1) In case of write operation (see Fig. 3(a)).

First, the CPU writes data D3 to be rewritten to the data holding FF 132, and then writes the data D3 to be rewritten to the data holding FF 132.
Address A is set to 01 and latched.

Next, when a negative logic pulse is applied to the preset *PR terminal of FF 14, FF-1
The Q terminal of FF 91 becomes H, and this H is applied to the D terminal of FF 91, but the inverter 97 turns the main of FF 91 at the falling point C of CLK-2 as shown in Fig. 3(a)-■. Q
The terminal becomes L, which is added to the *G terminal of the comparator 92, and the comparator starts a comparison operation.

That is, MAP-RA? of FIG. 3(a)-■? l When the drive address is other than A3 (e.g. +AI+Ax...)
The output of the comparator 92 is H, and the MAP-RAM
121 is the address A+, A as shown in Figure 3(a)-■
Outputs data DI, 02 corresponding to
I and is used to control the system.

Note that the intersecting diagonal lines in each data are parts where the data is undefined, and this depends on the access time of RAM2 and takes about 1
The time is about 00 to 150 ns (Fig. 3 (al-■
reference).

When the drive address becomes A3, the output of the comparator 92 becomes L as shown on the right side of FIG. 3 (al-■), indicating that the two addresses match.
As shown on the right side of -■, data D:l corresponding to address A is read out and written to the FF 111, and is used to control the system.

After that, when the output of the H1 comparator becomes L, CLK-1 and CIJ-2 are output from the NAND gate 81 as shown in FIG.
As shown in ■L MAP-RAM 1210) *H
E terminal and FF 132 (7) output enable (
01E) added to the terminal.

Therefore, MAP-RAM is writable, FF 132
is ready for output, so the data D code in the FF shown in FIG. 3(a)-■ is written to address A of the MAP-RAM 121 (03' in FIG. 3(a)-■). reference).

Then, data D3' is read out at the next address A8 and used for system control.

In addition, the CPU knows that the write arbitration operation has started when the Q terminal becomes H after applying a preset to the FF 14 as described above, and transfers data from the NAND gate 81 to the MAP-RAM.
Write enable (*-E
) signal causes the Q terminal of FF 14 to become L, and from this, CP[I knows that the write has been completed.

In this state, the CPU can perform the next write operation.

(2) In the case of read operation (see Figure 3)).

Similarly to the process in section (1), CPU gives a negative logic pulse to the preset PR terminal of FF 16, as shown in Fig. 3(b).
- As shown in 〇, the Q terminal of FF 16 becomes H, and this H
is added to the D terminal of FF 93, and the CLK
At the falling edge of -2, the main Q terminal of FF 93 becomes H.

The comparator 94 starts the operation backward, and the address holding FF 10
When the address A3 from 1 and the MAP-RAM drive address match, the comparator 94 outputs L as shown in FIG.
It is added to D gate 82.

The clocks shown in Figure 3(b)-■ and ■ are also added here, and when the three inputs are H, the write enable pulse for FF 131 is activated as shown in Figure 3(b)-■. 131, so MAP-RAM
Data D from is written. Furthermore, MAP-RAM
3 () corresponding to the MAP-RAM drive address.
b) - The data is read out as shown in [phase] and the FF 11
Added to 1.

Further, the three-state gate circuit 15 and the FF 16 are used for the CPU to know the start and end of the read arbitration operation, as described above.

Next, FIG. 4 shows a block diagram of another embodiment, and FIG. 5 shows a block diagram of still another embodiment.

FIG. 4 shows that when multiple MAP-RAMs 121, 122, 123, etc. are provided instead of one as shown in FIG. .113... and MAP-R
FFs 131, 132, etc. are required to store data for rewriting AM data or read data.

Here, the comparator 92 or 94 compares the address set in the RAM address holding FF 101 with the i^P-
Although we are looking for a match with the RAM drive address, the RAM identification address holding FF 102. Decoder 103.104
゜AND game 05.106 is provided to decode the output of the RAM identification address holding FF 102 when the addresses match, and output which MAP-RAM has been selected.

Incidentally, when a plurality of MAP-RAMs are used, it is not necessary to provide a plurality of block diagrams shown in FIG. 2, so the circuit scale becomes smaller.

In FIG. 5, a NOR gate 96 is used to rewrite the block in FIG. 4 with a MAP-RAM drive address, or to unify the comparator 95 for detecting a match between read addresses. It was realized.

Furthermore, as shown in FIG. 4, data holding FFs 131 to 136 for holding rewriting data or reading data were provided corresponding to the MAP-RAM, but each MAP-R
Two-way transceiver 137.138°1 compatible with AM
39, 139' are provided. This transceiver normally allows data to flow in the direction of A-8, but allows data to flow in the direction of B-A only when a write enable signal is applied.

As a result, it is only necessary to turn off two FFs, the FF 132 for holding rewritten data and the FF 131 for holding read data, thereby reducing the size of one circuit.

That is, MAP-RAM write/read arbitration can be performed using a small-scale circuit.

〔Effect of the invention〕

As described above in detail, the present invention has the advantage that RAM write/read arbitration can be performed using a small-scale circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram for implementing the present invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Fig. 4 is a diagram of another embodiment of Fig. 2. FIG. 5 is a block diagram of still another embodiment of FIG. 2, FIG. 6 is a block diagram of a conventional example, and FIG. 7 is an explanatory diagram of the operation of FIG. 6. Ki Oake 8 Torase IroT Konno's Brotsu Sword Illustration

Claims (1)

[Claims] 1. When controlling the operation of a system with a computer, a RAM (12) in which system control data is written and read in accordance with an input drive address; a first data holding memory (11) that temporarily stores data written in the RAM or data read from the RAM; and a second data holding memory (13) that temporarily stores a setting address. Address holding memory (10
), a comparing means (9) for comparing the set address and the drive address, the first clock, a second clock generated from the first clock, and the output of the comparing means are in a predetermined state. write/read arbitration means (8) that sends a signal to the RAM and the second data holding memory at the same time; The data corresponding to is read from the RAM and held in the first data holding memory (11), and then stored in the second data holding memory using the signal from the write/read arbitration means (8). A RAM write/write device characterized in that held data is written to the RAM, or data corresponding to the drive address at the time of sending out the coincidence output is read from the RAM and written to the second data holding memory. Read arbitration method. 2. R the address holding memory to the address holding memory
2. A RAM write/read arbitration system according to claim 1, characterized in that an address holding memory for AM identification and a decoder are added. 3. RAM writing/reading according to claim 1, characterized in that the second data holding memory has a structure in which the same number of bidirectional transceivers as the RAM are added to the second data holding memory. Mediation method. 4. The RAM write/read arbitration system according to claim 1, wherein the comparing means has a configuration in which an OR circuit is added to a common comparator.