JPH10302475A - Memory control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-port memory which can execute read-after-write fast by supplying a read precharge clock and a write precharge clock to the memory with half cycle staggered. SOLUTION: Write pre-charge is made while the system clock 4 is not asserted. When the clock is asserted, the write word line in the memory cell array 60 is driven through the write word driver 51 and the data given to the input data line 61 is written into each cell of the designated address. On the other hand, concurrently read precharge is made while the system clock is asserted. When the system clock 14 comes to be asserted no longer, the read word line inside the memory cell array 60 is driven through the word driver 52 and data is read out from each cell in the designated address to be outputted to the output data line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory control device, and more particularly to a memory control device for controlling a multiport RAM having a read-after-write function.

[0002]

2. Description of the Related Art In a multiport RAM, a plurality of ports share a memory cell and have a plurality of word lines and data lines corresponding to the number of access ports, so that writing and reading of a plurality of words can be performed simultaneously. You can do it. As the processing capacity of processors has been improved, the number of required ports has increased, and high-speed processing has been required. In addition, a so-called read-after-write function for reading data written in a memory cell in the same cycle is required.

Conventionally, in this type of technology, the read word line must be driven until the write is completed, which is an obstacle to high-speed operation. Hereinafter, this will be described with reference to the drawings.

Referring to FIG. 5, a conventional memory control device includes a write address flip-flop 91 for holding a write address 1, a write address decoder 31 for decoding a write address 2, and a read address flip-flop for holding a read address 2. A read address decoder 32 for decoding a read address;
A write enable flip-flop 21 for holding the write enable signal 3, a delay gate 99 for delaying the system clock 4, a write word driver 51 for driving the write word line 53, and a read word line 5
4 for driving the read word driver 4.

Referring to FIGS. 5 and 6, the conventional memory controller uses an inverted output of delay gate 99 as precharge signal 46. And
The output of the delay gate 99 is used as the read word driver drive signal 44. The logical product of the input / output of the delay gate 99 and the output of the write enable flip-flop 21 is used as the write word driver drive signal line (write pulse) 43 to ensure the read time after writing. I have.

[0006]

In the above-mentioned prior art,
One cycle must be made sufficiently large to secure the read time after writing. That is, if the cells involved in writing and the cells involved in reading are different, it is not always necessary to secure the read time after writing, but it is necessary to design in consideration of the worst case unless the cells are guaranteed to be different. There is.

On the other hand, by providing a comparison circuit for comparing the write address with the read address outside the memory, it is ensured that the cell to be written is different from the cell to be read, and the read after write is guaranteed. Time can be eliminated. However, in this case, the above-described comparison circuit and a circuit for bypassing the write data to the output side when the coincidence is detected are required, and the circuit configuration becomes complicated as a whole.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-port memory that performs high-speed read-after-write in view of the above problems.

[0009]

In order to solve the above-mentioned problems, a memory control device of the present invention supplies a read precharge clock and a write precharge clock to a memory with a shift therebetween.

According to another aspect of the present invention, a memory control device includes: a read timing generation circuit for supplying a read precharge clock to a memory based on a system clock; And a write timing generation circuit that supplies the data to the write timing generator.

Another memory control device of the present invention further includes a read address decoder for decoding a read address, and a read word driver for driving a read word line of the memory. An inverted signal of the charge clock is generated as a read clock, and the read word driver drives the read word line of the memory at the timing of the read clock generated by the read timing generation circuit in accordance with the result of decoding by the read address decoder.

Another memory control device of the present invention further includes a write address decoder for decoding a write address, and a write word driver for driving a write word line of the memory, wherein the write timing generation circuit includes a write enable signal. And the read precharge clock as a write pulse, and the write word driver generates the write word of the memory according to the result of decoding by the write address decoder at the timing of the write pulse generated by the write timing generation circuit. Drive line.

Another memory control device according to the present invention further includes a write address decoder for decoding a write address, and a write word driver for driving a write word line of the memory, wherein the write timing generation circuit includes a write enable signal. And the read precharge clock as a write pulse, and the write word driver generates the write word of the memory according to the result of decoding by the write address decoder at the timing of the write pulse generated by the write timing generation circuit. Drive line.

Another memory control device of the present invention outputs a read address as it is while the system clock is asserted, and reads a read address immediately before the system clock is no longer asserted while the system clock is not asserted. And a read address latch for holding and outputting the read address. The read address decoder decodes a read address output from the read address latch.

Another memory controller of the present invention outputs a write address as it is while the system clock is not asserted, and writes a write address immediately before the system clock is asserted while the system clock is asserted. And a write address latch for holding and outputting the write address. The write address decoder decodes a write address output from the write address latch.

Another memory control device of the present invention further includes a write enable flip-flop that holds and outputs a write enable signal at the edge of the system clock, and wherein the write timing generation circuit outputs the write enable signal output from the write enable flip-flop. A logical product of a write enable signal and the read precharge clock is generated as a write pulse.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the memory control device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an embodiment of the present invention comprises a write address latch 11 for holding a write address 1, a write address decoder 31 for decoding a write address 2, and a read address flip-flop for holding a read address 2. Drive 12, a read address decoder 32 for decoding a read address, a write enable flip-flop 21 for holding a write enable signal 3, a write word driver 51 for driving a write word line 53, and a read word line 54. And a read word driver 52 to be used. Further, a write timing generation circuit 41 for generating a write timing
And a read timing generation circuit 42 for generating a read timing.

The memory cell array 60 performs write precharge and read precharge at the timing when the write precharge signal line 45 and the read precharge signal line 46 are asserted, respectively. The memory cell array 60 performs the write operation and the read operation at the timing when the write word line 53 and the read word line 54 are asserted, respectively. The data received via the data input line 61 is written to each cell at the designated address, and the value of each cell at the designated address is output to the data output line 62 as a read address.

The write address latch 11 holds the write address 1 while the system clock 4 is not asserted.
While the system clock 4 is asserted, the write address 1 input immediately before is held and output. On the other hand, the read address latch 12 passes the read address 2 as it is while the system clock 4 is asserted, and holds and outputs the immediately preceding read address 2 while the system clock 4 is not asserted. . The write address output from the write address latch 11 is decoded by a write address decoder 31, and the read address output from the read address latch 12 is decoded by a read address decoder 32. The reason why the write address latch 11 and the read address latch 12 do not employ flip-flops is that the write address decoder 31 and the read address decoder 32 perform decoding at an early stage. Therefore, although a latch structure is desirable, adoption of a flip-flop structure is not excluded.

Write enable flip-flop 21
Holds and outputs the write enable signal 3 input immediately before the rising edge of the system clock 4.

Referring to FIG. 2, the write timing generation circuit 41 generates an AND of the output of the write enable flip-flop 21 and the system clock 4 as a write word driver drive signal line 43 and an AND gate 4.
12 and an inverter 411 that generates an inverted signal of the system clock 4 as a write precharge signal 45.

Referring to FIG. 3, read timing generation circuit 42 outputs system clock 4 as a read precharge signal 46 and outputs an inverted signal of system clock 4 as a read word driver drive signal.

Referring to FIG. 1, a write word driver 51 outputs a logical product of a signal from a write address decoder 31 and a write word driver drive signal 43 from a write timing generation circuit 41 as a write word signal 53. That is, if the specified address corresponds to the memory cell array 60, the write word driver drive signal 43 is applied to the memory cell array 60.

The read word driver 52 outputs a logical product of a signal from the read address decoder 32 and a read word driver drive signal 44 from the read timing generation circuit 42 as a write word signal 54. That is, if the specified address corresponds to the memory cell array 60, the read word driver drive signal 4
4 to the memory cell array 60.

Next, the operation of the embodiment of the present invention will be described with reference to the drawings.

Referring to FIGS. 1 and 4, first, when a write address 1 and a write enable signal 3 are supplied while the system clock 4 is not asserted,
The write address latch 11 is the write address decoder 3
1 to output the write address. As a result, a time required for decoding is secured until the system clock 4 is asserted. Write precharge is performed during a period when the system clock 4 is not asserted.

Then, when the system clock 4 is asserted, the write word line in the memory cell array 60 is driven through the write word driver 51, and the data given to the input data 61 is changed to each of the designated addresses. Written to the cell. On the other hand, in parallel with this, the read address latch 12
Output the read address. As a result, a time required for decoding is secured until the system clock 4 is no longer asserted. While the system clock 4 is being asserted, read precharge is performed.

When the system clock 4 is no longer asserted, the read word line in the memory cell array 60 is driven through the read word driver 52,
Data is read from each cell at the designated address and output as output data 62.

As described above, according to the embodiment of the present invention, the read precharge is performed in parallel with the write operation, and the timing of the write operation and the read operation is reduced by 1 /.
By shifting by two cycles, the written data can be read in one cycle even during high-speed operation.

In the present invention, for example, the number of RAM ports can be set to any number according to the requirements of the system. Further, a timing may be generated from the outside by adding a read enable signal. Also, if it is guaranteed that each signal can be supplied from the outside at appropriate timing, it is not always necessary to provide a write address latch or a read address latch. This is the same for the write enable flip-flop 21.

[0032]

As is apparent from the above description, according to the present invention, the write operation and the read operation in the multiport memory are shifted in timing by 1/2 cycle, so that even after high-speed operation, the write operation can be performed in one cycle. Data can be read. Further, since there is no need to provide a bypass circuit, the circuit configuration can be simplified and the design can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a memory control device of the present invention.

FIG. 2 is a diagram showing a configuration of a write timing generation circuit according to the present invention.

FIG. 3 is a diagram showing a configuration of a read timing generation circuit according to the present invention.

FIG. 4 is a diagram illustrating an operation of the exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional technique.

FIG. 6 is a diagram showing the operation of the conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Write address line 2 Read address line 3 Write enable line 4 System clock line 11 Write address latch 12 Read address latch 13 Inverter 21 Write enable flip-flop 31 Write address decoder 32 Read address decoder 41 Write timing generation circuit 42 Read timing generation circuit 43 Write word driver drive signal line (write pulse) 44 Read word driver drive signal line 45 Write precharge signal line 46 Read precharge signal line 51 Write word driver 52 Read word driver 53 Write word line 54 Read word line 60 Memory cell array 61 data input line 62 data output line 91 write address flip-flop 92 read address flip-flop 9 Delay gate 411 and 421 inverter 412 NAND gate

Claims (8)

[Claims] 1. A memory control device wherein a read precharge clock and a write precharge clock are shifted and supplied to a memory. 2. A read timing generation circuit for supplying a read precharge clock to a memory based on a system clock, and a write timing generation circuit for supplying a write precharge clock, which is an inverted signal of the read precharge clock, to the memory. A memory control device comprising: 3. A read address decoder for decoding a read address; and a read word driver for driving a read word line of the memory, wherein the read timing generation circuit outputs an inverted signal of the read precharge clock to a read clock. 3. The read word driver drives the read word line of the memory at the timing of the read clock generated by the read timing generation circuit in accordance with a result of decoding by the read address decoder. Memory controller. 4. A write address decoder for decoding a write address; and a write word driver for driving a write word line of the memory, wherein the write timing generation circuit outputs a write enable signal and a read precharge clock. Generating a logical product as a write pulse, wherein the write word driver drives a write word line of the memory at a timing of the write pulse generated by the write timing generation circuit in accordance with a decoding result by the write address decoder. 3. The memory control device according to claim 2, wherein: 5. A write address decoder for decoding a write address; and a write word driver for driving a write word line of the memory, wherein the write timing generation circuit outputs a write enable signal and a read precharge clock. Generating a logical product as a write pulse, wherein the write word driver drives a write word line of the memory at a timing of the write pulse generated by the write timing generation circuit in accordance with a decoding result by the write address decoder. 4. The memory control device according to claim 3, wherein: 6. A read address that outputs a read address as it is while the system clock is asserted, and holds and outputs a read address immediately before the system clock is no longer asserted while the system clock is not asserted. 4. The memory control device according to claim 3, further comprising a latch, wherein the read address decoder decodes a read address output from the read address latch. 7. A write address that outputs a write address as it is while the system clock is not asserted, and holds and outputs a write address immediately before the system clock is asserted while the system clock is asserted. 5. The memory control device according to claim 4, further comprising a latch, wherein the write address decoder decodes a write address output from the write address latch. 8. A write enable flip-flop that holds and outputs a write enable signal at an edge of the system clock, wherein the write timing generation circuit includes a write enable signal output from the write enable flip-flop and the read precharge. 4. The memory control device according to claim 3, wherein an AND with a clock is generated as a write pulse.