JPH01101723A - Receiving system - Google Patents

Abstract

PURPOSE:To cause the speed of a scanning to be high by providing two PLL circuits, simultaneously operating them and switch-using them. CONSTITUTION:The titled system is the super heterodyne receiver of a PLL system by microcomputer control and equips two local oscillators by the same types of two PLL circuits 3 and 4. Then, the system includes a means to lock the first PLL circuit at a present receiving frequency, a means to look the second PLL circuit 4 at the next receiving frequency and a means to change- over a switching circuit 14 by the detection of the absence of a receiving signal, to obtain a presently used lock value for the second PLL circuit 4 and to switch a successive frequency to lock the first PLL circuit 3 at the next frequency. Thus, the high speed scan can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scanning receiver that is an amateur radio in the HP band to the UHF band and is controlled by a micro combinator.

[Conventional technology]

Conventionally, in the FM communication system of amateur radio, a system of channel frequency allocation at fixed frequency intervals has been adopted since the main purpose is mobile use. Since the receiver only needs to be able to spot the channel frequency, a scanning receiver is used that sequentially receives spots from the bottom or top of the channel. When these scanning receivers detect a radio wave, they stop the scanning operation and continue receiving until the start button is pressed! When a radio wave is detected, scanning is temporarily stopped.
There is a format in which scanning is continued again after a predetermined time of several seconds has passed. Figure 2 shows an example of a conventional scanning circuit, in which a PLI and oscillation circuit are used in the local oscillator of a suit arm heterodyne receiver, and the system is controlled by a CPU. Since they are well-known circuits, they will not be described in detail, but they include a vCO that has a predetermined oscillation frequency range and can change the oscillation frequency with a DC voltage, and a variable frequency divider PD (Program) that divides the oscillation frequency.
mable Divider), a phase detector φD that compares the phase between its output and the output frequency of the reference oscillator, and the DC component obtained by passing the phase difference output t-LPF 'i to V.
In addition to CO, the oscillation frequency is stabilized when the phase difference output is zero.

The frequency of the VCO is 8X (the number of PD divisions). The PD is set by the CPU, and if there is no signal when checking the signal after oscillation has stabilized, the next frequency setting will be used. As is clear from the above operation, there is only one PLL circuit, and the reception frequency t
When changing from f t to f, -, as shown in Figure 3, the mouth,
Due to repeated fan locks, there is a period of unreceivable reception for each frequency change, and therefore scanning reception at a speed above a certain level is impossible.

In the PLL system, Y(a): Loop transfer function Wn: Loop natural frequency ζ (zeta), loop damping factor φ
: Phase comparator gain Kv : VCO gain N : Assuming programmable frequency division ratio, however, T
=CR,,T2=CR2, and although I omitted the reproduction, the larger ζ is, the shorter the time is, but the modulation frequency n (=W/'W
11) is high, especially when the reference frequency f is low, vC
Since it will leak during O output and worsen the C/N,
Usually ζ is 0.6 to 1.0, and Wn (-3db) is f
It is set from 1/100 of r to l/10. Therefore, with a PLL system with a low fr, it is difficult to shorten the time required for shooting two locations by one hour.

[Problem that the invention seeks to solve]

As mentioned above, there is a limit to increasing the scanning speed, and a common method to solve this problem is to use multiple loops in the PLL circuit and shorten the uptime for each loop.

It is impossible to reduce the quag time to zero, and a problem arises in that as the quag time increases, spurious signals are more likely to occur.

Accordingly, an object of the present invention is to provide a receiving system in which the speed of system scanning is increased by installing two PLL circuits, operating them simultaneously, and using them selectively.

[Means for solving problems]

The present invention is a PLL type soot+hetero gain receiver controlled by a micro combinatorial controller, in which two identical PLLs are connected.
It is equipped with two local oscillators using LL circuits, and during scanning, the first PLL circuit generates an output signal at the current receiving frequency.
The second PLL circuit includes means for locking at the next reception frequency, and a switching circuit for switching when detecting the absence of a reception signal. This is a high-speed scan reception method that includes means for sequentially switching frequencies, in which the first PLL circuit operates at the next frequency.

〔Example〕

FIG. 1 is a block diagram of an embodiment showing the receiving system of the present invention, in which the same parts in FIG. 1 and FIG. 3 is the first PLL circuit, which includes a programmable frequency divider PD6, a phase detector φD7, a low-pass filter LPF 8, and a VCOI.
A loop circuit 9], a second PLL circuit 4, a programmable frequency divider PDio, a phase detector φDll,
A loop circuit consisting of a low-pass filter LPF l 2 and a VCO 213, both of which are operated by the output of the reference oscillator REF 5 and the digital setting value of the CPU 2.
The signal is inputted to the mixer 1 and scanned at high speed by a switching circuit 14 which is controlled and alternately switched based on the detection of the absence of a received signal. To give and explain a specific example, let's take a scanning receiver for Amatea radio and set the frequency to 5.
0 to 54 MHz FM mode.

If the first intermediate frequency k is 10.7 MHz, the oscillation frequency of the local oscillator is 60.7 to 64.7 MHz or 3
9.3 to 43.3 ME (z, but here it is 60.7 to 64.7 ■h on one side.

The reference oscillator REF 5 is set to 10 kHz and is a direct frequency division type PLL, so the set value N is 6070 to 6470.

Here, if we were to scan upward from Iz (50,000 M), we would first set the setting value Ni6070 for PLL l, and at the same time set the setting value N=607 for PLL 2.
Send the data of 1. At this time, the switching circuit 14
is PLL 1 ([Il'e selected, 50,00
0 W (z t - first received. Next, the switching circuit 14 switches to the PLL 2 side and receives 50,010 MHz f!
: At the same time as receiving, set value N-607 to PLL l
Send the data of 2. Thereafter, the data of the current receiving frequency and the data of N+1 are sent to PLL 1 and PLL 2, respectively, and as shown in Fig. 3, CPU 2 is configured to receive the data with one PLL when one PLL is unlocked. Control your timing.

As a result, the unreceivable period due to the cyan lock time is reduced to zero, and continuous scanning from f1 to fn becomes possible.

In the case of the PLL circuit shown in Fig. 1, the loop-in decreases due to direct frequency division, and the reference oscillator REF 5 is
Since the frequency is low at kHz, the set value N becomes large and the lock-up time usually requires several tens of milliseconds, making high-speed scanning impossible with conventional methods.However, with the method of the present invention, the signal processing speed of the receiver can be increased. It is possible to increase the scanning speed up to

In the embodiment, Jingle Super is used, but it is of course possible to use multiple Sunoku. Also, there is no problem with PLL whether it is a multiple loop or a single loop.

〔Effect of the invention〕

According to the present invention, it is possible to perform high-speed scanning without considering the unrolling time of nine PLL circuits, which has a great practical effect in that amateur radio can be quickly dealt with.

[Brief explanation of the drawing]

FIG. 1 shows a superhetero gain receiver showing an embodiment of the present invention, in which the local oscillation is performed by a PLL circuit! The lock diagram, Figure 2 is a professional diagram of a superhetero gain receiver using the conventional method and local oscillation is a PLL circuit, Figure 3 is a time chart of the scanning in Figure 2, and Figure 4 is the scanning in Figure 1. FIG. 5 is a 70-chart diagram of the CPU of the present invention. 1...Mixer, 2...CPU, 3...PLLI,
4...PLL 2.5...Reference oscillator REF, 6.
10-15...Programmer frequency divider PD, 7/11
-16... Phase detector φD, 8, 12, 17... Low pass filter LPF, 9... VCOl. 13-VCO2, 18-VCO, l 4-...Switching circuit. Patent applicant Yaesu Musen Co., Ltd.

Claims (1)

[Claims] In a PLL type superheterodyne receiver whose frequency is controlled by a microcomputer, the first and second PLL circuits constitute two local oscillators, and the first and second PLL circuits operate together during scanning reception. The first PLL circuit is locked to the current reception frequency, the second PLL circuit is locked to the next frequency, and the first and second PLL circuits are switched while sequentially changing the frequency. A reception method characterized by scanning.