JP7688775B2 - Electro-optic display with ohmic conductive storage capacitor for relieving residual voltage - Google Patents

Description

(Reference to Related Applications)
This application claims priority to U.S. Patent Application No. 17/388,417, filed on July 29, 2021, and published on November 18, 2021 as U.S. Patent Publication No. 2021/0358424.

U.S. Patent Application No. 17/388,417 is related to U.S. Patent Application No. 17/032,189, filed September 25, 2000 (now U.S. Patent No. 11,107,425), U.S. Patent Application No. 16/745,473, filed January 17, 2020 (now U.S. Patent No. 10,825,405), and U.S. Patent Application No. 15/992,363, filed May 30, 2018 (now U.S. Patent No. 10,573,257), which claims priority to U.S. Provisional Patent Application No. 62/512,212, filed May 30, 2017. This application is also related to U.S. Patent Application No. 15/015,822, filed February 4, 2016 (now U.S. Patent No. 10,163,406), U.S. Patent Application No. 15/014,236, filed February 3, 2016 (now U.S. Patent No. 10,475,396), and U.S. Patent Application No. 15/266,554, filed September 15, 2016 (now U.S. Patent No. 10,803,813).

All of the above listed patents and applications are incorporated by reference in their entirety.

(Subject of the Invention)
The subject matter disclosed herein relates to means and methods for driving electro-optic displays. In particular, the subject matter relates to backplane designs for electro-optic displays and methods for driving and/or discharging such displays.

Electrophoretic displays or EPDs are generally driven by so-called DC balanced waveforms. DC balanced waveforms have been proven to improve the long-term use of EPDs by reducing serious hardware degradation and eliminating other reliability issues. However, DC balanced waveform constraints limit the set of possible waveforms available for driving EPD displays, making it difficult or sometimes impossible to implement advantageous features via waveform modes. For example, when implementing a "flashless" white-on-black display mode, excessive white border accumulation can become visible when a black-transitioned gray tone is next to a non-blinking black background. To eliminate such borders, a DC unbalanced driving scheme may work well, but such a driving scheme requires violating the DC balanced constraint. However, DC unbalanced driving schemes or waveforms may cause hardware degradation over time, which shortens the life of the display device. Therefore, there is a need to design electro-optic displays capable of operating with DC unbalanced waveforms or driving schemes without suffering hardware degradation.

According to one embodiment of the subject matter presented herein, an electrophoretic display is provided having a plurality of display pixels, each of which may include a pixel electrode for driving the display pixel, a single thin film transistor (TFT) coupled to the pixel electrode for transmitting a waveform to the pixel electrode, a front plane laminate (FPL) coupled to the single thin film transistor, and a storage capacitor coupled to the pixel electrode and placed in parallel with the FPL, the storage capacitor configured to be sufficiently ohmically conductive to enable release of residual voltage from the FPL through the storage capacitor.

In some embodiments, the resistance of the storage capacitor is approximately the same as the FPL resistance.

In some other embodiments, the resistance of the storage capacitor is one-third to three times the FPL resistance.

In yet another embodiment, the electrophoretic display may further comprise a discharge capacitor in parallel with the storage capacitor.
The present invention provides, for example, the following:
(Item 1)
1. An electrophoretic display having a plurality of display pixels, each of the plurality of display pixels comprising:
a pixel electrode for driving the display pixel;
a single thin film transistor (TFT) coupled to said pixel electrode for transmitting a waveform to said pixel electrode;
a front plane laminate (FPL) coupled to the single thin film transistor;
a storage capacitor coupled to the pixel electrode and disposed in parallel with the FPL;
Equipped with
An electrophoretic display, wherein the storage capacitor is configured to be sufficiently ohmic conductive to allow release of residual voltage from the FPL through the storage capacitor.
(Item 2)
2. The electrophoretic display of claim 1, wherein the resistance of the storage capacitor is approximately the same as the resistance of the FPL.
(Item 3)
2. The electrophoretic display of claim 1, wherein the resistance of the storage capacitor is between one third and three times the resistance of the FPL.
(Item 4)
10. The electrophoretic display of claim 1 further comprising a discharge capacitor in parallel with the storage capacitor.
(Item 5)
2. The electrophoretic display of claim 1, wherein the FPL comprises an electrophoretic material.
(Item 6)
6. The electrophoretic display of claim 5, wherein the electrophoretic material comprises an encapsulated electrophoretic material comprising charged pigment particles in a fluid medium.

FIG. 1 is one embodiment of an equivalent circuit of a display pixel in accordance with the subject matter presented herein.

2A and 2B are graphs illustrating the graytone and afterimage shifts of a display due to shifts in TFT performance.

FIG. 3 is an example pixel design to enable the use of post-driving discharge without introducing an optical shift in accordance with the subject matter presented herein.

FIG. 4 is another pixel design to enable the use of post-driving discharge without introducing an optical shift in accordance with the subject matter presented herein.

FIG. 5 is a voltage sequence following active updating followed by discharging.

FIG. 6 is another pixel design to enable the use of post-driving discharge without introducing an optical shift according to the subject matter presented herein.

FIG. 7 is yet another pixel design to enable the use of post-driven discharge without introducing an optical shift in accordance with the subject matter presented herein.

FIG. 8 shows a voltage sequence after active updating followed by discharging.

FIG. 9 is another pixel design in accordance with the subject matter presented herein.

FIG. 10a illustrates one experimental setup for measuring the FPL voltage.

10b-10c illustrate the FPL voltages measured using the setup illustrated in FIG. 10a.

FIG. 10d illustrates an example of a simulated active matrix drive during the drive phase.

11a-11e illustrate the FPL voltage and display brightness measured using different Rd values using the setup illustrated in FIG. 10a.

FIG. 12 illustrates a cross-sectional view of one configuration for a display pixel in accordance with the subject matter presented herein.

FIG. 13 illustrates yet another pixel design in accordance with the subject matter presented herein.

FIG. 14 illustrates a cross-sectional view of another configuration for a display pixel in accordance with the subject matter presented herein.

The subject matter disclosed herein relates to improving electro-optic display durability, particularly with respect to improving optical property shifts, such as reducing graytone and afterimage shifts, caused by component stress.

The term "electro-optical" is used in its conventional sense in the imaging arts as applied to a material or display, and is used herein to refer to a material having first and second display states that differ in at least one optical property, the material being changed from its first to its second display state by application of an electric field to the material. The optical property is typically color perceptible to the human eye, but may be another optical property such as optical transmittance, reflectance, luminescence, or, in the case of displays intended for machine reading, pseudocolor in the sense of a change in reflection of electromagnetic wavelengths outside the visible range.

The terms "bistable" and "bi-stable" are used herein in their conventional sense in the art to refer to a display comprising a display element having first and second display states differing in at least one optical property, where a given element is driven with an address pulse of finite duration to exhibit either the first or second display state, and where that state persists after the address pulse is terminated for at least several times, e.g., at least four times, the minimum duration of the address pulse required to change the state of the display element. In U.S. Pat. No. 7,170,670, it is shown that some particle-based electrophoretic displays capable of gray scale are stable not only in their extreme black and white states, but also in their intermediate gray states, and the same is true for some other types of electro-optic displays. Displays of this type are appropriately referred to as "multistable" rather than bistable, but for convenience the term "bistable" may be used herein to encompass both bistable and multistable displays.

The term "gray state" is used herein in its conventional sense in the imaging arts to refer to a state intermediate between two extreme pixel optical states, and not necessarily to a transition between these two extreme states of black and white. For example, several electrophoretic ink patents and published applications referenced below describe electrophoretic displays in which the extreme states are white and dark blue, and the intermediate "gray state" is actually light blue. In fact, as already mentioned, the change in optical state may not be a change in color at all. The terms "black" and "white" may be used hereinafter to refer to the two extreme optical states of the display, and should be understood to generally include extreme optical states that are not strictly black and white, such as, for example, the white and dark blue states mentioned above. The term "monochrome" may be used hereinafter to refer to a display or drive scheme that drives pixels only to their two extreme optical states, with no intervening gray states.

The term "pixel" is used herein in its conventional sense in display technology to mean the smallest unit of a display capable of generating all the colors the display itself can show. In a full-color display, each pixel typically consists of a number of subpixels, each of which can display fewer than all the colors the display itself can show. For example, in most conventional full-color displays, each pixel consists of a red subpixel, a green subpixel, a blue subpixel, and optionally a white subpixel, each of which can display a range of colors from black to the brightest version of its defined color.

Several types of electro-optic displays are known. One type of electro-optic display is the rotating dichroic member type, as described, for example, in U.S. Patent Nos. 5,808,783, 5,777,782, 5,760,761, 6,054,071, 6,055,091, 6,097,531, 6,128,124, 6,137,467, and 6,147,791 (this type of display is often referred to as a "rotating dichroic ball" display, although in some of the aforementioned patents the term "rotating dichroic member" is preferred as more accurate since the rotating member is not spherical). Such displays use a number of small bodies (typically spherical or cylindrical) having two or more segments with different optical properties and an internal dipole. These bodies are suspended within a liquid-filled cavity in a matrix, which is filled with liquid so that the bodies are free to rotate. The appearance of the display is altered by applying an electric field to the display, thus rotating the bodies to various positions and varying the sections of the bodies that are seen through the viewing surface. This type of electro-optic medium is typically bistable.

Another type of electro-optic display uses an electrochromic medium, for example in the form of a nanochromic film consisting of electrodes formed at least in part from a semiconducting metal oxide and a plurality of dye molecules attached to the electrodes that are capable of reversing the color change. See, for example, O'Regan, B., et al, Nature 1991, 353, 737, and Wood, D., Information Display, 18(3), 24 (March 2002). See also Bach, U., et al, Adv. Mater., 2002, 14(11), 845. Nanochromic films of this type are also described, for example, in U.S. Patent Nos. 6,301,038, 6,870,657, and 6,950,220. This type of medium is also typically bistable.

Another type of electro-optic display is the electrowetting display developed by Philips and described in Hayes, R. A., et al., "Video-Speed Electronic Paper Based on Electrowetting", Nature, 425, 383-385 (2003). It is shown in U.S. Patent No. 7,420,549 that such electrowetting displays can be bistable.

One type of electro-optic display that has been the subject of research and development interest for many years is the particle-based electrophoretic display, in which a plurality of electrically charged particles move through a fluid under the influence of an electric field. Electrophoretic displays can have attributes of good brightness and contrast, wide viewing angles, state bistability, and low power consumption when compared to liquid crystal displays.

As mentioned above, electrophoretic media require the presence of a fluid. In most prior art electrophoretic media, this fluid is liquid, but electrophoretic media can be produced using gaseous fluids (see, for example, Kitamura, T., et al., "Electrical toner movement for electronic paper-like display", IDW Japan, 2001, Paper HCS1-1, and Yamaguchi, Y., et al., "Toner display using insulative particles charged triboelectrically", IDW Japan, 2001, Paper AMD4-4). See also U.S. Patent Nos. 7,321,459 and 7,236,291. Such gas-based electrophoretic media are believed to be susceptible to the same types of problems as liquid-based electrophoretic media due to particle settling when the media is used in an orientation that allows for such settling, such as, for example, a sign in which the media is positioned in a vertical plane. Indeed, particle settling is believed to be a more severe problem in gas-based electrophoretic media than in liquid-based electrophoretic media due to the lower viscosity of the gaseous suspending fluid compared to the viscosity of the fluid that allows for faster settling of the electrophoretic particles.

Numerous patents and applications assigned to or in the name of the Massachusetts Institute of Technology (MIT) and E Ink Corporation describe various techniques used for encapsulated electrophoretic and other electro-optic media. Such encapsulated media include a number of small capsules, each of which itself includes an internal phase that includes electrophoretically movable particles in a fluid medium, and a capsule wall that surrounds the internal phase. Typically, the capsules are themselves held in a polymer adhesive to form a coherent layer that is positioned between two electrodes. Techniques described in these patents and applications include:
(a) Electrophoretic Particles, Fluids, and Fluid Additives (see, e.g., U.S. Pat. Nos. 7,002,728 and 7,679,814)
(b) Capsules, binders, and encapsulation processes (see, e.g., U.S. Pat. Nos. 6,922,276 and 7,411,719)
(c) Films and subassemblies containing electro-optical materials (see, e.g., U.S. Pat. Nos. 6,982,178 and 7,839,564).
(d) backplanes, adhesive layers, and other auxiliary layers, and methods used in displays (e.g., U.S. Pat. Nos. 485,294, 6,124,851, 6,130,773, 6,177,921, 6,232,950, 6,252,564, 6,312,304, 6,312,971, No. 6,376,828, No. 6,392,786, No. 6,413,790, No. 6,422,687, No. 6,445,374, No. 6,480,182, No. 6 , No. 498,114, No. 6,506,438, No. 6,518,949, No. 6,521,489, No. 6,535,197, No. 6,545,291, No. 6,6 No. 39,578, No. 6,657,772, No. 6,664,944, No. 6,680,725, No. 6,683,333, No. 6,724,519, No. 6,75 No. 0,473, No. 6,816,147, No. 6,819,471, No. 6,825,068, No. 6,831,769, No. 6,842,167, No. 6,842, No. 279, No. 6,842,657, No. 6,865,010, No. 6,873,452, No. 6,909,532, No. 6,967,640, No. 6,980,19 No. 6, No. 7,012,735, No. 7,030,412, No. 7,075,703, No. 7,106,296, No. 7,110,163, No. 7,116,318 , No. 7,148,128, No. 7,167,155, No. 7,173,752, No. 7,176,880, No. 7,190,008, No. 7,206,119, No. 7,223,672, No. 7,230,751, No. 7,256,766, No. 7,259,744, No. 7,280,094, No. 7,301,693, No. 7 , 304,780, 7,327,511, 7,347,957, 7,349,148, 7,352,353, 7,365,394, 7,3 No. 65,733, No. 7,382,363, No. 7,388,572, No. 7,401,758, No. 7,442,587, No. 7,492,497, No. 7,535 , No. 7,551,346, No. 7,554,712, No. 7,583,427, No. 7,598,173, No. 7,605,799, No. 7,636, No. 191, No. 7,649,674, No. 7,667,886, No. 7,672,040, No. 7,688,497, No. 7,733,335, No. 7,785,98 No. 8, No. 7,830,592, No. 7,843,626, No. 7,859,637, No. 7,880,958, No. 7,893,435, No. 7,898,717 , No. 7,905,977, No. 7,957,053, No. 7,986,450, No. 8,009,344, No. 8,027,081, No. 8,049,947, No. No. 8,072,675, No. 8,077,141, No. 8,089,453, No. 8,120,836, No. 8,159,636, No. 8,208,193, No. 8 , No. 237,892, No. 8,238,021, No. 8,362,488, No. 8,373,211, No. 8,389,381, No. 8,395,836, No. 8,4 No. 37,069, No. 8,441,414, No. 8,456,589, No. 8,498,042, No. 8,514,168, No. 8,547,628, No. 8,576 , No. 162, No. 8,610,988, No. 8,714,780, No. 8,728,266, No. 8,743,077, No. 8,754,859, No. 8,797,2 No. 58, No. 8,797,633, No. 8,797,636, No. 8,830,560, No. 8,891,155, No. 8,969,886, No. 9,147,36 No. 4, No. 9,025,234, No. 9,025,238, No. 9,030,374, No. 9,140,952, No. 9,152,003, No. 9,152,004 , 9,201,279, 9,223,164, 9,285,648, and 9,310,661, and U.S. Patent Application Publication Nos. 2002/0060321, 2004/0008179, 2004/0085619, 2004/0105036, 2004/0112525, 2005/0122 No. 306, No. 2005/0122563, No. 2006/0215106, No. 2006/0255322, No. 2007/0052757, No. 2007/00 No. 97489, No. 2007/0109219, No. 2008/0061300, No. 2008/0149271, No. 2009/0122389, No. 2009/0 No. 315044, No. 2010/0177396, No. 2011/0140744, No. 2011/0187683, No. 2011/0187689, No. 2011/ No. 0292319, No. 2013/0250397, No. 2013/0278900, No. 2014/0078024, No. 2014/0139501, No. 2014 /0192000, 2014/0210701, 2014/0300837, 2014/0368753, 2014/0376164, 20 No. 15/0171112, No. 2015/0205178, No. 2015/0226986, No. 2015/0227018, No. 2015/0228666, No. 2 (see International Patent Publication Nos. 2015/0261057, 2015/0356927, 2015/0378235, 2016/077375, 2016/0103380, and 2016/0187759, and International Application Publication Nos. WO 00/38000, European Patent Nos. 1,099,207 B1 and 1,145,072 B1).
(e) color formation and color control (e.g., U.S. Pat. Nos. 6,017,584, 6,664,944, 6,864,875, 7,075,502, 7,167,155, 7,667,684, 7,791,789, 7,956,841, 8,040,594, 8 ,054,526, 8,098,418, 8,213,076, and 8,363,299, and U.S. Patent Application Publication Nos. 2004/0263947, 2007/0109219, 2007/0223079, 2008/0023332, 2008/004331 No. 8, No. 2008/0048970, No. 2009/0004442, No. 2009/0225398, No. 2010/0103502, No. 2 No. 010/0156780, No. 2011/0164307, No. 2011/0195629, No. 2011/0310461, No. 2012/00 (See US Pat. Nos. 2012/08188, 2012/0019898, 2012/0075687, 2012/0081779, 2012/0134009, 2012/0182597, 2012/0212462, 2012/0157269, and 2012/0326957).
(f) Methods of driving displays (see, e.g., U.S. Pat. Nos. 7,012,600 and 7,453,445)
(g) Display Applications (see, e.g., U.S. Pat. Nos. 7,312,784 and 8,009,348)
(h) Non-electrophoretic displays (see U.S. Pat. Nos. 6,241,921, 6,950,220, 7,420,549, and 8,319,759, and U.S. Patent Application Publication No. 2012/0293858)
(i) Microcell structures, wall materials, and methods of forming the microcells (see, e.g., U.S. Pat. Nos. 7,072,095 and 9,279,906);
(j) Methods of filling and sealing microcells (see, e.g., U.S. Pat. Nos. 7,144,942 and 7,715,088)

This application further relates to U.S. Pat. Nos. 485,294, 6,124,851, 6,130,773, 6,177,921, 6,232,950, 6,252,564, 6,312,304, 6,312,971, 6,376,828, 6,392,786, 6,413,790, 6,42 No. 2,687, No. 6,445,374, No. 6,480,182, No. 6,498,114, No. 6,506,438, No. 6,518,949, No. 6,521, No. 489, No. 6,535,197, No. 6,545,291, No. 6,639,578, No. 6,657,772, No. 6,664,944, No. 6,680,72 No. 5, No. 6,683,333, No. 6,724,519, No. 6,750,473, No. 6,816,147, No. 6,819,471, No. 6,825,068 No. 6,831,769, No. 6,842,167, No. 6,842,279, No. 6,842,657, No. 6,865,010, No. 6,873,452, No. 6,909,532, No. 6,967,640, No. 6,980,196, No. 7,012,735, No. 7,030,412, No. 7,075,703, No. 7 , No. 106,296, No. 7,110,163, No. 7,116,318, No. 7,148,128, No. 7,167,155, No. 7,173,752, No. 7,1 No. 76,880, No. 7,190,008, No. 7,206,119, No. 7,223,672, No. 7,230,751, No. 7,256,766, No. 7,25 No. 9,744, No. 7,280,094, No. 7,301,693, No. 7,304,780, No. 7,327,511, No. 7,347,957, No. 7,349, No. 148, No. 7,352,353, No. 7,365,394, No. 7,365,733, No. 7,382,363, No. 7,388,572, No. 7,401,75 No. 8, No. 7,442,587, No. 7,492,497, No. 7,535,624, No. 7,551,346, No. 7,554,712, No. 7,583,427 , No. 7,598,173, No. 7,605,799, No. 7,636,191, No. 7,649,674, No. 7,667,886, No. 7,672,040, No. No. 7,688,497, No. 7,733,335, No. 7,785,988, No. 7,830,592, No. 7,843,626, No. 7,859,637, No. 7, No. 880,958, No. 7,893,435, No. 7,898,717, No. 7,905,977, No. 7,957,053, No. 7,986,450, No. 8,00 No. 9,344, No. 8,027,081, No. 8,049,947, No. 8,072,675, No. 8,077,141, No. 8,089,453, No. 8,120, No. 836, No. 8,159,636, No. 8,208,193, No. 8,237,892, No. 8,238,021, No. 8,362,488, No. 8,373,2 No. 11, No. 8,389,381, No. 8,395,836, No. 8,437,069, No. 8,441,414, No. 8,456,589, No. 8,498,042 No. 8,514,168, No. 8,547,628, No. 8,576,162, No. 8,610,988, No. 8,714,780, No. 8,728,266, No. 8,743,077, No. 8,754,859, No. 8,797,258, No. 8,797,633, No. 8,797,636, No. 8,830,560, No. 8 ,891,155, 8,969,886, 9,147,364, 9,025,234, 9,025,238, 9,030,374, 9,140,952, 9,152,003, 9,152,004, 9,201,279, 9,223,164, 9,285,648, and 9, 310,661, and U.S. Patent Application Publication Nos. 2002/0060321, 2004/0008179, 2004/0085619, 2004/0105036, 2004/0112525, 2005/0122306, 2005/0122563, 2006/0215106, 2006/02 No. 55322, No. 2007/0052757, No. 2007/0097489, No. 2007/0109219, No. 2008/0061300, No. 2008/ No. 0149271, No. 2009/0122389, No. 2009/0315044, No. 2010/0177396, No. 2011/0140744, No. 2011 /0187683, 2011/0187689, 2011/0292319, 2013/0250397, 2013/0278900, 201 No. 4/0078024, No. 2014/0139501, No. 2014/0192000, No. 2014/0210701, No. 2014/0300837, No. 20 No. 14/0368753, No. 2014/0376164, No. 2015/0171112, No. 2015/0205178, No. 2015/0226986, No. 2 No. 015/0227018, No. 2015/0228666, No. 2015/0261057, No. 2015/0356927, No. 2015/0378235, No. Nos. 2016/077375, 2016/0103380, and 2016/0187759, and International Publication Nos. WO 00/38000, European Patent Nos. 1,099,207 B1, and 1,145,072 B1 (all of the above-listed applications are incorporated by reference in their entirety).

This application is a continuation of U.S. Patent Nos. 5,930,026, 6,445,489, 6,504,524, 6,512,354, 6,531,997, 6,753,999, 6,825,970, 6,900,851, 6,995,550, 7,012,600, 7, No. 023,420, No. 7,034,783, No. 7,061,166, No. 7,061,662, No. 7,116,466, No. 7,119,7 No. 72, No. 7,177,066, No. 7,193,625, No. 7,202,847, No. 7,242,514, No. 7,259,744, No. 7 , 304,787, 7,312,794, 7,327,511, 7,408,699, 7,453,445, 7,492, No. 339, No. 7,528,822, No. 7,545,358, No. 7,583,251, No. 7,602,374, No. 7,612,760, No. No. 7,679,599, No. 7,679,813, No. 7,683,606, No. 7,688,297, No. 7,729,039, No. 7,733 , No. 311, No. 7,733,335, No. 7,787,169, No. 7,859,742, No. 7,952,557, No. 7,956,841, No. 7,982,479, No. 7,999,787, No. 8,077,141, No. 8,125,501, No. 8,139,050, No. 8,17 No. 4,490, No. 8,243,013, No. 8,274,472, No. 8,289,250, No. 8,300,006, No. 8,305,341 , No. 8,314,784, No. 8,373,649, No. 8,384,658, No. 8,456,414, No. 8,462,102, No. 8,5 No. 37,105, No. 8,558,783, No. 8,558,785, No. 8,558,786, No. 8,558,855, No. 8,576,164 No. 8,576,259, No. 8,593,396, No. 8,605,032, No. 8,643,595, No. 8,665,206, No. 8, No. 681,191, No. 8,730,153, No. 8,810,525, No. 8,928,562, No. 8,928,641, No. 8,976,44 No. 4, No. 9,013,394, No. 9,019,197, No. 9,019,198, No. 9,019,318, No. 9,082,352, No. 9 , No. 171,508, No. 9,218,773, No. 9,224,338, No. 9,224,342, No. 9,224,344, No. 9,230,4 Nos. 92, 9,251,736, 9,262,973, 9,269,311, 9,299,294, 9,373,289, 9,390,066, 9,390,661, and 9,412,314, and U.S. Patent Application Publication Nos. 2003/0102858, ... No. 004/0246562, No. 2005/0253777, No. 2007/0070032, No. 2007/0076289, No. 2007/0 No. 091418, No. 2007/0103427, No. 2007/0176912, No. 2007/0296452, No. 2008/0024429 No. 2008/0024482, No. 2008/0136774, No. 2008/0169821, No. 2008/0218471, No. 20 No. 08/0291129, No. 2008/0303780, No. 2009/0174651, No. 2009/0195568, No. 2009/032 No. 2721, No. 2010/0194733, No. 2010/0194789, No. 2010/0220121, No. 2010/0265561 , No. 2010/0283804, No. 2011/0063314, No. 2011/0175875, No. 2011/0193840, No. 2011 /0193841, 2011/0199671, 2011/0221740, 2012/0001957, 2012/0098 No. 740, No. 2013/0063333, No. 2013/0194250, No. 2013/0249782, No. 2013/0321278, No. 2014/0009817, 2014/0085355, 2014/0204012, 2014/0218277, 2014/ No. 0240210, No. 2014/0240373, No. 2014/0253425, No. 2014/0292830, No. 2014/029339 8, 2014/0333685, 2014/0340734, 2015/0070744, 2015/0097877, 2015/0109283, 2015/0213749, 2015/0213765, 2015/0221257, 2015/0262255, 2016/0071465, 2016/0078820, 2016/0093253, 2016/0140910, and 2016/0180777 (all of the above-listed applications are incorporated by reference in their entirety).

Many of the aforementioned patents and applications recognize that the walls surrounding the separate microcapsules in an encapsulated electrophoretic medium may be replaced with a continuous phase, thus producing so-called polymer-dispersed electrophoretic displays, in which the electrophoretic medium comprises a plurality of separate droplets of electrophoretic fluid and a continuous phase of polymeric material, and that the separate droplets of electrophoretic fluid in such polymer-dispersed electrophoretic displays may be considered capsules or microcapsules even though a separate capsule membrane is not associated with each individual droplet. See, for example, the aforementioned U.S. Patent No. 6,866,760. Thus, for purposes of this application, such polymer-dispersed electrophoretic media are considered a subspecies of encapsulated electrophoretic media.

A related type of electrophoretic display is the so-called "microcell electrophoretic display." In a microcell electrophoretic display, the electrically charged particles and fluid are not encapsulated in microcapsules, but instead are held within a number of cavities formed in a carrier medium, typically a polymer film. See, for example, U.S. Patent Nos. 6,672,921 and 6,788,449 (both assigned to Sipix Imaging, Inc.).

Although electrophoretic media are often opaque (e.g., in many electrophoretic media, the particles substantially block the transmission of visible light through the display) and operate in a reflective mode, many electrophoretic displays can be made to operate in a so-called "shutter" mode, in which one display state is substantially opaque and one is light transmissive. See, for example, U.S. Pat. Nos. 5,872,552, 6,130,774, 6,144,361, 6,172,798, 6,271,823, 6,225,971, and 6,184,856. Dielectrophoretic displays are similar to electrophoretic displays, but rely on variations in electric field strength and can operate in a similar mode. See U.S. Pat. No. 4,418,346. Other types of electro-optic displays may also be capable of operating in a shutter mode. Electro-optic media operating in shutter mode can be used in multi-layer structures for full color displays, where at least one layer adjacent to the viewing surface of the display operates in shutter mode to reveal or conceal a second layer that is further from the viewing surface.

Encapsulated electrophoretic displays typically do not suffer from the clustering and settling failure modes of conventional electrophoretic devices, and offer additional advantages such as versatile flexibility and the ability to print or coat the display on rigid substrates. (The use of the word "printing" is intended to include all forms of printing and coating, including, but not limited to, pre-metered coating, e.g., patch die coating, slot or extrusion coating, slide or cascade coating, curtain coating, etc., roll coating, e.g., knife-over-roll coating, forward and reverse roll coating, etc., gravure coating, dip coating, spray coating, meniscus coating, spin coating, brush coating, air knife coating, silk screen printing processes, electrostatic printing processes, thermal printing processes, ink jet printing processes, electrophoretic deposition (see U.S. Pat. No. 7,339,715), and other similar techniques.) Thus, the resulting display can be flexible. Moreover, because the display medium can be printed using a variety of methods, the display itself can be inexpensively produced.

Other types of electro-optical materials may also be used in the present invention.

Electrophoretic displays typically comprise a layer of electrophoretic material and at least two other layers, one of which is an electrode layer, disposed on either side of the electrophoretic material. In most such displays, both layers are electrode layers, and one or both of the electrode layers are patterned to define the pixels of the display. For example, one electrode layer may be patterned into elongated row electrodes and the other into elongated column electrodes extending at right angles to the row electrodes, the pixels being defined by the intersections of the row and column electrodes. Alternatively, and more commonly, one electrode layer has the form of a single continuous electrode and the other electrode layer is patterned into a matrix of pixel electrodes, each of which defines one pixel of the display. In another type of electrophoretic display intended for use with a stylus, printhead, or similar movable electrode separate from the display, only one of the layers adjacent to the electrophoretic layer comprises an electrode; the layer opposite the electrophoretic layer is typically a protective layer intended to prevent the movable electrode from damaging the electrophoretic layer.

In yet another embodiment, as described in U.S. Pat. No. 6,704,133, an electrophoretic display may be constructed with two continuous electrodes and an electrophoretic layer and an optoelectrophoretic layer between the electrodes. The optoelectrophoretic material changes resistivity with the absorption of photons, so incident light can be used to modify the state of the electrophoretic medium. Such a device is illustrated in FIG. 1. As described in U.S. Pat. No. 6,704,133, the device of FIG. 1 works best when driven by an emissive source, such as an LCD display, located on the opposite side of the display from the viewing surface. In some embodiments, the device of U.S. Pat. No. 6,704,133 incorporates a special barrier layer between the front electrode and the optoelectrophoretic material to reduce "dark current" caused by light incident from the front of the display leaking across the reflective electrooptic medium.

The aforementioned U.S. Patent No. 6,982,178 describes a method of assembling solid electro-optic displays (including encapsulated electrophoretic displays) that is highly suitable for mass production. Essentially, this patent describes a so-called "front plane laminate" ("FPL") that comprises, in order, a light-transmitting conductive layer, a layer of solid electro-optic medium in electrical contact with the conductive layer, an adhesive layer, and a release sheet. Typically, the light-transmitting conductive layer is supported on a light-transmitting substrate, which is preferably flexible in the sense that the substrate can be manually wrapped around a 10 inch (254 mm) diameter drum (for example) without permanent deformation. In this application and herein, the term "light-transmissive" is used to mean that the layer so designated transmits sufficient light to enable an observer looking through the layer to observe a change in the display state of the electro-optic medium, usually seen through the conductive layer and adjacent substrate (if present); if the electro-optic medium displays a change in reflectance at non-visible wavelengths, the term "light-transmissive" should of course be interpreted to refer to the transmission of the relevant non-visible wavelengths. The substrate is typically a polymeric film and will usually have a thickness within the range of about 1 to about 25 mils (25-634 μm), preferably about 2 to about 10 mils (51-254 μm). The conductive layer may conveniently be a thin metal or metal oxide layer, for example, of aluminum or ITO, or may be a conductive polymer. Aluminum or ITO coated poly(ethylene terephthalate) (PET) films are available, for example, from E. I. Mylar is commercially available as "aluminized Mylar" ("Mylar" is a registered trademark) from the Fabry-Perot Company, Wilmington DE, and such commercial materials may be used with good results in front plane laminates. The process for forming an electro-optic display using a front plane laminate may include the use of a thermal lamination process to attach the FPL or dual release film to the backplane. The backplane may be of the direct drive segmented variety, with one or more patterned conductive traces, or may be of the nonlinear circuit variety (e.g., active matrix).

The aforementioned U.S. Patent No. 6,982,178 also describes a method of testing the electro-optic medium in a front plane laminate prior to incorporation of the front plane laminate into a display. In this testing method, a release sheet is provided with a conductive layer, and a voltage sufficient to change the optical state of the electro-optic medium is applied between this conductive layer and a conductive layer opposite the electro-optic medium. Observation of the electro-optic medium will then reveal any defects in the medium, thus avoiding laminating a defective electro-optic medium into the display and avoiding the costs incurred in discarding not only a defective front plane laminate but the entire display.

The aforementioned U.S. Patent No. 6,982,178 also describes a second method for testing the electro-optic medium in a front plane laminate by placing static electricity on a release sheet, thus forming an image on the electro-optic medium. This image is then viewed, as before, to detect any defects in the electro-optic medium.

Assembly of an electro-optic display using such a front plane laminate may be accomplished by removing the release sheet from the front plane laminate and contacting the adhesive layer with the backplane under conditions effective to adhere the adhesive layer to the backplane, thereby securing the adhesive layer, layer of electro-optic medium, and conductive layer to the backplane. This process is well suited to mass production, as the front plane laminate can be mass produced, typically using roll-to-roll coating techniques, and then cut into pieces of any size required for use with a particular backplane.

No. 7,561,324 describes a so-called "dual release sheet," which is essentially a simplified version of the front plane laminate of the aforementioned U.S. Pat. No. 6,982,178. One form of the dual release sheet comprises a layer of solid electro-optic medium sandwiched between two adhesive layers, one or both of which are covered by a release sheet. Another form of the dual release sheet comprises a layer of solid electro-optic medium sandwiched between two release sheets. Both forms of the dual release film are intended for use in a process generally similar to the process for assembling an electro-optic display from a front plane laminate already described, but involving two separate laminations; typically, in a first lamination, the dual release sheet is laminated to a front electrode to form a front assembly, and then, in a second lamination, the front assembly is laminated to a backplane to form the final display, although the order of these two laminations can be reversed if desired.

No. 7,839,564 describes a so-called "inverted front plane laminate," which is a variation of the front plane laminate described in the aforementioned U.S. Pat. No. 6,982,178. This inverted front plane laminate comprises, in order, at least one of a light-transmissive protective layer and a light-transmissive conductive layer, an adhesive layer, a layer of a solid electro-optic medium, and a release sheet. This inverted front plane laminate is used to form an electro-optic display having a layer of laminating adhesive between the electro-optic layer and the front electrode or front substrate, and a second (typically thin layer of adhesive) may or may not be present between the electro-optic layer and the backplane. Such electro-optic displays can combine good resolution with good low temperature performance.

The photoelectrophoretic properties of certain pigments have been recognized for some time. For example, U.S. Pat. No. 3,383,993 discloses a photoelectrophoretic imaging device that can be used to reproduce an image projected onto a transparent electrode of a medium (typically ITO or the like). The photoelectrophoretic process described in the '993 patent and other related patents by Xerox Corporation is not reversible, however, as the photoelectrophoretic process involves the migration of photoelectrophoretic particles to an "injection electrode" where they become attached to the electrode. The lack of reversibility and the cost and complexity of the setup have prevented the phenomenon from being widely commercialized.

Although the display of the present invention is intended to display images for long periods of time with little or no energy input, the looped display described above can be used to refresh content on the same time scale as emissive displays (e.g., large LED displays). The display of the present invention can display two different images in less than an hour (e.g., less than 10 minutes, e.g., less than 5 minutes, e.g., less than 2 minutes). Furthermore, the refresh periods can be staggered depending on the use of the display. For example, the transport schedule can be refreshed every 5 minutes with an advertisement lasting 30 seconds, then the transport schedule is switched back to another 5 minute period.

In some cases, one method that enables the use of DC unbalanced waveforms is to discharge the display module after active updating. The discharge then involves shorting the imaging film of the display and eliminating the residual charge that accumulates on the imaging film (e.g., a layer of electrophoretic material) due to DC unbalanced driving. The use of post-update driving discharge (referred to herein as uPDD or UPD) has been successfully demonstrated to reduce the accumulation of residual charge (measured by residual voltage) and corresponding module polarization that would otherwise result in permanent degradation of the imaging film due to its electrochemical nature.

Remnant voltage is now found to be a more common phenomenon in electrophoretic and other impulse-driven electro-optic displays, both in cause and effect. It has also been found that DC imbalance can cause long-term lifetime degradation of some electrophoretic displays.

There are several potential sources of residual voltage. The primary cause of residual voltage is believed to be ionic polarization within the materials of the various layers that form the display (although some embodiments are not limited in any way by this concept).

Such polarization occurs in a variety of ways. In the first (for convenience designated "Type I") polarization, an ionic double layer is created across or adjacent to a material interface. For example, a positive potential at an indium tin oxide ("ITO") electrode may produce a corresponding polarized layer of negative ions in the adjacent lamination adhesive. The decay rate of such a polarized layer is related to the recombination of separated ions within the lamination adhesive layer. The geometry of such a polarized layer is determined by the shape of the interface, but may be planar in nature.

In the second ("Type II") type of polarization, nodules, crystals, or other types of material heterogeneity within a single material can result in regions where ions can move slower than the surrounding material. Different ion migration rates can result in different degrees of charge polarization within the bulk of the media, and polarization can therefore occur within a single display component. Such polarization can be substantially localized in nature or distributed throughout the entire layer.

In the third ("Type III") type of polarization, polarization can occur at any interface that represents a barrier to charge transport of any particular type of ion. One example of such an interface in a microcavity electrophoretic display is the boundary between an electrophoretic suspension ("internal phase") that contains the suspending medium and particles, and a surrounding medium ("external phase") that contains walls, adhesives, and binders. In many electrophoretic displays, the internal phase is a hydrophobic liquid, while the external phase is a polymer, such as gelatin. Ions present in the internal phase may be insoluble and non-diffusible in the external phase, and vice versa. Upon application of an electric field perpendicular to such an interface, polarization layers of opposite sign will accumulate on both sides of the interface. When the applied electric field is removed, the resulting non-equilibrium charge distribution results in a measurable residual voltage potential that decays with a relaxation time determined by the mobility of the ions in the two phases on either side of the interface.

Polarization can occur during a drive pulse. Each image update is an event that can affect the remnant voltage. A positive waveform voltage can produce a remnant voltage across the electro-optic medium that is of the same or opposite polarity (or nearly zero), depending on the particular electro-optic display.

From the preceding discussion, it will be apparent that polarization can occur at multiple locations within an electrophoretic or other electro-optic display, primarily at interfaces and material heterogeneities, with each location having its own characteristic spectrum of decay times. Depending on the location of these voltage sources (in other words, the polarized charge distributions) relative to the electroactive moieties (e.g., the electrophoretic suspension), and the degree of electrical coupling between each type of charge distribution and the movement of particles through the suspension or other electro-optic activity, various types of polarization will produce more or less deleterious effects. Since electrophoretic displays operate by the movement of charged particles which inherently creates polarization in the electro-optic layer, in a sense a preferred electrophoretic display is not one in which residual voltages are not present in the display at all times, but rather one in which residual voltages do not cause objectionable electro-optic behavior. Ideally, the residual impulse is minimized by introducing a minimal pause between image updates so that the electrophoretic display can affect all transitions between optical states without concern for residual voltage effects, and the residual voltage will decrease to below 1 V, preferably below 0.2 V, within 1 second, preferably within 50 ms. For electrophoretic displays operating at video rates or voltages below +/- 15 V, these ideal values should be correspondingly reduced. Similar considerations apply to other types of electro-optic displays.

In summary, remnant voltage as a phenomenon is at least substantially the result of ionic polarization occurring within display material components, either at interfaces or within the material itself. Such polarizations are problematic, particularly when they persist on meso-timescales of about 50 ms to about 1 hour or longer. Remnant voltage itself can manifest as image retention or visual artifacts in a variety of ways, with some severity that can vary with the time elapsed between image updates. Remnant voltage can also create DC imbalances, shortening the final display lifetime. The effects of remnant voltage are therefore detrimental to the quality of electrophoretic or other electro-optical devices, and it can be desirable to minimize both the remnant voltage itself and the sensitivity of the optical state of the device to the effects of remnant voltage.

In practice, charge that builds up in the electrophoretic material due to the polarization effects described above can be discharged or eliminated to reduce residual voltage effects. In some embodiments, such discharge can be performed after a refresh or drive sequence.

In some embodiments, the post-drive or post-refresh discharge may be implemented using a readily available thin film transistor (TFT) backplane 100 for the EPD and the EPD's controller circuitry, as illustrated in FIG. 1. In use, each display pixel may include a thin film transistor UPD (e.g., TFT _(upd) ) 102, which may be configured to provide a certain electrical conductivity such that the display's top plane 106 and source (or data) line VS are held at the same voltage potential (e.g., ground) for a certain period of time. The above-mentioned patent application Ser. No. 15/014,236 (incorporated herein in its entirety) discusses such drive methods in more detail. The display pixel 100 as illustrated herein and various embodiments illustrated below typically include an electrophoretic material 108 positioned between the pixel electrode 104 and the top plane 106, which may include a substrate and a common electrode, which may be a transparent conductive layer. Typically, the TFT _(upd) 102 is designed to function as a pixel control transistor for providing or transmitting a drive waveform to the pixel electrode 104 of the pixel. Thus, the TFT _(upd) 102 is typically configured to operate in a conductive state (i.e., "on" state) for a very short amount of time compared to the non-conductive state (i.e., "off" state), with a ratio of "on" time to "off" time of, for example, greater than 1:1,000. Use of the uPDD will change this ratio to about 1:2 or 1:50 depending on the uPDD configuration, which will lead to positive bias stress after extended use, in some cases comparable to the stress caused by image updates, typically tens of thousands of times or more. Positive bias stress is known to cause threshold voltage shifts in amorphous silicon TFTs that are permanent. The threshold voltage shift can lead to behavioral changes in the affected TFTs and TFT backplane, which in turn lead to optical shifts in the optical properties of the EPD. The optical shifts due to uPDD have been observed and are illustrated in Figures 2A and 2B. As shown, due to uPDD, the display graytone (Figure 2A) and afterimage shift (Figure 2B) values can increase significantly within two years after tens of thousands of refresh cycles.

In the case of using only a single TFT, such as TFT _(upd) 102 illustrated in FIG. 1, both normal image updating and uPDD are accomplished through the same TFT (i.e., TFT _(upd) ). Alternatively, in some embodiments, an additional TFT may be added to each pixel and used only for the uPDD discharge scheme. The overall discharge scheme remains the same, but the pixel TFT used for normal display operation (e.g., TFT _(upd) 102 in FIG. 1) would be used only for active display updating, as in standard active matrix driving of EPDs that do not incorporate a discharge. This configuration ensures that the performance of the pixel TFT used for normal display operation is stable and not affected by the discharge. Although the additional TFT used for discharge may incur a threshold voltage shift due to positive bias stress, it will not cause an optical shift in the EPD, which will not affect the discharge operation, as long as the TFT is turned on during discharge (i.e., the potential threshold voltage shift is taken into account by the discharge scheme). Such a configuration can enable stable display operation without optical response shift, while at the same time enabling the DC non-balanced waveform enabled by the post-drive discharge.

One exemplary embodiment according to the concepts described above is illustrated in FIG. 3. In addition to a standard pixel TFT (e.g., TFT _(upd) 302), the display pixel 300 may include an active component dedicated to clearing residual voltage or excess charge from the electrophoretic film 314. This active component may be any type of transistor (e.g., TFT, CMOS, etc.), or any other component that can be activated or turned on by application of electrical (e.g., voltage) or optical energy, i.e., a diode or a photodetector/diode, or any electrically/optically activated switch in general, or other such device. For purposes of illustrating the general concepts, a TFT (e.g., n-type TFT) is used herein, but it is understood that this is not meant to serve as a limitation. As illustrated in FIG. 3, a transistor designated TFT _(dis) 304 may be used for the purpose of releasing residual voltage charge in the electrophoretic imaging film 314. In this configuration, the gate of the TFT _(upd) 302 is connected to a select line (e.g., Vg(upd) 308) from the gate driver output, while the gate of the TFT _(dis) 304 is connected to a discharge select line such as Vg(dis) 306, which can be used to turn the TFT _(dis) 304 on and off at its gate (e.g., by supplying a voltage to the gate of the transistor through the select line to affect the gate-source or gate-drain potential). In one embodiment, all pixel discharge select lines for multiple pixels can be connected together to a single display output, such as to simultaneously turn on all pixel discharge TFT (e.g., TFT _(dis) 304) transistors of all display pixels of the display, for simultaneous discharging of the entire display. In some embodiments, both the source lines of the TFT _(upd) 302 and the TFT _(dis) 304 can be connected to a data line Vs 310. During operation, the TFT _(dis) 304 may be turned off for all pixels, while the TFT _(upd) 302 is used for active updating of the display. During discharging, the TFT _(dis) 304 may be turned on, while the TFT _(upd) 302 may be turned off. In some embodiments, one or both of the TFT _(upd) 302 and the TFT _(dis) 304 may be n-type transistors. In that case, the source of the TFT _(upd) 302 may be electrically coupled to the source line Vs 310, and the drain of the TFT _(upd) 302 may be coupled to the pixel electrode 312 of the display pixel 300. Additionally, if the TFT _(dis) 304 transistor is an n-type transistor, its source may be coupled to the source line Vs 310, while its drain may be coupled to the pixel electrode 312. Indeed, when the TFT _(dis) 304 is turned on and conducting, charge from the electrophoretic film 314 can be removed or released through the TFT _(dis) 304 and/or the source line Vs 310 .

FIG. 4 illustrates another embodiment of a display pixel 400 according to the subject matter presented herein. In this embodiment, the discharge TFT _(dis) 402 may be electrically coupled to the top plane 404 of the EPD (e.g., connected to the common electrode of the EPD) and to the Vcom 406 voltage line (e.g., the drain of the discharge TFT 402 is directly coupled to the top plane 404 of the EPD, while its source is coupled to the pixel electrode 408 of the pixel), as shown in FIG. 4. In this configuration, discharging of the display module does not occur through the source driver (e.g., Vs 410), but instead is directly through the top plane connection. In addition, in this setting, it is possible to discharge the display during updating by placing the discharge TFT _(dis) 402 in a weakly conductive state to act as a resistive or conductive path for discharging, because Vs 410 is not connected to the discharge TFT _(dis) 402 and therefore does not affect its operation in this case. In this configuration, the TFT _(dis) 402 may be activated through a select line Vg _(dis) 412, while the transistor TFT _(upd) 414 may be activated through a select line Vg _(upd) 416; the two select lines (i.e., Vg _(dis) 412 and Vg _(upd) 416) may optionally not be electrically coupled.

FIG. 5 illustrates an example voltage sequence that may be applicable to either of the two proposed pixel designs presented in FIGS. 3 and 4. This voltage sequence ignores potential RC time constraints that may appear, for example, when switching from one voltage to another, or that may be introduced during power down. _Vg(upd) is connected to a select line as in standard active matrix driving, and switches between high and low voltages to turn the TFTs on and off. During active updating, Vcom may be held constant, typically at a voltage equal to the kickback voltage of the TFT _(upd) . Vs is connected to a data line that provides a data signal to refresh the pixel with the desired waveform. _Vg(dis) is connected to a low voltage to keep the TFT _(dis) off. During discharge after active updating, Vg _(upd) is turned off and Vcom and Vs are held at 0V. _Vg(dis) is turned on to short the electrophoretic imaging film through TFT _(dis) . The voltage sequence shown in FIG. 5 is an exemplary illustration of the discharge scheme using the new TFT pixel design. This new TFT pixel design is flexible enough to accommodate more complex implementations of the discharge scheme. The idea is that the discharge occurs by turning on a dedicated TFT while leaving the pixel TFT apart from the discharge operation and used for normal display operation. Secondary effects may include the possibility that the kickback voltage experienced by the TFT _(dis) when turned off at the end of the discharge may affect the discharge effectiveness or optical properties of the display. Such effects may be mitigated by implementing a properly designed power-off circuit for Vg _(dis) with some RC damping to prevent or minimize such effects.

In the above description, both TFT _(upd) and TFT _(dis) are N-type TFTs. These transistors can also both be P-type TFTs or each can be N-type and P-type. One of the examples based on the circuit in FIG. 3 is shown in FIG. 6, where both TFT _(upd) 604 and TFT _(dis) 602 are P-type TFTs. The same can be done for the circuit in FIG. 4 (not shown here).

Alternatively, instead of active components such as TFTs, passive components can also be employed to discharge the EPD. Figure 7 shows another possible implementation of the subject matter presented herein, where a resistor _Rdis 702 is placed in parallel with the pixel's storage capacitor Cs 704. As shown, the resistor _Rdis 702 is also coupled to both the pixel electrode 706 and the common electrode 708. The purpose of this resistor is to provide a path for discharging residual voltage from the electrophoretic imaging film at the end of the drive period. The advantage of this pixel design is that it does not require adding an extra line _Vgdis to control the second TFT. However, since _Rdis 702 currently has a fixed resistance value, the resistance value of _Rdis 702 needs to be designed appropriately. For example, the RC constant associated with the addition of R _dis 702 to the pixel circuit, including the pixel electrode and storage capacitor, needs to be larger than the drive frame time to achieve the required pixel voltage retention characteristics during the frame time. This RC constant also needs to be low enough to provide sufficient discharge at the end of the drive period. In some other embodiments, R _dis 702 may be replaced with a field switchable shunt resistor using amorphous silicon or any other technology that provides an appropriate resistance in parallel with the electrophoretic imaging film for discharge that does not interfere with normal drive operation. In addition to providing a dedicated TFT used only for discharge and another TFT used only for display update to avoid optical shifts in display performance due to positive bias stress, the subject matter presented herein also enables several additional modes of use that may be beneficial, as described below.

8 shows an example voltage sequence applicable only to the circuit presented in FIG. 3, where TFT _upd 302 and TFT _dis 304 have dedicated gate lines. In this voltage sequence, both TFT _upd 302 and TFT _dis 304 are turned on during the active update phase, while TFT _dis 304 may or may not be turned on at the end of the update for discharging. In this mode of use, TFT _dis 304 may provide extra current for faster pixel charging, which may enable, for example, higher frame rate driving. Furthermore, TFT _dis 304 in the proposed pixel design may also be used as a global update transistor. By turning on TFT _dis 304 and turning off TFT _upd 302, a long-term positive bias on TFT _upd 302 may be prevented when a global update is performed.

9 illustrates another embodiment of the subject matter disclosed herein. Similar to the setup presented in FIG. 7, the display device 900 may use a resistor Rd 902 connected across the FPL 904 layer to release residual charge and/or voltage, thereby sparing the pixel TFT 906 from additional stress and device degradation induced by having to be turned on to release the residual charge. In some embodiments, the resistor Rd 902 may be placed in parallel with the storage capacitor Cs 908 to create a path for the residual charge to be removed. Alternatively, the storage capacitor Cs 908 itself may be configured to be "leaky" and provide a path for the residual charge to be removed. Here, the term "leaky" is defined as the dielectric resistance of a capacitor (e.g., Cs 908) decreasing to a point where the capacitor can ohmically conduct sufficient current to allow the residual charge to be removed or discharged.

In practice, the resistance of the resistor Rd or the dielectric resistance of the capacitor is 1/3 to 3 times the resistance of the FPL904 layer, or R _FPL /3<R D <R _FPL ×3.
where R _FPL is the resistance of the FPL 904 layer. Figures 10 and 11 illustrate some experimental data regarding the discharge of residual charge. Figure 10a shows an experimental setup where the FPL test glass is connected to an external circuit to simulate the effect of having a resistive path (Rd) in parallel with a storage capacitor (e.g., Cs = 7 nF/cm ² ) on an active matrix display. A DC unbalanced waveform driving at -15V for 25 frames is followed by a ground frame applied to the experimental circuit as illustrated in Figure 10b, or without a ground frame as illustrated in Figure 10c. Figure 10d illustrates that each frame consists of holding the FPL voltage VFPL at the desired level for 1 ms, followed by floating (i.e. no current is applied to the circuit) for 9 ms to simulate an active matrix driving scheme. In this case, the front plane laminate or FPL layer as described herein may include a light-transmissive conductive layer, a layer of a solid electro-optic medium in electrical contact with the conductive layer, an adhesive layer, and a release sheet. In some other embodiments, the FPL layer may include a separate light-transmissive conductive layer in place of a release sheet.

The resulting measured FPL voltages are presented in Figures 11a-e, where Figure 11a illustrates the FPL voltage measured during the drive phase, Figure 11b illustrates the brightness of the display during the drive phase, Figure 11c illustrates the FPL voltage measured during the floating phase, Figure 11d illustrates the brightness during the floating phase, and Figure 11e illustrates the FPL voltage (i.e., residual charge) measured at the end of the floating phase for four different Rd values and two different test waveforms.

From experimental data, it can be observed that a smaller Rd resistance value may result in a faster decay of the FPL voltage during the floating phase, resulting in a smaller accumulation of residual voltage. However, it is also desirable to have Rd not too small, which would cause a degradation of the ink switching speed during the driving phase due to the storage capacitor Cs being discharged very quickly, which may cause more optical kickback during the floating phase. Therefore, since the capacitance of the storage capacitor is usually chosen to be sufficient to maintain the FPL voltage during the frame time (Cs x R _FPL >> frame time), the resistance value of Rd is preferably not too small compared to the FPL resistance value R _FPL to prevent a rapid discharge of the FPL voltage during the frame time, which may cause a loss of ink velocity during the driving phase. Of course, the resistance value of Rd cannot be too large compared to that of R _FPL , otherwise the advantage of having this passive discharge path is reduced.

In some embodiments, the resistance of Rd or the ohmic resistance of the storage capacitor is:
R _FPL /3<Rd<R _FPL ×3
10% to 120% of the R _{FPL value, or the ohmic resistance of the storage capacitor may be configured to be 70% to 130% of the R FPL value} , or the ohmic resistance of the storage capacitor may be configured to be 50% to 150% of the R _FPL value, or the ohmic resistance of the storage capacitor may be configured to be approximately one-third to three times _{the R FPL value} . Additionally, as illustrated in FIG. 11e, this configuration eliminates the need to terminate the waveform at a ground _frame while still allowing for the release of residual voltage. For example, referring again to Fig. 11e, for an FPL with a resistance of about ²⁴ MΩcm2, an Rd of about ¹⁵ MΩcm2, with Rd = ∞, can achieve an 80% reduction in residual voltage build-up even when the waveform is not terminated at a ground frame compared to when the waveform is terminated at a ground frame. In addition, this configuration also reduces optical kickback, allowing the white state to be whiter (see Fig. 11d), thereby achieving a better contrast ratio.

In some embodiments, the Rd discharge path described herein may be achieved by making the pixel storage capacitor "leaky" such that the dielectric resistance of the storage capacitor is reduced to the point where the capacitor can ohmically conduct sufficient current to allow residual charge to be eliminated or released. Referring now to FIG. 12, a display pixel 1200 may include a pixel TFT 1202 positioned on a glass substrate 1206 and adjacent to a storage capacitor 1204. In this case, the TFT 1202 may include a source 1206, a drain 1210, and a gate 1212. The storage capacitor 1204 may be connected to the drain 1210 of the TFT 1202 through a pixel electrode 1214 (e.g., ITO). In this configuration, the storage capacitor 1204 may be doped, for example, with a dopant to sufficiently reduce its dielectric resistance to allow residual charge to be released.

Alternatively, an additional capacitor may be added to the display pixel to create a path for releasing the residual voltage, the additional capacitor may be configured to be leaky. Referring now to FIG. 13, a discharge capacitor 1302 may be positioned in parallel with the storage capacitor 1304, the discharge capacitor 1302 may be configured to be leaky so that it can ohmically conduct sufficient current to allow the residual charge to be discharged. In practice, referring now to FIG. 14, a discharge capacitor 1400 may be positioned on the same substrate 1402 and adjacent to the storage capacitor 1404 and the pixel TFT 1406. The TFT 1406 may have a source 1408, a drain 1410, and a gate 1412, the drain 1410 may be electrically coupled to the discharge capacitor 1400 and the storage capacitor 1404 through a pixel electrode 1414.

It will be apparent to those skilled in the art that numerous changes and modifications can be made to the specific embodiments of the invention described above without departing from the scope of the invention. Therefore, the entirety of the foregoing description should be interpreted in an illustrative rather than a limiting sense.

Claims (4)

1. An electrophoretic display having a plurality of display pixels, each of the plurality of display pixels comprising:
a pixel electrode for driving the display pixel;
a single thin film transistor (TFT) coupled to said pixel electrode for transmitting a waveform to said pixel electrode;
a front plane laminate (FPL) coupled to the single thin film transistor;
a storage capacitor coupled to the pixel electrode, the storage capacitor being placed in parallel with the FPL;
An electrophoretic display, wherein the storage capacitor is configured such that its dielectric resistance is approximately the same as a resistance of the FPL to allow release of residual voltage from the FPL through the storage capacitor . 10. The electrophoretic display of claim 1 further comprising a discharge capacitor in parallel with the storage capacitor. The electrophoretic display of claim 1, wherein the FPL comprises an electrophoretic material. 4. An electrophoretic display as claimed in claim 3 , wherein the electrophoretic material comprises an encapsulated electrophoretic material containing charged pigment particles in a fluid medium.

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