JP7645138B2 - Method for manufacturing hard mask and method for manufacturing solar cell - Google Patents

Description

The present invention relates to a method for manufacturing a hard mask, a method for manufacturing a solar cell, and an ion implantation device.

In recent years, among solar cells using crystalline silicon as a substrate (hereinafter also referred to as crystalline solar cells), the structure that has been attracting attention for its improved power generation efficiency is the TOPCon (Tunnel Oxide Passivating Contacts) structure, which uses silicon oxide (SiO _x ) and amorphous silicon (a-Si) layers as a passivation layer.

At EUPVSEC 2018, ISFH in Germany reported a power generation efficiency of 26.1% (an EU record) using POLO (polycrystalline silicon on oxide)-IBC, which has a similar structure to the TOPCon-IBC (Tunnel Oxide Passivating Contact-Interdigitated Back Contact) structure (Non-Patent Document 1). Fraunhofer ISE in Germany also reported a power generation efficiency of 26.0% using the TOPCon structure (Non-Patent Document 2). Mass production of crystalline solar cells using the TOPCon structure is currently being considered in China and other countries.

In a TOPCon-IBC solar cell, an n-type silicon region and a p-type silicon region are arranged so as to be spaced apart on the back surface of the silicon substrate (the surface opposite the light-receiving surface). To obtain a configuration in which an n-type region and a p-type region are arranged in the same silicon layer, a film-forming process, a masking process using photolithography, and an etching process are repeated multiple times in a TOPCon-IBC crystalline solar cell. Also, in the TOPCon structure, a p-layer or n-layer is selectively formed in high concentration only on the lower part of the electrode on the light-receiving surface side, so a similar process as above is used.

"Laser contact openings for local poly-Si-metal contacts enabling 26.1%-efficient POLO-IBC solar cells", Solar Energy Materials and Solar Cells186(2018)184-193 "Design rules for high-efficiency both-sidescontacted silicon solar cells with balanced charge carrier transport and recombination losses", Nature energy VOL 6 April 2021 429-438

However, when forming p and n layers locally as described above, or when manufacturing p or n layers with high concentration locally, the number of manufacturing steps increases, which may lead to increased costs for the manufacturing line. In addition, with TOPCon-IBC, the distance between the backside p and n layers must be aligned to within an alignment accuracy of ±30 μm.

In view of the above circumstances, the object of the present invention is to provide a method for manufacturing a hard mask, a method for manufacturing a solar cell, and an ion implantation device that suppresses cost increases in solar cell manufacturing lines.

In order to achieve the above object, a method for manufacturing a hard mask according to one embodiment of the present invention includes the steps of:
a plate-like substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface being provided with a recess;
A reinforcing plate is accommodated in the recess via an adhesive layer,
a pattern area portion having an opening penetrating to the recess is formed in the second main surface opposite to the recess,
The reinforcing plate and the adhesive layer are removed from the recess.

This method of manufacturing a hard mask can reduce the cost increase of a solar cell manufacturing line and can precisely control the ion implantation region in the solar cell.

In the above-mentioned method for manufacturing a hard mask, a silicon substrate may be used as the substrate.

In the method for manufacturing the hard mask, a surface alignment process between the auxiliary plate and the first main surface may be performed before the pattern area portion is formed on the second main surface.

This method of manufacturing a hard mask makes it possible to produce a hard mask that is free of cracks and chips.

In the above-mentioned method for manufacturing a hard mask, the pattern area may be formed using a dicing blade.

This method of manufacturing a hard mask allows hard masks to be manufactured at low cost.

In the above-mentioned method for manufacturing a hard mask, a crystalline silicon substrate may be used as the silicon substrate.

This method of manufacturing a hard mask makes it possible to produce a hard mask with little variation in the width of the opening pattern.

In order to achieve the above object, a method for producing a solar cell according to one embodiment of the present invention includes the steps of:
a hard mask is prepared, the hard mask having a first main surface and a second main surface opposite to the first main surface, the first main surface being provided with a recess, and the second main surface opposite to the recess being provided with a pattern region having an opening penetrating to the recess;
Using a hard mask on the main surface side of the crystalline silicon substrate, an impurity element of a first conductivity type or an impurity element of a second conductivity type is selectively implanted into a silicon layer formed on the main surface by ion implantation.

This method of manufacturing solar cells makes it possible to selectively implant p- and n-layers, or selectively increase the concentration of one type of dopant. It also makes it possible to suppress cost increases in solar cell manufacturing lines and to precisely control the ion implantation regions in solar cells.

In the above solar cell manufacturing method, the hard mask may be made of silicon.

In the method for manufacturing a solar cell, at least two of the hard masks are prepared,
One hard mask may be used to selectively inject an impurity element of a first conductivity type into the silicon layer to form a first region of the first conductivity type in the silicon layer, and the other hard mask may be used to selectively inject an impurity element of a second conductivity type into the silicon layer in which the first region is not formed, to form a second region of the second conductivity type in the silicon layer.

This method of manufacturing a solar cell makes it possible to change the width of each of the first and second regions independently.

In the above-mentioned method for manufacturing a solar cell, the second region may be arranged in parallel with the first region, and the distance between the first region and the second region may be set to 5 μm or more and 100 μm or less.

This method of manufacturing a solar cell allows for precise control of the distance between the first and second regions.

In order to achieve the above object, an ion implantation apparatus according to one aspect of the present invention comprises:
A support table capable of supporting a substrate;
The hard mask;
an ion implantation source for implanting ions into the substrate through the hard mask.

This type of ion implantation device can reduce cost increases in solar cell manufacturing lines and accurately control the ion implantation area in solar cells.

In the above ion implantation apparatus, the hard mask may be made of silicon.

As described above, the present invention provides a hard mask manufacturing method, a solar cell manufacturing method, and an ion implantation device that suppresses cost increases in solar cell manufacturing lines.

1 is a schematic configuration diagram of a solar cell manufactured by a solar cell manufacturing method according to an embodiment of the present invention. 1 is a schematic diagram of an ion implantation apparatus applied to a method for manufacturing a solar cell according to an embodiment of the present invention. 1A is a schematic plan view of a hard mask according to an embodiment of the present invention, and FIGS. 1B and 1C are schematic cross-sectional views of the hard mask according to the embodiment of the present invention. 5A to 5C are schematic cross-sectional views illustrating a manufacturing process of the hard mask according to the embodiment. 5A to 5C are schematic cross-sectional views illustrating a manufacturing process of the hard mask according to the embodiment. 1A to 1C are schematic plan views illustrating a manufacturing process of a hard mask according to an embodiment of the present invention. 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a solar cell according to an embodiment of the present invention. 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing a solar cell according to an embodiment of the present invention.

Below, an embodiment of the present invention will be described with reference to the drawings. XYZ axis coordinates may be introduced in each drawing. In addition, the same reference numerals may be used for identical components or components having the same functions, and after the components have been described, the description may be omitted as appropriate. In addition, the numerical values shown below are examples and are not limited to these examples.

[Solar cells]

Figure 1 is a schematic diagram of a solar cell manufactured by the solar cell manufacturing method according to this embodiment.

The solar cell 100 shown in FIG. 1 is a TOPCon-IBC type crystalline solar cell. The solar cell 100 comprises an n-type (first conductivity type) crystalline silicon substrate 110, a silicon layer 111, an n-type region (first region) 111n, a p-type region (second region) 111p, a protective layer 112, a protective layer 120, an n-side electrode 130n, and a p-side electrode 130p.

An n-side electrode 130n is connected to the n-type region 111n. A p-side electrode 130p is connected to the p-type region 111p. The n-side electrode 130n or the p-side electrode 130p contains, for example, at least one of silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), etc., or a mixture of the above metals.

In the solar cell 100, the light receiving surface is located on the opposite side to the back surface 110a of the crystalline silicon substrate 110. For example, the front surface 110b of the crystalline silicon substrate 110 has an uneven structure (textured structure) to efficiently capture sunlight. On the front surface 110b, protective layers 112, 120 are provided along the uneven surface of the front surface 110b, which also function as anti-reflection films to suppress light loss due to reflection of sunlight.

The solar cell 100 receives sunlight from the surface 110b of the crystalline silicon substrate 110, and an electrode structure (back electrode structure) is provided on the opposite side to the surface 110b. As a result, the solar cell 100 has a structure in which the electrodes are not on the light-receiving surface, and shadow loss of sunlight due to the electrodes is suppressed.

A silicon layer 111 is provided on the back surface 110a of the crystalline silicon substrate 110. The thickness d1 of the silicon layer 111 is, for example, 5 nm or more and 200 nm or less. In this embodiment, a non-mass-separated ion implantation method (plasma doping method) is used to form an n-type region 111n and a p-type region 111p in the silicon layer 111. The non-mass-separated ion implantation method can implant impurity elements over a large area, improving the throughput in solar cell manufacturing.

As long as the impurity element is introduced into the silicon layer 111 in an ion state, the method is not limited to the non-mass-separated ion implantation method, and a mass-separated ion implantation method is also possible. In the following explanation, the non-mass-separated ion implantation method is used as a representative example of an impurity introduction method and will be described in detail. For simplicity, the non-mass-separated ion implantation will be referred to as "ion implantation". Next, an apparatus for performing ion implantation will be described.

[Ion implantation device]

Figure 2 is a schematic diagram of an ion implantation device that is used in the solar cell manufacturing method according to this embodiment.

The ion implantation device 1000 includes a vacuum chamber 1001 (lower vacuum chamber), a vacuum chamber 1002 (upper vacuum chamber), an insulating member 1003, a support stand 1004, a gas supply source 1005, and a hard mask 10. The ion implantation device 1000 further includes an RF introduction coil 1100, a permanent magnet 1101, an RF introduction window (quartz window) 1102, an electrode 1200, an electrode 1201, a DC power supply 1300, and an AC power supply 1301.

The vacuum chamber 1002 has a smaller diameter than the vacuum chamber 1001 and is provided on the vacuum chamber 1001 via an insulating member 1003. The vacuum chamber 1002 is an ion implantation source that implants ions into the substrate S1 through the hard mask 10. The vacuum chambers 1001 and 1002 can be maintained in a reduced pressure state by a vacuum exhaust means such as a turbo molecular pump. The support table 1004 is provided in the vacuum chamber 1001. The support table 1004 can support the substrate S1. A heating mechanism for heating the substrate S1 may be provided in the support table 1004. The substrate S1 is a semiconductor wafer, a glass substrate, or the like for manufacturing the solar cell 100. In addition, a gas for ion implantation is introduced into the vacuum chamber 1002 by a gas supply source 1005.

The support table 1004 can support the substrate S1. The substrate S1 is placed on the support table 1004 with the back surface 110a shown in FIG. 1 facing the vacuum chamber 1002. A hard mask 10 is placed between the substrate S1 and the vacuum chamber 1002. The ion implantation device 1000 may be provided with a mask movement mechanism (not shown) for replacing the hard mask 10 with another hard mask or for changing the distance between the hard mask 10 and the substrate S1. For example, the distance between the hard mask 10 and the substrate S1 can be set to 0 mm to 5 mm.

The RF introduction coil 1100 is arranged on the RF introduction window 1102 so as to surround the permanent magnet 1101. The permanent magnet 1101 is shaped like a ring. The RF introduction coil 1100 is shaped like a coil. The diameter of the RF introduction coil 1100 can be set appropriately according to the size of the substrate S1. When gas for ion implantation is introduced into the vacuum chamber 1002 and a predetermined power is supplied to the RF introduction coil 1100 from the AC power source 1301, plasma 1010 is generated in the vacuum chamber 1002 by ICP (Inductively Coupled Plasma) discharge.

The electrode 1200 is an electrode (e.g., a mesh electrode) having multiple openings, and is supported by the insulating member 1003. The potential of the electrode 1200 is a floating potential. This generates a stable plasma 1010 in the space surrounded by the vacuum chamber 1002 and the electrode 1200.

Under the electrode 1200, another electrode (e.g., a mesh electrode) 1201 having a number of openings is disposed. The electrode 1201 faces the substrate S1. A DC power supply 1300 is connected between the electrode 1201 and the RF induction coil 1100, and a negative potential (acceleration voltage) is applied to the electrode 1201. As a result, positive ions in the plasma 1010 are extracted from the plasma 1010 by the electrode 1201.

The extracted positive ions can pass through the mesh electrodes 1200 and 1201 and reach the substrate S1 (silicon layer 111). In the ion implantation device 1000, the acceleration voltage of the positive ions can be set, for example, in the range of 1 kV to 30 kV. In addition, a bias power supply capable of adjusting the acceleration voltage may be connected to the support table 1004.

A gas containing an impurity element (n-type impurity element or p-type impurity element) to be implanted into the substrate S1 is introduced into the vacuum chamber 1002. A plasma 1010 is formed in the vacuum chamber 1002 by this gas, and n-type impurity ions or p-type impurity ions in the plasma 1010 are implanted into the substrate S1. The n-type impurity ions are, for example, at least one of P, PX ⁺ , PX ₂ ⁺ , PX ₃ ⁺ , etc. Here, "X" is either hydrogen or halogen (F, Cl). The p-type impurity ions are, for example, at least one of B ⁺ , BY ⁺ , BY ₂ ⁺ , BY ₃ ⁺ , B ₂ Y ₂ ⁺ , B ₃ Y ₂ ⁺ , B ₄ Y ₂ ⁺ , etc. Here, "Y" is either hydrogen or halogen (F, Cl).

The concentrations of the impurity elements in the n-type region 111n and the p-type region 111p are adjusted so that the conductivity of the n-type region 111n and the p-type region 111p is optimized. However, the concentration of the impurity element implanted in the n-type region 111n is set to be higher than the concentration of the n-type impurity element in the crystalline silicon substrate 110.

In this embodiment, the means for forming the plasma 1010 is not limited to the ICP method, but may also be an electron cyclotron resonance plasma method, a helicon wave plasma method, or the like.

In addition, in this embodiment, when an impurity element is implanted into the silicon layer 111, a gas containing hydrogen (e.g., _PH3 , _BH2 , etc.) may be added to the gas for ion implantation. This allows hydrogen to be implanted into the silicon layer 111, and structural defects in the silicon layer 111 are repaired. This suppresses recombination of carriers in the structural defects, and increases the total amount of carriers that reach the n-type region 111n and the p-type region 111p. This improves the photoelectric conversion efficiency and increases the open circuit voltage ( _Voc ).

[Hard Mask]

FIG. 3(a) is a schematic plan view of a hard mask according to this embodiment. FIGS. 3(b) and 3(c) are schematic cross-sectional views of a hard mask according to this embodiment. FIG. 3(b) shows a cross section taken along line A1-A2 in FIG. 3(a). FIG. 3(c) shows a cross section taken along line A3-A4 in FIG. 3(a).

The hard mask 10 is made of crystalline silicon. The hard mask 10 is not limited to crystalline silicon, and may be made of graphite. Below, the hard mask 10 will be described using crystalline silicon as an example.

The planar shape of the hard mask 10 is, for example, an octagon. The planar shape is not limited to an octagon, and may be a polygon such as a rectangle or a hexagon. The hard mask 10 has a main surface 11 (first main surface), a main surface 12 (second main surface) opposite the main surface 11, a recess (countersink) 13 provided in the main surface 11, a pattern area 15 provided in the main surface 12, and a thick peripheral portion 14 surrounding the pattern area 15 and the recess 13.

The recess 13 is dug down from the main surface 11 and is located, for example, in the center of the hard mask 10. The planar shape of the recess 13 is a rectangle surrounded by a pair of opposing long sides 13La, 13Lb and a pair of opposing short sides 13Sa, 13Sb. The depth of the recess 13 is shallower than the thickness of the hard mask 10. Here, the direction in which the long sides 13La, 13Lb extend is the first direction, and the direction in which the short sides 13Sa, 13Sb extend is the second direction. The first direction and the second direction are approximately perpendicular to each other.

A pattern area 15 having an opening 15h penetrating to the recess 13 is provided on the main surface 12 opposite the recess 13. A plurality of openings 15h are provided in the pattern area 15. The line width of each of the plurality of openings 15h is substantially the same. The plurality of openings 15h are arranged side by side in the first direction. For example, each of the plurality of openings 15h is arranged side by side periodically in the first direction. Also, each of the plurality of openings 15h extends linearly along the second direction. In the hard mask 10, a line-and-space opening pattern is formed by the plurality of openings 15h.

The multiple openings 15h are arranged in the pattern area 15 in a number of 10 to 1700. The line width of the openings 15h is set to, for example, 10 μm to 600 μm. When the multiple openings 15h are arranged periodically in the first direction, the pitch of the openings 15h is set to, for example, 300 μm to 4000 μm. The thickness of the pattern area 15 (or the depth of the openings 15h) is set to, for example, 0.2 mm to 10.0 mm, e.g., 0.4 mm.

Each of the multiple openings 15h is connected to grooves 15ta and 15tb provided in the peripheral portion 14 surrounding the pattern region portion 15. Each of the multiple openings 15h is provided between grooves 15ta and 15tb in the second direction. Each of grooves 15ta and 15tb extends in the second direction. Groove 15ta extends from the pattern region portion 15 to end 10ea of the hard mask 10 facing the long side 13La. Groove 15tb extends from the pattern region portion 15 to end 10eb of the hard mask 10 facing the long side 13Lb.

The grooves 15ta and 15tb do not penetrate from the main surface 12 to the main surface 11 of the hard mask 10, but are bottomed grooves in the peripheral portion 14. The depth and line width of the opening 15h and the grooves 15ta and 15tb are substantially the same. That is, when an arbitrary opening 15h is selected from the pattern area portion 15, a single linear space groove 15s is formed by the opening 15h and a pair of grooves 15ta and 15tb that communicate with both ends of the opening 15h. In addition, multiple space grooves 15s are arranged side by side in the first direction in the hard mask 10.

FIGS. 4(a) to 5(c) are schematic cross-sectional views illustrating the manufacturing process of the hard mask according to this embodiment, and FIG. 6 is a schematic plan view illustrating the manufacturing process of the hard mask according to this embodiment.

As shown in FIG. 4(a), a plate-shaped substrate having a main surface 11 and a main surface 12 opposite to the main surface 11, for example, a silicon substrate 10s, is prepared, and then a recess 13 is formed in the main surface 11 of the silicon substrate 10s. A crystalline silicon substrate such as a silicon wafer is used as the original substrate of the silicon substrate 10s in which the recess 13 is formed. The planar shape of the silicon substrate 10s is the same as the planar shape of the hard mask 10 shown in FIG. 3(a). A graphite substrate may also be used as the plate-shaped substrate.

The recess 13 is formed by a method such as grind polishing, dry etching, or wet etching. The thickness of the silicon substrate 10s (crystalline silicon substrate) is, for example, 0.5 mm to 20 mm. The depth of the recess 13 is 0.2 mm to 10 mm. By forming the recess 13 in the silicon substrate 10s, a peripheral portion 14 surrounding the recess 13 and a region 15a having a smaller thickness than the peripheral portion 14 are formed in the silicon substrate 10s. The thickness of the region 15a corresponds to, for example, the thickness of the pattern region 15. The region 15a is replaced with the pattern region 15 by processing described below.

Next, as shown in FIG. 4(b), an adhesive layer 20 is placed in the recess 13, and the reinforcing plate 30 is placed in the recess 13 via the adhesive layer 20. The material of the reinforcing plate 30 is the same as the material of the silicon substrate 10s.

Here, if the thickness d2 of the peripheral portion 14 is different from the thickness d3 from the main surface 12 to the non-adhesive surface (exposed surface) 30s of the reinforcing plate 30, and there is a step between the peripheral portion 14 and the reinforcing plate 30 on the main surface 11 side, a polishing process is performed on the main surface 11 or the non-adhesive surface 30s before forming the pattern area portion on the main surface 12, and the main surface 11 and the non-adhesive surface 30s are aligned.

For example, in the state of FIG. 4(b), if d2>d3, as shown in FIG. 4(c), grind polishing is performed on the main surface 11 side, and the main surface 11 and the non-bonding surface 30s are surface-aligned so that d2 and d3 are approximately the same. In this case, if the material of the reinforcing plate 30 and the material of the silicon base 10s are the same, one will not be preferentially polished. Furthermore, if the material of the reinforcing plate 30 and the material of the silicon base 10s are the same, the same polishing tool can be used, and there is no need to prepare separate polishing materials for the reinforcing plate 30 and the silicon base 10s.

Next, as shown in FIG. 4(d), the silicon substrate 10s with the reinforcing plate 30 attached thereto is placed on an adhesive base (dicing sheet) 40. The main surface 11 and the reinforcing plate 30 come into contact with the base 40.

Next, the space groove 15s shown in FIG. 3(a) is formed on the main surface 12 side of the silicon substrate 10s by the dicing blade 50. The depth of the space groove 15s is at least the thickness of the pattern region 15. In addition, since the reinforcing plate 30 is accommodated in the recess 13 when the space groove 15s is formed, even if the dicing blade 50 abuts against the thin region 15a, the mechanical strength of the region 15a is ensured. As a result, the space groove 15s is formed on the main surface 12 side of the silicon substrate 10s without cracking or chipping the silicon substrate 10s. In addition, since the thickness of the peripheral portion 14 and the thickness from the main surface 12 to the non-adhesive surface 30s of the reinforcing plate 30 are approximately the same, even if the dicing blade 50 is pressed against the main surface 12, unnecessary stress is not applied to the portion between the peripheral portion 14 and the region 15a, and the silicon substrate 10s is less likely to crack or chip.

As a result, as shown in FIG. 5(a), an opening 15h penetrating all the way to the recess 13 is stably formed in the main surface 12 on the side opposite the recess 13. Note that a plurality of space grooves 15s may be formed, for example, from left to right in FIG. 5(a) or from right to left. Alternatively, they may be formed first from the center of the recess 13, and then formed symmetrically on both sides starting from the center.

As a result, as shown in FIG. 5(b), the dicing blade 50 forms a silicon substrate 10s on which the pattern area 15 is formed. Thereafter, as shown in FIG. 5(c), the silicon substrate 10s is separated from the dicing blade 50, and the silicon substrate 10s is immersed in a chemical solution, thereby removing the reinforcing plate 30 and the adhesive layer 20 from the recess 13. As a result, the hard mask 10 is formed.

When forming the space grooves 15s, the space grooves 15s may be formed using a dicing blade 50 having the same thickness and line width as the space grooves 15s. In this case, one space groove 15s is formed with each pass of the dicing blade 50. Alternatively, as shown in FIG. 6, a dicing blade thinner than the line width of the space grooves 15s may be used to move the dicing blade back and forth multiple times over one space groove 15s to form the space grooves 15s.

For example, as shown in FIG. 6, when forming one space groove 15s using a dicing blade having a width of about one-third the line width of the space groove 15s, groove portion 15-1 and groove portion 15-2 corresponding to both sides of the space groove 15s may be ground in advance, and groove portion 15-3 corresponding to the center of the space groove 15s may be ground last. With this method, the load (stress) applied to the silicon substrate 10s by the dicing blade is alleviated, and a space groove 15s without cracks or chips is formed. In this way, a space groove 15s having the desired line width may be finally formed.

[How solar cells are manufactured]

Figures 7(a) to 8(b) are schematic cross-sectional views illustrating the manufacturing method of the solar cell of this embodiment.

First, a hard mask 10 is prepared, and as shown in FIG. 7(a), the hard mask 10 is placed opposite the main surface 111a of the silicon layer 111. Here, the main surface 12 opposite the recess 13 of the hard mask 10 is placed opposite the main surface 111a. Note that a known texture forming technique may be used for the surface 110b of the crystalline silicon substrate 110.

Next, using the hard mask 10, n-type impurity elements or p-type impurity elements are selectively implanted into the silicon layer 111 by ion implantation.

For example, as shown in FIG. 7B, n-type impurity ions 200n are selectively implanted into the main surface 111a of the silicon layer 111 exposed from the opening 15h. The n-type impurity ions 200n are, for example, phosphorus (P) ions. For example, a gas containing an n-type impurity is introduced into the vacuum chamber 1002, and plasma is generated by this gas. Then, when the n-type impurity ions 200n are irradiated onto the main surface 111a of the silicon layer 111 through the hard mask 10 by the ion implantation method, some of the n-type impurity ions 200n pass through the opening 15h of the hard mask 10. The n-type impurity ions 200n that have passed through the opening 15h are selectively implanted into a predetermined region of the silicon layer 111.

8(a), the hard mask 10 is moved laterally to position the opening 15h at the position where the p-type region 111p is to be formed. Next, the gas containing n-type impurities is switched to gas containing p-type impurities, and plasma is generated by the gas containing p-type impurities in the vacuum chamber 1002. Then, when p-type impurity ions 200p are irradiated to the main surface 111a of the silicon layer 111 through the hard mask 10 by the ion implantation method, a part of the p-type impurity ions 200p is selectively implanted into the silicon layer 111 exposed from the opening 15h. The p-type impurity ions 200p are, for example, boron (B) ions. The p-type region 111p is arranged in parallel with the n-type region 111n in the Y-axis direction in a region where the n-type region 111n of the silicon layer 111 is not formed. Note that an ion implantation device for implanting n-type impurities and an ion implantation device for implanting p-type impurities may be prepared separately. In this case, the implantation of n-type impurities and the implantation of p-type impurities are carried out using different ion implantation devices.

The distance between the n-type region 111n and the p-type region 111p is set to 5 μm or more and 100 μm or less. This allows the distance between the n-type region 111n and the p-type region 111p to be set within the above range, making it possible to add a p-side electrode 130p or an n-side electrode 130n.

Next, as shown in FIG. 8(b), protective layer 112 and protective layer 120 are formed on crystalline silicon substrate 110 by CVD, sputtering, or the like. After that, as shown in FIG. 1, n-side electrode 130n connected to n-type region 111n is formed in n-type region 111n. Also, p-side electrode 130p connected to p-type region 111p is formed in p-type region 111p.

At least two hard masks 10 with different line widths of the openings 15h may be prepared. In this case, one hard mask 10 is used to selectively inject an n-type impurity element into the silicon layer 111 to form an n-type region 111n in the silicon layer 111. The other hard mask 10 is used to selectively inject a p-type impurity element into the silicon layer 111 in which the n-type region 111n is not formed, to form a p-type region 111p in the silicon layer 111. With this method, the n-type region 111n and the p-type region 111p with different widths in the Y-axis direction can be formed in the silicon layer 111 without repeating the photolithography process and the etching process multiple times.

According to this manufacturing method, it is no longer necessary to repeat the film formation process, photolithography process, and etching process multiple times to form the n-type region 111n and the p-type region 111p in order to form the back electrode structure, thereby further reducing the number of manufacturing processes required to manufacture a solar cell.

The hard mask 10 is not formed by a process in which the photolithography step and the etching step are each repeated multiple times, but is simply formed by mechanical processing using a dicing blade 50. This allows the hard mask 10 to be formed at low cost. Furthermore, if the space groove 15s is formed by laser processing, a phenomenon may occur in which a portion of the space groove 15s is locally dissolved. In this embodiment, mechanical processing using a dicing blade 50 is used, so this phenomenon does not occur.

The manufacturing method of this embodiment is applicable not only to solar cells of the TOPCon-IBC type, but also to TOPCon structures. In this case, in the TOPCon structure, a high-concentration p-layer or n-layer is selectively formed under the electrode on the light-receiving surface side, so the wafer process for the back surface 110a side described using the TOPCon-IBC type is applied to the wafer process for the front surface 110b side. In this embodiment, the back surface 110a and front surface 110b of the solar cell are collectively referred to as the main surface.

The processing accuracy of the line width of the opening 15h and the ion implantation results when a mask made of graphite (Example 1) and a mask made of crystalline silicon (Example 2) are used as the hard mask 10 are shown below.

Table 1 shows the results when the material of the hard mask is graphite, and Table 2 shows the results when the material of the hard mask is crystalline silicon. In both Tables 1 and 2, the opening 15h is formed with a dicing blade. The ions implanted into the crystalline silicon substrate using these hard masks are phosphorus (P) (10 Kev, 1×10 ¹⁶ ions/cm ² ).

The target line width of the openings of the graphite mask shown in Table 1 is 200 μm, the number of openings is 98, and the pitch is 1.6 mm. The target line width of the openings of the silicon mask shown in Table 2 is 260 μm, the number of openings is 161, and the pitch is 0.96 mm. The variation values in Tables 1 and 2 are expressed as ((max value - min value) / (max value + min value)) x 100 (%).

In the graphite mask shown in Table 1, the variation in the line width of the openings is 7.7%. Furthermore, using a mask with this variation, the variation in the implantation region width of the region implanted with phosphorus is 9.7%. One reason for this variation is thought to be that the graphite mask is made of polycrystalline graphite, and the particle size is relatively large.

In contrast, with the crystalline silicon mask shown in Table 2, the variation in the line width of the opening is 0.4%, a significant improvement. Furthermore, using this mask, the variation in the implantation region width of the region implanted with phosphorus is 0.5%. Because the crystalline silicon mask is made of single crystal silicon, the variation in the line width of the opening is extremely small compared to the graphite mask, and by using a crystalline silicon mask, solar cells with extremely small variation in the implantation region width can be manufactured.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made. For example, the TOPCon-IBC structure has been described in this embodiment, but the present invention can also be adopted in a TOPCon structure in which an n-type region and a p-type region are formed under the light-receiving surface electrode. Each embodiment is not limited to being an independent form, and can be combined as far as technically possible.

10...Hard mask 10s...Silicon substrate 10ea, 10eb...End 11, 12...Main surface 13...Concave 13La, 13Lb...Long side 13Sa, 13Sb...Short side 14...Periphery 15...Pattern area 15a...Area 15h...Opening 15t...Groove 15s...Space groove 15-1, 15-2, 15-3...Groove 20...Adhesive layer 30...Reinforcing plate 30s...Non-adhesive surface 40...Base 50...Dicing blade 100...Solar cell 110...Crystalline silicon substrate 110a...Back surface 110b...Front surface 111...Silicon layer 111a, 111b...Main surface 111n...n-type region 111p...p-type region 112, 120...Protective layer 130p...p-side electrode 130n...n-side electrode 200n...n-type impurity ion 200p...p-type impurity ion 1000...ion implantation apparatus 1001, 1002...vacuum chamber 1003...insulating member 1004...support stand 1005...gas supply source 1010...plasma 1100...RF introduction coil 1101...permanent magnet 1102...RF introduction window 1200, 1201...electrode 1300...DC power supply 1301...AC power supply S1...substrate

Claims (9)

a plate-like substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface being provided with a recess;
A reinforcing plate is placed in the recess via an adhesive layer,
forming a pattern area portion having an opening penetrating to the recess on the second main surface opposite to the recess;
removing the reinforcing plate and the adhesive layer from the recess. 2. A method for manufacturing a hard mask according to claim 1, comprising the steps of:
The method for producing a hard mask, wherein the substrate is a silicon substrate. A method for producing the hard mask according to claim 1 or 2, comprising the steps of:
a surface alignment process for aligning the reinforcing plate with the first main surface before forming the pattern area on the second main surface. A method for producing a hard mask according to any one of claims 1 to 3, comprising the steps of:
The method for manufacturing a hard mask, wherein the pattern area is formed by using a dicing blade. A method for manufacturing a hard mask according to claim 2, comprising the steps of:
The method for producing a hard mask, wherein a crystalline silicon substrate is used as the silicon substrate. A hard mask formed by the method for producing a hard mask according to any one of claims 1 to 5 is prepared;
a hard mask is used on a main surface side of a crystalline silicon substrate, and an impurity element of a first conductivity type or an impurity element of a second conductivity type is selectively implanted into a silicon layer formed on the main surface by an ion implantation method. A method for producing a solar cell according to claim 6, comprising the steps of:
The method for manufacturing a solar cell, wherein the hard mask is made of silicon. A method for producing a solar cell according to claim 6 or 7, comprising the steps of:
Preparing at least two of the hard masks;
selectively injecting an impurity element of a first conductivity type into the silicon layer using one of the hard masks to form a first region of the first conductivity type in the silicon layer;
using the other hard mask, selectively injecting an impurity element of a second conductivity type into the silicon layer in which the first region is not formed, to form a second region of the second conductivity type in the silicon layer. A method for producing a solar cell according to claim 8, comprising the steps of:
the second region is provided in parallel with the first region, and a distance between the first region and the second region is set to 5 μm or more and 100 μm or less.