JP7643833B2 - Switching Elements - Google Patents

Description

The technology disclosed in this specification relates to switching elements.

Patent document 1 discloses a trench-gate type switching element. This switching element has a p-type bottom region that contacts the gate insulating film at the bottom of the trench. When the switching element is turned off, a depletion layer extends from the bottom region to its periphery, thereby mitigating the electric field near the bottom of the trench.

JP 2018-019045 A

In the switching element of Patent Document 1, the vertical dimension of the bottom region (the distance from the top to the bottom) is small. By increasing the vertical dimension of the bottom region, the electric field near the bottom surface of the trench can be further alleviated. On the other hand, a current flows in the region sandwiched between the bottom regions (hereinafter referred to as the specific region) when the switching element is on. In addition, when the switching element is on, a depletion layer of a certain width extends from the bottom regions on both sides of the specific region. Therefore, the width of the current path in the specific region is narrow, and the electrical resistance of the specific region is high. If the vertical dimension of the bottom region is increased, the vertical dimension of the specific region also increases, and the electrical resistance of the specific region becomes even higher. Therefore, the on-resistance of the switching element becomes higher. In this specification, a technology is proposed for reducing the on-resistance in a switching element having a bottom region with a large vertical dimension.

The switching element disclosed in this specification has a semiconductor substrate, a plurality of trenches provided on the upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of each of the trenches, and a gate electrode disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has an n-type source region in contact with the gate insulating film, a p-type body region in contact with the gate insulating film below the source region, a p-type bottom region in contact with the gate insulating film at the bottom surface of each of the trenches, and an n-type drift region in contact with the gate insulating film below the body region and separated from the source region by the body region. The vertical dimension of each of the bottom regions is larger than the vertical dimension of each of the trenches. The drift region has a first drift region and a second drift region. The first drift region is distributed from a position above the upper end of each of the bottom regions to a position below the lower end of each of the bottom regions and is in contact with each of the bottom regions. The second drift region contacts the first drift region from below and has a lower n-type impurity concentration than the first drift region.

In this switching element, the vertical dimension of each bottom region is larger than the vertical dimension of each trench. Therefore, the electric field near the bottom surface of each trench is effectively alleviated. Also, in this switching element, the specific region sandwiched between each bottom region is composed of a first drift region with a high n-type impurity concentration. Therefore, when the switching element is on, the width of the depletion layer extending from each bottom region to the specific region is narrow. Therefore, even if the vertical dimension of the specific region is large, the electrical resistance of the specific region is not very high. Therefore, with this structure, the on-resistance of the switching element is reduced.

FIG.

The switching element 10 of the embodiment shown in FIG. 1 is a metal oxide semiconductor field effect transistor (MOSFET). The switching element 10 has a semiconductor substrate 12. In this embodiment, the semiconductor substrate 12 is made of SiC (silicon carbide). A source electrode 80 is disposed on an upper surface 12a of the semiconductor substrate 12. A drain electrode 84 is disposed on a lower surface 12b of the semiconductor substrate 12.

A plurality of trenches 34 are formed in the upper surface 12a of the semiconductor substrate 12. The trenches 34 extend parallel to one another on the upper surface 12a. A gate insulating film 38 and a gate electrode 40 are formed in each trench 34. The gate insulating film 38 covers the inner surface of the trench 34. The gate electrode 40 is insulated from the semiconductor substrate 12 by the gate insulating film 38. The upper surface of the gate electrode 40 is covered by an interlayer insulating layer 36. The gate electrode 40 is insulated from the source electrode 80 by the interlayer insulating layer 36.

The semiconductor substrate 12 has a source region 22, a contact region 24, a body region 26, a drift region 28, a drain region 30 and a bottom region 32.

A plurality of source regions 22 are formed in the semiconductor substrate 12. Each source region 22 is an n-type region. Each source region 22 is exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 22 is in ohmic contact with the source electrode 80. Each source region 22 is in contact with the gate insulating film 38 at the upper end of the trench 34.

A plurality of contact regions 24 are formed in the semiconductor substrate 12. Each contact region 24 is a p-type region. Each contact region 24 is exposed on the upper surface 12a of the semiconductor substrate 12 at a position adjacent to the source region 22. Each contact region 24 is in ohmic contact with the source electrode 80.

The body region 26 is a p-type region. The body region 26 has a lower p-type impurity concentration than each of the contact regions 24. The body region 26 contacts the source region 22 and the contact region 24 from below. The body region 26 contacts the gate insulating film 38 below the source region 22.

A plurality of bottom regions 32 are formed in the semiconductor substrate 12. Each bottom region 32 is a p-type region. Each bottom region 32 is in contact with the gate insulating film 38 at the bottom surface of the corresponding trench 34. Symbol D32 in FIG. 1 indicates the vertical dimension of each bottom region 32. The vertical dimension D32 is the distance from the upper end to the lower end of each bottom region 32 (the distance measured along the thickness direction of the semiconductor substrate 12). Symbol D34 in FIG. 1 indicates the vertical dimension of each trench 34. The vertical dimension D34 is the distance from the upper end to the lower end of each trench (the distance measured along the thickness direction of the semiconductor substrate 12). The vertical dimension D32 of each bottom region 32 is larger than the vertical dimension D34 of each trench 34. Each bottom region 32 has a shape that is longer in the vertical direction than in the width direction.

The drift region 28 is an n-type region. The drift region 28 contacts the body region 26 from below. The drift region 28 is separated from the source region 22 by the body region 26. The drift region 28 contacts the gate insulating film 38 on the lower side of the body region 26. The drift region 28 is distributed from the position of the lower end of the body region 26 to a position lower than the lower end of each bottom region 32. The drift region 28 contacts each bottom region 32. In the cross section shown in FIG. 1, each bottom region 32 is separated from the body region 26 by the drift region 28. Note that each bottom region 32 may be connected to the body region 26 by a p-type region formed at a position not shown, or may be separated from the body region 26. The drift region 28 has a current diffusion region 28a, a first drift region 28b, and a second drift region 28c. The n-type impurity concentration of the current diffusion region 28a is higher than the n-type impurity concentration of the first drift region 28b. The n-type impurity concentration of the first drift region 28b is higher than the n-type impurity concentration of the second drift region 28c.

The current diffusion region 28a contacts the body region 26 from below. The current diffusion region 28a is distributed from the lower end of the body region 26 to a position above the upper end of each bottom region 32 (i.e., the bottom surface of the trench 34). The current diffusion region 28a is not in contact with each bottom region 32. The n-type impurity concentration in the current diffusion region 28a is almost constant. More specifically, the n-type impurity concentration in the current diffusion region 28a is distributed within a range of ±10% of the average value.

The first drift region 28b contacts the current diffusion region 28a from below. The first drift region 28b is distributed from a position above the upper end of each bottom region 32 to a position below the lower end of each bottom region 32. The first drift region 28b contacts the bottom region 32. The n-type impurity concentration in the first drift region 28b is almost constant. More specifically, the n-type impurity concentration in the first drift region 28b is distributed within a range of ±10% of the average value. The thickness T of the first drift region 28b in the portion located below each bottom region 32 may be 10 to 30% of the vertical dimension D32 of each bottom region 32.

The second drift region 28c contacts the first drift region 28b from below. The thickness of the second drift region 28c is thicker than the thickness of the first drift region 28b.

The drain region 30 is an n-type region. The n-type impurity concentration of the drain region 30 is higher than the n-type impurity concentration of the current diffusion region 28a. The drain region 30 contacts the second drift region 28c from below. The drain region 30 is exposed at the lower surface 12b of the semiconductor substrate 12. The drain region 30 is in ohmic contact with the drain electrode 84.

Next, the operation of the switching element 10 will be described. A higher potential than the source electrode 80 is applied to the drain electrode 84. When a potential equal to or higher than the gate threshold is applied to the gate electrode 40, a channel is formed in the body region 26 near the gate insulating film 38. Then, as shown by the arrow 100, electrons flow from the source electrode 80 through the source region 22, the channel in the body region 26, the drift region 28, and the drain region 30 toward the drain electrode 84. In other words, the switching element 10 is turned on.

As shown by the arrow 100, electrons flow from the source region 22 through the channel into the current diffusion region 28a. Since the n-type impurity concentration of the current diffusion region 28a is high, the electrical resistance of the current diffusion region 28a is low. Therefore, in the current diffusion region 28a, electrons diffuse widely in the lateral direction (parallel to the upper surface 12a of the semiconductor substrate 12). In addition, when the switching element 10 is in the on state, the depletion layer 90 spreads from the bottom region 32 to the first drift region 28b due to the built-in potential. Therefore, electrons flow from the current diffusion region 28a to the first drift region 28b at a position away from the trench 34 (a position bypassing the depletion layer 90). The electrons flow downward in the region sandwiched between the two bottom regions 32 of the first drift region 28b (hereinafter referred to as the specific region 29) to the second drift region 28c. Electrons that flow into the second drift region 28c flow through the drain region 30 to the drain electrode 84.

In this embodiment, the vertical dimension D32 of the bottom region 32 is large, so the vertical dimension of the specific region 29 is also large. In addition, the depletion layer 90 spreads from the bottom regions 32 on both sides into the specific region 29, so the depletion layer 90 narrows the current path (path through which electrons flow) in the specific region 29. In this way, the specific region 29 is long in the vertical direction, and the depletion layer 90 narrows the width of the current path in the specific region 29, so the electrical resistance of the specific region 29 tends to be high. However, in this embodiment, the n-type impurity concentration of the first drift region 28b is relatively high, so the width W of the depletion layer extending from each bottom region 32 to the specific region 29 is narrow. Therefore, a wide current path is secured in the specific region 29. Therefore, in the switching element 10, the electrical resistance of the current path in the specific region 29 is not very high. In addition, because the current diffusion region 28a provided above the first drift region 28b diffuses electrons widely in the lateral direction, the electrons can flow relatively uniformly within the specific region 29. This reduces the electrical resistance of the current path within the specific region 29. Therefore, the on-resistance of the switching element 10 is low.

When the potential of the gate electrode 40 is reduced below the gate threshold, the channel disappears and the flow of electrons stops. In other words, the switching element 10 is turned off.

When the switching element 10 is turned off, the potential of the drift region 28 rises relative to the potential of the body region 26, so that a depletion layer develops from the body region 26 to the drift region 28. At this time, the potential of the drift region 28 rises relative to the potential of the bottom region 32, so that a depletion layer develops from the bottom region 32 to the drift region 28. As a result, almost the entire drift region 28 is depleted. By depleting the drift region 28 in this manner, the potential difference between the drain electrode 84 and the source electrode 80 is maintained in the drift region 28. Note that although the n-type impurity concentration of the first drift region 28b is relatively high, the potential difference between the drain electrode 84 and the source electrode 80 is large, so that the depletion layer quickly spreads to the first drift region 28b. Also, since the n-type impurity concentration of the second drift region 28c is low, when the depletion layer reaches the second drift region 28c, the depletion layer quickly spreads to almost the entire second drift region 28c. In this way, when the switching element 10 is turned off, the depletion layer spreads quickly to the first drift region 28b and the second drift region 28c, so that the switching element 10 has a high breakdown voltage.

The depletion layer spreading from the bottom region 32 also spreads around the bottom surface of the trench 34. The depletion layer spreading from the bottom region 32 suppresses the occurrence of electric field concentration in the region near the bottom surface of the trench 34 (i.e., inside the semiconductor substrate 12 and the gate insulating film 38) at the time of turn-off. In particular, as described above, the bottom region 32 has a shape that is long in the vertical direction. The vertical dimension D32 of the bottom region 32 is larger than the vertical dimension D34 of the trench 34. In this way, since the bottom region 32 has a shape that is long in the vertical direction, the depletion layer extending from the bottom region 32 spreads over a wide range in the vertical direction in a short time. Since the depletion layer spreads over a wide range in the vertical direction in the lower part of the trench 34 in a short time, the electric field is more effectively alleviated in the region near the bottom surface of the trench 34.

As described above, the switching element 10 of the embodiment can reduce the electric field near the bottom of the trench 34 when turned off, and can achieve a low on-resistance when turned on.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples given above. The technical elements described in this specification or drawings demonstrate technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

10: switching element 12: semiconductor substrate 22: source region 24: contact region 26: body region 28: drift region 28a: current diffusion region 28b: first drift region 28c: second drift region 29: specific region 30: drain region 32: bottom region 34: trench 36: interlayer insulating layer 38: gate insulating film 40: gate electrode 80: source electrode 84: drain electrode 90: depletion layer

Claims (2)

A switching element,
A semiconductor substrate;
A plurality of trenches provided on an upper surface of the semiconductor substrate;
a gate insulating film covering the inner surface of each of the trenches;
a gate electrode disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film;
a drain electrode in contact with a lower surface of the semiconductor substrate;
having
The semiconductor substrate is
an n-type source region in contact with the gate insulating film;
a p-type body region below the source region and in contact with the gate insulating film;
a p-type bottom region in contact with the gate insulating film at the bottom surface of each of the trenches;
an n-type drift region that is in contact with the gate insulating film below the body region and is separated from the source region by the body region ;
a drain region disposed below the drift region, having a higher n-type impurity concentration than the drift region, and in ohmic contact with the drain electrode;
having
a vertical dimension of each of the bottom regions is greater than a vertical dimension of each of the trenches;
The drift region is
a first drift region that is distributed from a position above the upper end of each of the bottom regions to a position below the lower end of each of the bottom regions and is in contact with each of the bottom regions;
a second drift region in contact with the first drift region from below and having a lower n-type impurity concentration than the first drift region;
having
the drain region contacts the second drift region from below,
The thickness of the second drift region is greater than the thickness of the first drift region.
Switching element. the drift region having a current spreading region;
the current spreading region is in contact with the body region from a lower side, is distributed from a position of a lower end of the body region to a position above an upper end of each bottom region, and is not in contact with each bottom region;
an n-type impurity concentration of the current spreading region is higher than an n-type impurity concentration of the first drift region;
The first drift region is in contact with the current spreading region from below.
The switching element according to claim 1 .

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