JP7589569B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device and a manufacturing method thereof.

In recent years, wireless communication systems using RFID (Radio Frequency IDentification) technology have been attracting attention as devices using field effect transistors (hereafter referred to as FETs). RFID tags have an IC chip with a circuit made of FETs, and an antenna for wireless communication with a reader/writer. The antenna installed in the tag receives a carrier wave transmitted from the reader/writer, and the driver circuit in the IC chip operates.

RFID tags are expected to be used for a variety of purposes, including logistics management, product management, and shoplifting prevention, and are already being introduced in some areas, such as IC cards for transportation and product tags.

In order for RFID tags to be used in all kinds of products in the future, it will be necessary to reduce manufacturing costs, and the use of inexpensive processes that use coating and printing technologies in their production is being considered.

For example, in the case of transistors in the drive circuits of IC chips, FETs using carbon nanotubes (CNTs) and organic semiconductors, which can be applied using inkjet technology and screen printing technology, are being actively investigated.

The driving circuit in the IC chip is composed of at least a memory circuit that stores data, a rectifier circuit that generates a power supply voltage from the AC signal sent from the reader/writer, and a logic circuit that demodulates the AC signal and reads out the data stored in the memory circuit. Among them, the logic circuit is generally composed of a complementary semiconductor device consisting of a p-type FET and an n-type FET in order to reduce its power consumption.

However, it is known that FETs using CNTs (hereafter referred to as CNT-FETs) usually exhibit the characteristics of a p-type semiconductor element in the atmosphere. Therefore, it has been considered to convert the characteristics of a CNT-FET to an n-type semiconductor element by forming an n-type modified polymer on the semiconductor layer containing CNTs, or by forming a second insulating layer containing an electron donor compound having at least one selected from nitrogen atoms and phosphorus atoms (see, for example, Patent Documents 1 and 2).

International Publication No. 2009/139339 International Publication No. 2018/180146

However, the techniques described in Patent Documents 1 and 2 have an issue with the narrow noise margin of the output signal relative to the input signal when a complementary semiconductor device is assembled.

Therefore, the present invention aims to address the above-mentioned issues and provide a complementary semiconductor device with a wide noise margin.

In order to solve the above problems, the present invention has the following configuration.
That is, the present invention provides:
A semiconductor device including a first semiconductor element and a second semiconductor element provided on a substrate having an insulating surface,
the first semiconductor element is an n-type semiconductor element,
A source electrode;
A drain electrode;
A gate electrode;
a first semiconductor layer in contact with the source electrode and the drain electrode;
a gate insulating layer insulating the first semiconductor layer from the gate electrode;
Including,
The second semiconductor element includes:
A source electrode;
A drain electrode;
A gate electrode;
a second semiconductor layer in contact with the source electrode and the drain electrode;
a gate insulating layer insulating the second semiconductor layer from the gate electrode;
Including,
the first semiconductor layer and the second semiconductor layer both contain carbon nanotubes;
The semiconductor device is characterized in that the value (Cn/Ln) obtained by dividing the total length (Cn ⁾ of the carbon nanotubes present per 1 ^μm2 of the first semiconductor layer by the distance (Ln) between the source electrode and drain electrode of the first semiconductor element is different from the value (Cp/Lp) obtained by dividing the total length (Cp) of the carbon nanotubes present per 1 μm2 of the second semiconductor layer by the distance (Lp) between the source electrode and drain electrode of the second semiconductor element.

The semiconductor device of the present invention further comprises:
A semiconductor device including a first semiconductor element and a second semiconductor element provided on a substrate having an insulating surface,
the first semiconductor element is an n-type semiconductor element,
A source electrode;
A drain electrode;
A gate electrode;
a first semiconductor layer in contact with the source electrode and the drain electrode;
a gate insulating layer insulating the first semiconductor layer from the gate electrode;
Including,
the second semiconductor element is a p-type semiconductor element,
A source electrode;
A drain electrode;
A gate electrode;
a second semiconductor layer in contact with the source electrode and the drain electrode;
a gate insulating layer insulating the second semiconductor layer from the gate electrode;
Including,
the first semiconductor layer and the second semiconductor layer both contain carbon nanotubes;
The semiconductor device is characterized in that the total length (Cn) of the carbon nanotubes present per 1 ^μm2 of the first semiconductor layer is different from the total length (Cp) of the carbon nanotubes present per 1 ^μm2 of the second semiconductor layer.

The present invention provides a complementary semiconductor device with a wide noise margin.

FIG. 2 is a schematic cross-sectional view showing a first semiconductor element in the semiconductor device according to the first embodiment of the present invention; FIG. 2 is a schematic cross-sectional view showing a second semiconductor element in the semiconductor device according to the first embodiment of the present invention; FIG. 11 is a schematic cross-sectional view showing a first semiconductor element in a semiconductor device according to a third embodiment of the present invention; FIG. 2 is a schematic diagram illustrating the function of a semiconductor device according to an embodiment of the present invention; FIG. 1 is a diagram showing an example of transfer characteristics of a semiconductor device according to an embodiment of the present invention. 1A to 1C are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention;

One embodiment of the semiconductor device according to the present invention has a first semiconductor element which is an n-type semiconductor element and a second semiconductor element which is a p-type semiconductor element, and the semiconductor layers of both semiconductor elements contain carbon nanotubes, and the value (Cn/Ln) obtained by dividing the total length (Cn) of the carbon nanotubes present per 1 ^μm2 of the semiconductor layer of the first semiconductor element by the distance (Ln) between the source electrode and drain electrode of the first semiconductor element is different from the value (Cp/Lp) obtained by dividing the total length (Cp) of the carbon nanotubes present per 1 ^μm2 of the semiconductor layer of the second semiconductor element by the distance (Lp) between the source electrode and drain electrode of the second semiconductor element.

Furthermore, one embodiment of the semiconductor device according to the present invention has a first semiconductor element which is an n-type semiconductor element and a second semiconductor element which is a p-type semiconductor element, the semiconductor layers of both semiconductor elements contain carbon nanotubes, and the total length (Cn) of the carbon nanotubes present per 1 ^μm2 of the semiconductor layer of the first semiconductor element is different from the total length (Cp ⁾ of the carbon nanotubes present per 1 μm2 of the semiconductor layer of the second semiconductor element.

The configurations according to the above embodiments make it possible to provide a complementary semiconductor device with a wide noise margin.

The following describes in detail preferred embodiments of the semiconductor device and manufacturing method thereof according to the present invention. However, the present invention is not limited to the following embodiments, and can be modified in various ways depending on the purpose and application.

(Embodiment 1)
A semiconductor device according to a first embodiment of the present invention is a semiconductor device in which a first semiconductor element further includes a second insulating layer in contact with the first semiconductor layer on the opposite side of the first semiconductor layer to the gate insulating layer.

<First Semiconductor Element>
The first semiconductor element is provided on a substrate having an insulating surface, and comprises a source electrode, a drain electrode, a gate electrode, a first semiconductor layer in contact with the source electrode and the drain electrode, a gate insulating layer that insulates the first semiconductor layer from the gate electrode, and a second insulating layer in contact with the first semiconductor layer on the opposite side of the gate insulating layer with respect to the first semiconductor layer, and the first semiconductor layer contains carbon nanotubes.

Figure 1 shows a schematic cross-sectional view of an example of a first semiconductor element. This semiconductor element 1 has a gate electrode 11 formed on a substrate 10, a gate insulating layer 12 covering it, a source electrode 13 and a drain electrode 14 provided thereon, a first semiconductor layer 15 provided between these electrodes, and a second insulating layer 16 on the upper side of the first semiconductor layer 15 that covers the first semiconductor layer. The first semiconductor layer 15 contains carbon nanotubes (hereinafter referred to as "CNT").

The structure of the first semiconductor element 1 is a so-called bottom gate bottom contact structure in which the gate electrode 11 is disposed on the underside (substrate 10 side) of the first semiconductor layer 15, and the source electrode 13 and drain electrode 14 are disposed on the underside of the first semiconductor layer 15. However, the structure of the first semiconductor element is not limited to this, and may be, for example, a so-called top gate structure in which the gate electrode 11 is disposed on the upper side (opposite the substrate 10) of the first semiconductor layer 15, or a so-called top contact structure in which the source electrode 13 and drain electrode 14 are disposed on the upper surface of the first semiconductor layer 15.

(Substrate having an insulating surface)
The substrate having an insulating surface of the first semiconductor element may be made of any material as long as at least the surface on which the electrode system is disposed is insulating. For example, inorganic materials such as silicon wafer, glass, sapphire, and alumina sintered body, and organic materials such as polyimide, polyvinyl alcohol, polyvinyl chloride, polyethylene terephthalate, polyvinylidene fluoride, polysiloxane, polyvinylphenol (PVP), polyester, polycarbonate, polysulfone, polyethersulfone, polyethylene, polyphenylene sulfide, and polyparaxylene are preferably used. In addition, it may be a laminate of multiple materials, such as a PVP film formed on a silicon wafer or a polysiloxane film formed on polyethylene terephthalate.

(Source electrode, drain electrode, gate electrode)
The material used for the source electrode, drain electrode and gate electrode of the first semiconductor element may be any conductive material that can be generally used as an electrode. Examples of such conductive materials include conductive metal oxides such as tin oxide, indium oxide and indium tin oxide (ITO). In addition, examples of such conductive materials include metals such as platinum, gold, silver, copper, iron, tin, zinc, aluminum, indium, chromium, lithium, sodium, potassium, cesium, calcium, magnesium, palladium, molybdenum, amorphous silicon and polysilicon, alloys of a plurality of metals selected from these, and inorganic conductive materials such as copper iodide and copper sulfide. In addition, examples of such conductive materials include polythiophene, polypyrrole, polyaniline, a complex of polyethylenedioxythiophene and polystyrenesulfonic acid, and conductive polymers whose conductivity has been improved by doping with iodine or the like. In addition, examples of such conductive materials include carbon materials and materials containing an organic component and a conductor.

Materials containing organic components and conductors increase the flexibility of the electrodes, and provide good adhesion and electrical connection even when bent. The organic components are not particularly limited, but include monomers, oligomers or polymers, photopolymerization initiators, plasticizers, leveling agents, surfactants, silane coupling agents, defoamers, pigments, etc. From the viewpoint of improving the bending resistance of the electrodes, oligomers or polymers are preferred. However, the conductive materials of the electrodes and wiring are not limited to these. These conductive materials may be used alone, or multiple materials may be stacked or mixed for use.

The electrodes can be formed using known methods, such as those described in WO 2018/180146.

The distance 100 (Ln) between the source electrode and the drain electrode of the first semiconductor element is not particularly limited, but is preferably 1000 μm or less, more preferably 500 μm or less, and even more preferably 100 μm or less. By setting the distance in this range, the characteristics of the semiconductor element are further improved. The distance between the electrodes can be measured using an optical microscope or a scanning electron microscope (SEM), etc.

Wiring may also be formed to electrically connect the multiple first semiconductor elements. The material used for the wiring may be any conductive material that can generally be used as an electrode. For example, the same electrode materials as described above may be used.

There are no particular limitations on the method of forming the wiring and the method of forming the pattern as long as it is a method that can provide electrical continuity, but examples include the same methods as those for the electrode materials described above.

(Gate insulating layer)
The material used for the gate insulating layer is not particularly limited, but examples thereof include inorganic materials such as silicon oxide and alumina, organic polymer materials such as polyimide, polyvinyl alcohol, polyvinyl chloride, polyethylene terephthalate, polyvinylidene fluoride, polysiloxane, and polyvinylphenol (PVP), and mixtures of inorganic material powders and organic materials. Among organic materials, those containing organic compounds containing silicon-carbon bonds are preferred from the viewpoint of adhesion to the substrate and electrodes.

An example of an organic compound containing a silicon-carbon bond is polysiloxane. Polysiloxane is more preferable because it has high insulating properties and can be cured at low temperatures.

The thickness of the gate insulating layer of the first semiconductor element is preferably 0.05 to 5 μm, and more preferably 0.1 to 1 μm. By setting the thickness within this range, it becomes easier to form a uniform thin film. The thickness can be measured by an atomic force microscope, ellipsometry, etc.

The method for producing the gate insulating layer of the first semiconductor element is not particularly limited, but examples include a method in which a composition containing a material for forming the gate insulating layer is applied to a substrate, dried, and the resulting coating film is heat-treated as necessary. Examples of coating methods include known coating methods such as spin coating, blade coating, slit die coating, screen printing, bar coater, casting, print transfer, immersion and pulling, and inkjet. The temperature for heat-treating the coating film is preferably in the range of 100 to 300°C.

The gate insulating layer may be a single layer or multiple layers. Also, one layer may be formed from multiple insulating materials, or multiple insulating materials may be stacked to form multiple gate insulating layers.

(First Semiconductor Layer)
The first semiconductor layer contains CNT. As the CNT, any of single-walled CNTs in which one carbon film (graphene sheet) is wound in a cylindrical shape, double-walled CNTs in which two graphene sheets are wound concentrically, and multi-walled CNTs in which multiple graphene sheets are wound concentrically may be used, but it is preferable to use single-walled CNTs in order to obtain high semiconductor properties. CNTs can be obtained by an arc discharge method, a chemical vapor deposition method (CVD method), a laser ablation method, or the like.

More preferably, the CNT contains 80% by weight or more of semiconducting CNT. Even more preferably, the CNT contains 95% by weight or more of semiconducting CNT. Known methods can be used to obtain 80% by weight or more of semiconducting CNT. For example, there are a method of ultracentrifugation in the presence of a density gradient agent, a method of selectively attaching a specific compound to the surface of semiconducting or metallic CNT and separating them by utilizing the difference in solubility, and a method of separating them by electrophoresis or the like by utilizing the difference in electrical properties. Methods for measuring the content of semiconducting CNT include a method of calculating from the absorption area ratio of the visible-near infrared absorption spectrum, and a method of calculating from the intensity ratio of the Raman spectrum.

The length of a single CNT is preferably shorter than the distance between the source electrode and the drain electrode (hereinafter simply referred to as the "electrode distance"). The average length of the CNTs depends on the electrode distance, but is preferably 2 μm or less.

The average length of CNTs refers to the average length of 20 randomly picked CNTs. One method for measuring the average length of CNTs is to randomly pick 20 CNTs from an image obtained with an atomic force microscope and obtain the average length.

Generally, commercially available CNTs have a distribution in length and may contain CNTs longer than the distance between the electrodes, so it is preferable to add a process to make the length of the CNTs shorter than the distance between the electrodes. For example, it is effective to cut the CNTs into short fibers by acid treatment with nitric acid, sulfuric acid, etc., ultrasonic treatment, or freeze-pulverization. In addition, it is even more preferable to use separation by a filter in order to improve the purity of the CNTs.

The diameter of the CNTs is not particularly limited, but is preferably 1 nm or more and 100 nm or less, more preferably 50 nm or less, and even more preferably 5 nm or less.

As the CNT, it is preferable to use a CNT composite in which a conjugated polymer is attached to at least a portion of the surface of the CNT. A conjugated polymer refers to a compound whose repeating units have a conjugated structure and a degree of polymerization of 2 or more.

A state in which a conjugated polymer is attached to at least a portion of the CNT surface means that a part or all of the CNT surface is coated with the conjugated polymer. It is speculated that the reason that a conjugated polymer can coat a CNT is that an interaction occurs due to the overlap of the π electron clouds derived from the conjugated structures of both. Whether or not a CNT is coated with a conjugated polymer can be determined by whether the reflected color of the coated CNT approaches the color of the conjugated polymer from the color of the uncoated CNT. The presence of an attachment and the weight ratio of the attachment to the CNT can be quantitatively identified by elemental analysis such as X-ray photoelectron spectroscopy (XPS).

By attaching a conjugated polymer to at least a portion of the surface of the CNT, it becomes possible to uniformly disperse the CNT in a solution without impairing the high electrical properties that the CNT possesses. It also becomes possible to form a uniformly dispersed CNT film by coating the solution in which the CNTs are uniformly dispersed. This makes it possible to achieve high semiconducting properties.

Methods for attaching a conjugated polymer to CNT include (I) adding CNT to a molten conjugated polymer and mixing, (II) dissolving a conjugated polymer in a solvent and adding CNT to the solution and mixing, (III) pre-dispersing CNT in a solvent using ultrasound or the like, adding a conjugated polymer to the solution and mixing, and (IV) placing a conjugated polymer and CNT in a solvent and irradiating the mixture with ultrasound to mix. In the present invention, any of these methods may be used, or a combination of multiple methods may be used.

Examples of conjugated polymers include, but are not limited to, polythiophene-based polymers, polypyrrole-based polymers, polyaniline-based polymers, polyacetylene-based polymers, poly-p-phenylene-based polymers, and poly-p-phenylenevinylene-based polymers. The above polymers are preferably those in which a single monomer unit is arranged, but those in which different monomer units are block copolymerized or randomly copolymerized can also be used. Graft polymerized polymers can also be used.

Among the above polymers, in the present invention, polythiophene-based polymers are preferably used, since they are easily attached to CNTs and easily form CNT composites. More preferred are those that contain a condensed heteroaryl unit having a nitrogen-containing double bond in the ring and a thiophene unit in the repeating unit.

As the condensed heteroaryl unit having a nitrogen-containing double bond in the ring, a benzothiadiazole unit or a quinoxaline unit is particularly preferable. The presence of these units increases the adhesion between the CNT and the conjugated polymer, allowing the CNT to be more effectively dispersed in the semiconductor layer.

The semiconductor layer may further contain an organic semiconductor or insulating material as long as the electrical properties are not impaired. The thickness of the semiconductor layer is preferably 1 nm or more and 100 nm or less. Being within this range makes it easier to form a uniform thin film. It is more preferably 1 nm or more and 50 nm or less, and even more preferably 1 nm or more and 20 nm or less. The thickness can be measured using an atomic force microscope.

As a method for forming the semiconductor layer, it is possible to use dry methods such as resistance heating deposition, electron beam, sputtering, and CVD, but it is preferable to use a coating method from the viewpoint of manufacturing costs and suitability for large areas. Specifically, spin coating, blade coating, slit die coating, screen printing, bar coater, mold method, print transfer method, immersion and pulling method, inkjet method, etc. can be preferably used, and the coating method can be selected according to the coating film properties to be obtained, such as coating film thickness control and orientation control. In addition, the formed coating film may be annealed in air, under reduced pressure, or in an inert gas atmosphere such as nitrogen or argon.

(Second Insulating Layer)
The second insulating layer is formed on the side of the semiconductor layer opposite to the side on which the gate insulating layer is formed. The side opposite to the side on which the gate insulating layer is formed on the semiconductor layer refers to the upper side of the semiconductor layer, for example, when the gate insulating layer is formed on the lower side of the semiconductor layer. By forming the second insulating layer, a CNT-FET that normally exhibits p-type semiconductor characteristics can be converted into a semiconductor element that exhibits n-type semiconductor characteristics.

The second insulating layer preferably contains an organic compound containing a bond between a carbon atom and a nitrogen atom. Any organic compound may be used as such an organic compound, and examples of such an organic compound include amide-based compounds, imide-based compounds, urea-based compounds, amine-based compounds, imine-based compounds, aniline-based compounds, and nitrile-based compounds. In particular, the second insulating layer preferably contains (a) a compound having a structure in which at least one group represented by general formula (1) and at least one group represented by general formula (2) are bonded to one carbon-carbon double bond or one conjugated system, and (b) a polymer.

In compound (a), at least one group represented by general formula (1) and at least one group represented by general formula (2) are bonded to one carbon-carbon double bond or one conjugated system, so that the electron density of the π orbital of one carbon-carbon double bond or one conjugated system is high. Furthermore, since a structure such as one carbon-carbon double bond or one conjugated system is prone to π-π interactions or charge transfer interactions with CNTs, compound (a) strongly interacts electronically with CNTs, and it is presumed that a CNT-FET that normally exhibits p-type semiconductor characteristics can be converted into a semiconductor element that exhibits stable n-type semiconductor characteristics.

Furthermore, since the second insulating layer contains the (b) polymer, it is believed that the field where the (a) compound interacts with the CNTs can be kept stable, which is believed to result in more stable n-type semiconductor characteristics.

In general formulas (1) and (2), R ¹ represents a structure selected from a hydrogen atom, an alkyl group, and a cycloalkyl group. R ² to R ⁴ each independently represent a structure selected from a hydrogen atom, an alkyl group, a cycloalkyl group, an alkenyl group, a cycloalkenyl group, an alkynyl group, an aryl group, and a heteroaryl group. Any two of R ¹ to R ⁴ may form a ring structure. When two or more groups represented by general formula (1) or general formula (2) are included, R ¹ to R ⁴ may be the same or different from each other.

The alkyl group refers to a saturated aliphatic hydrocarbon group such as a methyl group, an ethyl group, an n-propyl group, an isopropyl group, an n-butyl group, a sec-butyl group, or a tert-butyl group, which may or may not have a substituent. The number of carbon atoms in the alkyl group is not particularly limited, but from the standpoint of ease of availability and cost, it is preferably 1 to 20, more preferably 1 to 8.

Cycloalkyl groups refer to saturated alicyclic hydrocarbon groups such as cyclopropyl, cyclohexyl, norbornyl, and adamantyl groups. The cycloalkyl groups may or may not have a substituent. The number of carbon atoms in the cycloalkyl groups is not particularly limited, but is preferably in the range of 3 to 20.

The alkenyl group refers to an unsaturated aliphatic hydrocarbon group containing a double bond, such as a vinyl group, an allyl group, or a butadienyl group, which may or may not have a substituent. The number of carbon atoms in the alkenyl group is not particularly limited, but is preferably in the range of 2 to 20.

A cycloalkenyl group refers to an unsaturated alicyclic hydrocarbon group containing a double bond, such as a cyclopentenyl group, a cyclopentadienyl group, or a cyclohexenyl group. The cycloalkenyl group may or may not have a substituent. The number of carbon atoms in the cycloalkenyl group is not particularly limited, but is preferably in the range of 3 to 20.

The term "alkynyl group" refers to an unsaturated aliphatic hydrocarbon group containing a triple bond, such as an ethynyl group. The alkynyl group may or may not have a substituent. The number of carbon atoms in the alkynyl group is not particularly limited, but is preferably in the range of 2 to 20.

The aryl group refers to an aromatic hydrocarbon group such as a phenyl group, a naphthyl group, a biphenyl group, an anthracenyl group, a phenanthryl group, a terphenyl group, or a pyrenyl group. The aryl group may or may not have a substituent. The number of carbon atoms in the aryl group is not particularly limited, but is preferably in the range of 6 to 40.

Heteroaryl groups refer to aromatic groups having one or more atoms other than carbon in the ring, such as furanyl groups, thiophenyl groups, benzofuranyl groups, dibenzofuranyl groups, pyridyl groups, and quinolinyl groups. Heteroaryl groups may or may not have a substituent. The number of carbon atoms in a heteroaryl group is not particularly limited, but is preferably in the range of 2 to 30.

The case where any two of R ¹ to R ⁴ form a ring structure is, for example, the case where R ¹ and R ² , or R ¹ and R ³ are bonded to each other to form a conjugated or non-conjugated ring structure. The ring structure may contain, in addition to carbon atoms, each of nitrogen, oxygen, sulfur, phosphorus, and silicon atoms. The ring structure may also be a structure in which the ring structure is condensed with another ring.

A conjugated system is a system in which two or more multiple bonds are conjugated, and the π electrons of the multiple bonds interact and are delocalized through single bonds. For example, it is a structure in which double bonds and/or triple bonds are connected by single bonds or atoms with unshared electron pairs or empty p orbitals, and specific examples are shown in general formulas (3) to (5).

Examples of compounds in which at least one group represented by general formula (1) and at least one group represented by general formula (2) are bonded to one conjugated system include compounds represented by general formulas (6) to (9). The structure corresponding to one conjugated system is covered with a dotted line.

(a) Examples of the compound include tetrakis(dimethylamino)ethylene, 4-((2-dimethylamino)vinyl)-N,N-dimethylaniline, 1,2-phenylenediamine, 1,4-phenylenediamine, 2,3,5,6-tetramethyl-1,4-phenylenediamine, N,N-dimethyl-1,4-phenylenediamine, N,N-dimethyl-N',N'-diphenyl-1,4-phenylenediamine, N,N,N'-trimethyl-N'-phenyl-1,4-phenylenediamine, N,N,N'-trimethyl-1,4-phenylenediamine, N,N,N',N'-tetramethyl ethyl-1,4-phenylenediamine, N,N-bis(methoxymethyl)-N',N'-dimethyl-1,4-phenylenediamine, 5,10-dihydro-5,10-dimethylphenazine, benzidine, 3,3',5,5'-tetramethylbenzidine, N,N,N',N'-tetramethylbenzidine, 4-(pyrrolidin-1-yl)aniline, 4-(4-methylpiperidin-1-yl)aniline, 2,4-dipiperidin-1-yl-phenylamine, tris[4-(diethylamino)phenyl]amine, N,N,N',N'-tetrakis[4-(diisobutylamino)phenyl]-1,4-phenylenediamine, 1,5-diaminonaphthalene, 1,8-diaminonaphthalene, etc. These compounds may be used alone or in combination.

Methods for analyzing the (a) compound and (b) polymer in the second insulating layer include a method for analyzing a sample obtained by extracting the composition of the second insulating layer from a semiconductor element using nuclear magnetic resonance (NMR) or a method for analyzing the second insulating layer using XPS or the like.

The thickness of the second insulating layer is preferably 500 nm or more, more preferably 1.0 μm or more, even more preferably 3.0 μm or more, and particularly preferably 10 μm or more. By making the thickness within this range, the stability of the characteristics of the semiconductor element is further improved. In addition, the upper limit is not particularly limited, but it is preferable that it is 500 μm or less.

The thickness of the second insulating layer is determined by measuring the cross section of the second insulating layer using a scanning electron microscope, calculating the thickness of 10 randomly selected points in the image of the second insulating layer located on the semiconductor layer, and taking the arithmetic average of the thicknesses.

The second insulating layer may contain other compounds in addition to the (a) compound and (b) polymer. Examples of other compounds include thickeners and thixotropic agents for adjusting the viscosity and rheology of the solution when the second insulating layer is formed by coating.

The second insulating layer may be a single layer or multiple layers. In the case of multiple layers, as long as at least one layer containing the compound (a) is in contact with the semiconductor layer, at least one layer may contain the compound (a) and the polymer (b), or the compound (a) and the polymer (b) may be contained in separate layers. For example, a configuration may be exemplified in which a first layer containing the compound (a) is formed on the semiconductor layer, and a second layer containing the polymer (b) is formed thereon.

The method for forming the second insulating layer is not particularly limited, and dry methods such as resistance heating deposition, electron beam, sputtering, and CVD can be used, but a coating method is preferable from the viewpoint of manufacturing costs and suitability for large areas. Specific examples of coating methods that can be used preferably include spin coating, blade coating, slit die coating, screen printing, bar coater, casting, print transfer, immersion and pulling, inkjet, and drop casting. The coating method can be selected depending on the coating film properties to be obtained, such as coating film thickness control and orientation control.

(Protective Layer)
The first semiconductor element may further have a protective layer on the second insulating layer, the protective layer having a role of protecting the semiconductor element from physical damage such as rubbing and from moisture and oxygen in the air.

Examples of materials for the protective layer include inorganic materials such as silicon wafers, glass, sapphire, and sintered alumina, and organic materials such as polyimide, polyvinyl alcohol, polyvinyl chloride, polyethylene terephthalate, polyvinylidene fluoride, polysiloxane, polyvinylphenol, polyester, polycarbonate, polysulfone, polyethersulfone, polyethylene, polyphenylene sulfide, polyparaxylene, polyacrylonitrile, and cycloolefin polymer. In addition, the protective layer may be made of a plurality of laminated materials, such as a polyvinylphenol film formed on a silicon wafer or an aluminum oxide film formed on polyethylene terephthalate.

In a semiconductor element, the current flowing between the source electrode and the drain electrode (source-drain current) can be controlled by changing the gate voltage. The mobility μ (cm ² /V·s) of the semiconductor element can be calculated using the following formula.

μ=(δId/δVg)L・D/(W・εr・ε・Vsd)
where Id is the source-drain current (A), Vsd is the source-drain voltage (V), Vg is the gate voltage (V), D is the thickness of the gate insulating layer (m), and L is the channel length (m). W is the channel width (m), εr is the relative dielectric constant of the gate insulating layer (F/m), ε is the dielectric constant of a vacuum (8.85×10 ⁻¹² F/m), and δ is the change in the corresponding physical quantity. Shows.

The threshold voltage of a semiconductor element can be determined from the intersection of the extension of the linear portion of the Id-Vg graph with the Vg axis.

A semiconductor element with a small absolute value of the threshold voltage and high mobility is highly functional and has good characteristics.

<Second Semiconductor Element>
The second semiconductor element is provided on a substrate having an insulating surface, and includes a source electrode, a drain electrode, a gate electrode, a second semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer that insulates the second semiconductor layer from the gate electrode, and the second semiconductor layer contains CNTs.

Figure 2 shows a schematic cross-sectional view of an example of a second semiconductor element. This semiconductor element 2 has a gate electrode 21 formed on a substrate 20, a gate insulating layer 22 covering it, a source electrode 23 and a drain electrode 24 provided thereon, and a second semiconductor layer 25 provided between these electrodes. The second semiconductor layer 25 contains CNTs.

The structure of the second semiconductor element 2 is a bottom-gate/bottom-contact structure, similar to the semiconductor element 1 shown in FIG. 1. However, the structure of the second semiconductor element 2 is not limited to this, and may be a top-gate structure or a top-contact structure.

(Substrate having an insulating surface)
The substrate having an insulating surface of the second semiconductor element may be, for example, the same as the substrate having an insulating surface of the first semiconductor element described above.

From the viewpoint of manufacturing costs and process simplicity, it is preferable to form the first and second semiconductor elements on a substrate having the same insulating surface, rather than on separate substrates.

(Source electrode, drain electrode, gate electrode)
Examples of materials used for the source electrode, drain electrode, and gate electrode of the second semiconductor element include the same materials as those used for the electrodes of the first semiconductor element described above.

From the viewpoint of manufacturing costs, it is preferable to form the electrodes of the second semiconductor element from the same material as the electrodes of the first semiconductor element described above, rather than from different materials. When the electrodes are formed from the same material, it means that the elements contained in each electrode that have the highest molar ratio are the same. The type and content ratio of the elements in the electrodes can be identified by elemental analysis such as X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS).

Furthermore, from the viewpoint of process simplicity, it is preferable that the electrodes of the second semiconductor element are formed in the same process as the electrodes of the above-mentioned semiconductor elements.

The distance 200 (Ln) between the source electrode and the drain electrode of the second semiconductor element is not particularly limited, but is preferably 1000 μm or less, more preferably 500 μm or less, and even more preferably 100 μm or less. By setting the distance in this range, the characteristics of the semiconductor element are further improved. The distance between the electrodes can be measured using an optical microscope or a scanning electron microscope (SEM), etc.

Wiring may also be formed to electrically connect between multiple second semiconductor elements or between the first semiconductor element and the second semiconductor element. The material used for the wiring may be any conductive material that can generally be used as an electrode. For example, the same material as the wiring electrically connecting between the first semiconductor elements described above may be used.

(Gate insulating layer)
The material used for the gate insulating layer of the second semiconductor element is not particularly limited, but examples thereof include the same materials as those used for the gate insulating layer of the first semiconductor element described above.

From the viewpoint of manufacturing costs, it is preferable that the gate insulating layer of the second semiconductor element is formed of the same material as the gate insulating layer of the first semiconductor element described above, rather than being formed of different materials. These gate insulating layers are made of the same material means that the types and composition ratios of elements contained in the composition constituting each gate insulating layer at 1 mol % or more are the same. Whether the types and composition ratios of elements are the same or not can be identified by elemental analysis such as X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS).

Furthermore, from the viewpoint of process simplicity, it is preferable that the gate insulating layer of the second semiconductor element is formed in the same process as the gate insulating layer of the first semiconductor element described above.

(Second Semiconductor Layer)
The second semiconductor layer contains CNTs, which are the same as those in the first semiconductor layer.

From the viewpoint of manufacturing costs, it is preferable to form the second semiconductor layer from the same material as the first semiconductor layer, rather than from a different material. Furthermore, from the viewpoint of process simplicity, it is preferable to form the second semiconductor layer in the same process as the first semiconductor layer.

In the semiconductor device according to the first embodiment, the total length (Cn) of CNTs present per 1 μm ² of the first semiconductor layer is different from the total length (Cp) of CNTs present per 1 μm ² of the second semiconductor layer. This makes the electrical characteristics, such as the on-current, off-current, and threshold voltage, of the first and second semiconductor elements equivalent, resulting in a semiconductor device with a wide noise margin.

Among them, it is preferable that the total length (Cp) of the CNTs present per 1 μm ² of the second semiconductor layer is shorter than the total length (Cn) of the CNTs present per 1 μm ² of the first semiconductor layer. This is preferable because the electrical characteristics of the first semiconductor element and the second semiconductor element are more equal. This is presumed to be for the following reason. As can be seen from the fact that CNT-TFTs usually exhibit p-type semiconductor characteristics, in CNTs, the mobility of holes, which are carriers responsible for the electrical conductivity of p-type semiconductors, is greater than the mobility of electrons, which are carriers responsible for the electrical conductivity of n-type semiconductors. For this reason, in order to make the electrical characteristics of the p-type semiconductor element and the n-type semiconductor element equivalent, it is preferable to make the carrier density of the n-type semiconductor element denser than the carrier density of the p-type semiconductor element. Furthermore, in order to make the electrical characteristics of the p-type semiconductor element and the n-type semiconductor element equivalent, it is also preferable to make the distance between the source electrode and the drain electrode of the n-type semiconductor element shorter than the distance between the source electrode and the drain electrode of the p-type semiconductor element.

More preferably, the total length (Cp) of the CNTs present per 1 μm ² of the second semiconductor layer is 0.2 to 0.8 times the total length (Cn) of the CNTs present per 1 μm ² of the first semiconductor layer. The above numerical range is a range obtained by rounding off the last significant digit of the limit value. That is, 0.8 times or less means 0.84 times or less, and 0.2 times or more means 0.15 times or more. By being in this range, the mobility of the first semiconductor element and the second semiconductor element is increased, the electrical characteristics are more equivalent, and the semiconductor device has a wider noise margin.

The total length of CNTs present per 1 μm ² of the semiconductor layer refers to the sum of the lengths of CNTs present within 1 μm ² randomly extracted from the semiconductor layer. A method for measuring the total length of CNTs includes a method of randomly selecting 1 μm ² from an image of the semiconductor layer of a semiconductor element obtained by an atomic force microscope, measuring the lengths of all CNTs contained in that area, and adding them up. The total length of the CNTs is a value obtained by rounding off numbers less than 1 μm. In other words, the total length of CNTs of 1 μm is 0.5 μm or more and 1.4 μm or less.

The distance between the source electrode and drain electrode of a semiconductor element refers to the shortest distance between the source electrode and drain electrode. One method for measuring the distance between the source electrode and drain electrode is to measure the shortest distance between the source electrode and drain electrode from an image of the semiconductor element obtained with an optical microscope or a scanning electron microscope (SEM), etc.

(Third insulating layer)
The second semiconductor element may further include a third insulating layer formed on the side opposite to the side on which the gate insulating layer is formed with respect to the second semiconductor layer. The side opposite to the side on which the gate insulating layer is formed with respect to the second semiconductor layer refers to the upper side of the semiconductor layer, for example, when the gate insulating layer is formed on the lower side of the second semiconductor layer. By further forming the third insulating layer of the present invention, the second semiconductor layer can be protected from external environments such as oxygen and moisture, and physical impacts. In addition, by forming the third insulating layer, the characteristics of the second semiconductor element can also be adjusted.

The formation of the third insulating layer does not convert a CNT-FET, which normally exhibits p-type semiconductor characteristics, into a semiconductor element exhibiting n-type semiconductor characteristics. In this respect, the third insulating layer differs from the second insulating layer provided in the first semiconductor element.

The third insulating layer and the second insulating layer are different in that the types and composition ratios of elements contained at 1 mol % or more in the composition constituting the third insulating layer and the second insulating layer are different. The types and content ratios of elements in the third insulating layer and the second insulating layer can be identified by elemental analysis such as X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS) of samples obtained by extracting the composition of the third insulating layer and the second insulating layer from the semiconductor element.

The material used for the third insulating layer is not particularly limited, but specifically includes inorganic materials such as silicon oxide and alumina; organic polymer materials such as polyimide and its derivatives, polyvinyl alcohol, polyvinyl chloride, polyethylene terephthalate, polyvinylidene fluoride, polysiloxane and its derivatives, polyvinylphenol and its derivatives; or a mixture of inorganic material powder and organic polymer material, or a mixture of organic low molecular weight material and organic polymer material. Among these, it is preferable to use an organic polymer material that can be prepared by a coating method. In particular, it is preferable to use an organic polymer material selected from the group consisting of polyfluoroethylene, polynorbornene, polysiloxane, polyimide, polystyrene, polycarbonate and their derivatives, polyacrylic acid derivatives, polymethacrylic acid derivatives, and copolymers containing these, from the viewpoint of uniformity of the insulating layer. By using an organic polymer material selected from the group consisting of polysiloxane, polystyrene, polyvinylphenol, and polymethyl methacrylate, it is possible to protect the second semiconductor layer without deteriorating the electrical characteristics of the second semiconductor element, so it is particularly preferable.

The thickness of the third insulating layer is preferably 50 nm to 10 μm, and more preferably 100 nm to 3 μm. The third insulating layer may be a single layer or multiple layers. In addition, one layer may be formed from multiple insulating materials, or multiple insulating materials may be laminated.

The method for forming the third insulating layer is not particularly limited, and dry methods such as resistance heating deposition, electron beam, sputtering, and CVD can be used, but a coating method is preferable from the viewpoint of manufacturing costs and suitability for large areas. Specific examples of coating methods that can be preferably used include spin coating, blade coating, slit die coating, screen printing, bar coater, casting, print transfer, immersion and pulling, inkjet, and drop casting. The coating method can be selected depending on the coating film properties to be obtained, such as coating film thickness control and orientation control.

(Embodiment 2)
The semiconductor device according to the second embodiment of the present invention has a feature that, instead of the feature that the total length (Cn) of the carbon nanotubes present per 1 μm ² of the first semiconductor layer is different from the total length (Cp) of the carbon nanotubes present per 1 μm ² of the second semiconductor layer in the semiconductor device according to the first embodiment, the value (Cn/Ln) obtained by dividing the total length (Cn) of the carbon nanotubes present per 1 μm ² of the first semiconductor layer by the distance (Ln) between the source electrode and the drain electrode of the first semiconductor element is different from the value (Cp/Lp) obtained by dividing the total length (Cp) of the carbon nanotubes present per 1 μm ² of the second semiconductor layer by the distance (Lp) between the source electrode and the drain electrode of the second semiconductor element. Except for this point, the configuration is the same as that of the semiconductor device according to the first embodiment.

The semiconductor device according to the second embodiment has the above characteristics, and as a result, the electrical characteristics of the first semiconductor element and the second semiconductor element, such as the on-current, off-current, and threshold voltage, are equivalent, resulting in a semiconductor device with a wide noise margin.

Among them, it is preferable that the value (Cp/Lp) obtained by dividing the total length (Cp) of the CNTs present per 1 μm ² of the second semiconductor layer by the distance (Lp) between the source electrode and the drain electrode of the second semiconductor element is smaller than the value (Cn/Ln) obtained by dividing the total length (Cn) of the CNTs present per 1 μm ² of the first semiconductor layer by the distance (Ln) between the source electrode and the drain electrode of the first semiconductor element. This is preferable because the electrical characteristics of the first semiconductor element and the second semiconductor element become more equal. This is presumed to be for the following reason. As can be seen from the fact that CNT-TFTs usually exhibit p-type semiconductor characteristics, in CNTs, the mobility of holes, which are carriers responsible for the electrical conductivity of p-type semiconductors, is greater than the mobility of electrons, which are carriers responsible for the electrical conductivity of n-type semiconductors. For this reason, in order to make the electrical characteristics of the p-type semiconductor element and the n-type semiconductor element equivalent, it is preferable to make the carrier density of the n-type semiconductor element denser than the carrier density of the p-type semiconductor element. Furthermore, in order to make the electrical characteristics of the p-type semiconductor element and the n-type semiconductor element equivalent, it is also preferable to make the distance between the source electrode and drain electrode of the n-type semiconductor element shorter than the distance between the source electrode and drain electrode of the p-type semiconductor element.

More preferably, the value (Cp/Lp) obtained by dividing the total length (Cp) of the CNTs present per 1 μm ² of the second semiconductor layer by the distance (Lp) between the source electrode and the drain electrode of the second semiconductor element is 0.2 to 0.8 times the value (Cn/Ln) obtained by dividing the total length (Cn) of the CNTs present per 1 μm ² of the first semiconductor layer by the distance (Ln) between the source electrode and the drain electrode of the first semiconductor element. The above numerical range is a range obtained by rounding off the last significant digit of the limit value. That is, 0.8 times or less means 0.84 times or less, and 0.2 times or more means 0.15 times or more. By being in this range, the mobility of the first semiconductor element and the second semiconductor element is increased, the electrical characteristics are more equivalent, and the semiconductor device has a wider noise margin.

The semiconductor device according to the second embodiment may further have a feature that the total length (Cn) of the carbon nanotubes present per 1 μm ² of the first semiconductor layer is different from the total length (Cp) of the carbon nanotubes present per 1 μm ² of the second semiconductor layer. Also, the total length (Cp) of the carbon nanotubes present per 1 μm ² of the second semiconductor layer may be shorter than the total length (Cn) of the carbon nanotubes present per 1 μm ² of the first semiconductor layer. Furthermore, the total length (Cp) of the carbon nanotubes present per 1 μm ² of the second semiconductor layer may be 0.2 to 0.8 times the total length (Cn) of the carbon nanotubes present per 1 μm ² of the first semiconductor layer.

(Embodiment 3)
A semiconductor device according to a third embodiment of the present invention is a semiconductor device in which the first semiconductor layer in the first semiconductor element further contains an n-type modifier.

Figure 3 shows a schematic cross-sectional view of an example of a first semiconductor element in a semiconductor device according to embodiment 3 of the present invention. This semiconductor element 3 has a gate electrode 31 formed on a substrate 30, a gate insulating layer 32 covering it, a source electrode 33 and a drain electrode 34 provided thereon, and a first semiconductor layer 35 provided between these electrodes. The first semiconductor layer 35 contains CNTs and an n-type modifier.

<n-type modifier>
The n-type modifier is a material for converting a CNT-FET, which normally exhibits p-type semiconductor characteristics, into a semiconductor element exhibiting n-type semiconductor characteristics. When the first semiconductor layer contains CNTs and an n-type modifier, the first semiconductor element becomes an n-type semiconductor element.

Methods for incorporating an n-type modifier into the first semiconductor layer include doping, adsorbing, or coating the n-type modifier onto the CNTs in the first semiconductor layer.

The n-type modifier is not particularly limited as long as it can convert the CNT-FET into a semiconductor element that exhibits n-type semiconductor properties, but examples include substances containing electron donor atoms that provide electrons to CNTs, such as alkali metals such as potassium and phosphorus, and substances that have functional groups that act as electron-donating groups, such as amines, alkyl halides, and alcohols.

The semiconductor device according to the second embodiment has the same configuration and manufacturing method as the first embodiment, except that the first semiconductor element does not include the second insulating layer as an essential component, and instead the first semiconductor layer includes the n-type modifier.

In the semiconductor device according to the third embodiment, the total length (Cn) of the CNTs present per 1 μm ² of the first semiconductor layer is different from the total length (Cp) of the CNTs present per 1 μm ² of the second semiconductor layer. Alternatively, the value (Cn/Ln) obtained by dividing the total length (Cn) of the carbon nanotubes present per 1 μm ² of the first semiconductor layer by the distance (Ln) between the source electrode and the drain electrode of the first semiconductor element is different from the value (Cp/Lp) obtained by dividing the total length (Cp) of the carbon nanotubes present per 1 μm ² of the second semiconductor layer by the distance (Lp) between the source electrode and the drain electrode of the second semiconductor element. As a result, the electrical characteristics such as the on-current, off-current, and threshold voltage of the first semiconductor element and the second semiconductor element become equivalent, resulting in a semiconductor device with a wide noise margin.

<Semiconductor Device>
The semiconductor device of the present invention includes both a first semiconductor element and a second semiconductor element. An example of a semiconductor device according to an embodiment of the present invention is shown in Fig. 4A. Here, the first semiconductor element 41 is an n-type semiconductor element, and the second semiconductor element 42 is a p-type semiconductor element. The operation of the semiconductor device shown in Fig. 3A will be described below.

First, the input signal (V _in ) changes between low "L" (ground potential GND) and high "H" (V _DD ). When the input signal is "L", the p-type semiconductor element conducts and the n-type semiconductor element cuts off, causing the output signal (V _out ) to become "H". Conversely, when the input signal is "H", the n-type semiconductor element 41 conducts and the p-type semiconductor element 42 cuts off, causing the output signal to become "L". An example of the transfer characteristics of this semiconductor device is shown in FIG. 4B.

For example, if the threshold voltage of the n-type semiconductor element is different from the threshold voltage of the p-type semiconductor element, the timing of conduction and cutoff of the n-type semiconductor element and the p-type semiconductor element will be shifted, and the output signal will not be inverted with respect to the input signal, and may not operate normally. Therefore, if the electrical characteristics of the n-type semiconductor element and the p-type semiconductor element are equivalent, a semiconductor device with good characteristics will be obtained. For example, if the electrical characteristics of the n-type semiconductor element and the p-type semiconductor element are equivalent, the input signal that changes the output signal (V in FIG. 3B: input signal that makes the output signal V _DD /2) will be V _DD /2, and a semiconductor device with a wide noise margin and high performance will be obtained. In addition, in the curve (transfer characteristic curve) showing the output signal with respect to the input signal shown in FIG. 4B, the slope (gain) of the tangent at Vin=V correlates with the mobility of each semiconductor element, and a semiconductor device with a large gain has high performance. In addition to the above-mentioned threshold voltage, the electrical characteristics include, for example, on current, off current, and mobility.

(Applicability of Semiconductor Devices)
The semiconductor device according to the embodiment of the present invention can be applied to ICs in various electronic devices, wireless communication devices such as RFID tags, wireless power supply devices, TFT arrays for displays such as active matrix driven liquid crystal displays and electronic paper, sensors, and opening detection systems.

<Method of Manufacturing Semiconductor Device>
The method for manufacturing a semiconductor device according to an embodiment of the present invention preferably includes at least a step of applying and drying a semiconductor layer to an area between a source electrode and a drain electrode of a first semiconductor element and a second semiconductor element. In this manufacturing method, the electrodes, gate insulating layer, semiconductor layer, second insulating layer, and third insulating layer constituting the first semiconductor element and the second semiconductor element to be manufactured are formed as described above. By appropriately selecting the order of these forming methods, the semiconductor device according to the present invention can be manufactured.

From the viewpoint of manufacturing cost and process simplicity, it is preferable to form the first semiconductor element and the second semiconductor element simultaneously, rather than separately. Therefore, it is preferable that they have the same structure. In particular, it is preferable to form the first semiconductor layer and the second semiconductor layer by coating and drying in the same process.

Here, "simultaneously forming" refers to forming two electrodes or layers together by carrying out the processes required for forming the electrodes or layers once. Also, "forming by coating and drying in the same process" refers to forming the layers by carrying out the coating and drying processes for forming the target layers once.

All of these processes can be applied even when the first and second semiconductor elements have different structures, but are easier to apply when they have the same structure.

Below, an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention will be specifically described. First, as shown in FIG. 5(a), a gate electrode 510 is formed in a first semiconductor element region 500 on a substrate 50, and a gate electrode 511 is formed in a second semiconductor element region 501 by the method described above.

Next, as shown in FIG. 5(b), gate insulating layers 520, 521 are formed for the first semiconductor element 500 and the second semiconductor element 501.

Next, as shown in FIG. 5(c), source electrodes 540, 541 and drain electrodes 550, 551 are simultaneously formed on the top of the gate insulating layers 520, 521 of the first semiconductor element 500 and the second semiconductor element 501 using the same material by the method described above.

Next, as shown in FIG. 5(d), the first semiconductor layers 560, 460 and the second semiconductor layer 561 are formed between the source electrodes 540, 541 and the drain electrodes 550, 551 of the first semiconductor element 500 and the second semiconductor element 501, respectively, by the method described above.

Next, as shown in FIG. 5(e), a second insulating layer 5848 is formed by the method described above so as to cover the first semiconductor layer 560 of the first semiconductor element 500, thereby completing the manufacturing of a semiconductor device.

In addition, in order to improve the efficiency of material use and reduce the number of material types, it is preferable that the gate electrodes 510, 511 of the first semiconductor element 400 and the second semiconductor element 501 are made of the same material. For the same reason, it is preferable that the composition used to form the first semiconductor layer 560 and the composition used to form the second semiconductor layer 561 are the same composition. The composition being the same means that the types and composition ratios of elements contained in each composition at 1 mol % or more are the same. Whether the types and composition ratios of elements are the same or not can be identified by elemental analysis such as X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS).

It is also preferable that the concentration of the composition used to form the first semiconductor layer 560 is different from the concentration of the composition used to form the second semiconductor layer 561. Alternatively, it is preferable that the coating amount of the composition used to form the first semiconductor layer 560 is different from the coating amount of the composition used to form the second semiconductor layer 561. By using any of these methods, a semiconductor device in which the electrical characteristics of the first semiconductor element and the second semiconductor element are equivalent can be easily manufactured, which is preferable.

The coating method in the coating process of the first semiconductor layer 560 and the second semiconductor layer 561 is not particularly limited, but is preferably any one selected from the group consisting of an inkjet method, a dispenser method, and a spray method. Among them, from the viewpoint of raw material usage efficiency, the inkjet method is more preferable as a coating method. In that case, it is possible to adjust the coating amount by adjusting, for example, the number of shots or the solution extrusion pressure.

The present invention will be described in more detail below with reference to examples. Note that the present invention is not limited to the following examples.

Preparation Example 1 of Semiconductor Solution: Semiconductor Solution A1, Semiconductor Solution A2
First, 1.0 mg of CNT1 (manufactured by CNI, single-walled CNT, purity 95%) was added to a 10 ml solution of 2.0 mg of poly(3-hexylthiophene) (P3HT) (manufactured by Aldrich Co., Ltd.), and the mixture was ultrasonically stirred for 4 hours at 20% output using an ultrasonic homogenizer (Tokyo Rikakikai Co., Ltd. VCX-500) while cooling on ice, to obtain CNT dispersion A (CNT composite concentration relative to solvent: 0.96 g/l). Next, a semiconductor solution for forming a semiconductor layer was prepared. The CNT dispersion A was filtered using a membrane filter (pore size 10 μm, diameter 25 mm, Millipore Omnipore membrane) to remove CNT composites with a length of 10 μm or more. 5 ml of o-DCB (Wako Pure Chemical Industries, Ltd.) was added to the obtained filtrate, and then the low boiling point solvent chloroform was distilled off using a rotary evaporator, and the solvent was replaced with o-DCB to obtain CNT dispersion A'.
3 mL of o-DCB was added to 1 mL of CNT dispersion A' to prepare semiconductor solution A1 (CNT composite concentration relative to solvent: 0.033 g/L). Also, 1.5 mL of o-DCB was added to 1 mL of CNT dispersion A' to prepare semiconductor solution A2 (CNT composite concentration relative to solvent: 0.061 g/L).

Composition Preparation Example 1: Gate Insulating Layer Solution A
61.29g (0.45 mol) of methyltrimethoxysilane, 12.31g (0.05 mol) of 2-(3,4-epoxycyclohexyl)ethyltrimethoxysilane, and 99.15g (0.5 mol) of phenyltrimethoxysilane were dissolved in 203.36g of propylene glycol monobutyl ether (boiling point 170°C), and 54.90g of water and 0.864g of phosphoric acid were added thereto while stirring. The resulting solution was heated at a bath temperature of 105°C for 2 hours, and the internal temperature was raised to 90°C to distill off a component mainly consisting of by-produced methanol. The solution was then heated at a bath temperature of 130°C for 2.0 hours, and the internal temperature was raised to 118°C to distill off a component mainly consisting of water and propylene glycol monobutyl ether, and then cooled to room temperature to obtain a polysiloxane solution A having a solid content concentration of 26.0% by weight. The weight average molecular weight of the resulting polysiloxane was 6000. 10 g of the obtained polysiloxane solution A was weighed out, and 54.4 g of propylene glycol monoethyl ether acetate (hereinafter referred to as PGMEA) was mixed therewith, followed by stirring at room temperature for 2 hours to obtain a gate insulating layer solution A.

Composition Preparation Example 2: Solution A for preparing second insulating layer
2.5 g of polymethyl methacrylate (manufactured by Fuji Film Wako Pure Chemical Industries, Ltd.) was dissolved in 7.5 g of N,N-dimethylformamide to prepare polymer solution A. Next, 1 g of N,N,N',N'-tetramethyl-1,4-phenylenediamine (manufactured by Tokyo Chemical Industry Co., Ltd.) was dissolved in 9.0 g of N,N-dimethylformamide to prepare compound solution A. 0.30 g of compound solution A was added to 0.68 g of polymer solution A to obtain solution A for producing a second insulating layer.

Composition Preparation Example 3: Solution B for preparing second insulating layer
Solution B for preparing a second insulating layer was obtained in the same manner as in Composition Preparation Example 2, except that N,N,N',N'-tetramethylbenzidine (manufactured by Tokyo Chemical Industry Co., Ltd.) was used instead of N,N,N',N'-tetramethyl-1,4-phenylenediamine.

Composition Preparation Example 4: Third Insulating Layer Solution A
A third insulating layer solution A was prepared by dissolving 1.485 g of polymethyl methacrylate in 8.5 g of cyclohexanone.

Composition Preparation Example 5: Third Insulating Layer Solution B
A third insulating layer solution B was obtained in the same manner as in Composition Preparation Example 4, except that an acrylic resin having a hydroxyl group (manufactured by Kyoeisha Chemical Co., Ltd., product number "Orikox KC-7000") was used instead of polymethyl methacrylate.

Composition Preparation Example 6: Third Insulating Layer Solution C
A third insulating layer solution C was obtained in the same manner as in Composition Preparation Example 4, except that ethyl cellulose (manufactured by The Dow Chemical Company, product number "Ethocel STD-100CPS") was used instead of polymethyl methacrylate.

(Evaluation of Semiconductor Device)
The semiconductor device shown in FIG. 3A, which is composed of the first semiconductor element and the second semiconductor element produced in each example and comparative example, was evaluated. V _DD was 10V, and the GND terminal was grounded. The slope (gain) of the tangent of the transfer characteristic of the output signal (V _out ) with respect to the change in the input signal (V _in ) from 0 to 10V was measured. In addition, the V _{in at} which V _out changes (V _in at which V _out becomes V _DD /2) was measured. The larger the gain, the higher the performance of the semiconductor device. In addition, the closer V in is to 5V (=V _DD /2), the better the semiconductor characteristics of the n-type semiconductor element and the p-type semiconductor element are.

Example 1
First, chromium was vacuum-deposited to a thickness of 5 nm and gold to a thickness of 50 nm on a glass substrate (film thickness 0.7 mm) through a mask by resistance heating, thereby forming a gate electrode 510 of a first semiconductor element and a gate electrode 511 of a second semiconductor element as shown in FIG. 5 .

Next, the gate insulating layer solution A was spin-coated onto the substrate (2000 rpm x 30 seconds) and heat-treated at 200°C for 1 hour under a nitrogen stream to form gate insulating layers 520 and 521 with a thickness of 600 nm.

Next, gold was vacuum-deposited to a film thickness of 50 nm by resistance heating, and photoresist (product name "LC100-10cP", manufactured by Rohm and Haas Co., Ltd.) was applied thereon by spin coating (1000 rpm x 20 seconds), and dried by heating at 100°C for 10 minutes. Next, the photoresist film prepared as described above was pattern-exposed through a mask using a parallel light mask aligner (Canon Inc., PLA-501F), and then shower-developed for 70 seconds with a 2.38% by weight aqueous solution of tetramethylammonium hydroxide (product name "ELM-D", manufactured by Mitsubishi Gas Chemical Co., Ltd.) using an automatic developing device (Takizawa Sangyo Co., Ltd., AD-2000), followed by washing with water for 30 seconds. After that, it was etched for 5 minutes with an etching solution (product name "AURUM-302", manufactured by Kanto Chemical Co., Ltd.), and then washed with water for 30 seconds. Next, the resist was removed by immersing the substrate in a stripping solution (product name "AZ Remover 100", manufactured by AZ Electronic Materials Co., Ltd.) for 5 minutes, and then the substrate was washed with water for 30 seconds and dried by heating at 120°C for 20 minutes to form the source electrode 540 and drain electrode 550 of the first semiconductor element, and the source electrode 541 and drain electrode 551 of the second semiconductor element.

The width of the source electrode 540 and drain electrode 550 of the first semiconductor element, and the source electrode 541 and drain electrode 551 of the second semiconductor element were 100 μm, and the distance between these electrodes was 30 μm. On the substrate 1 on which each electrode was formed as described above, 200 pl of semiconductor solution A1 was applied to the first semiconductor element by the inkjet method, and 100 pl of semiconductor solution A1 was applied to the second semiconductor element, and then heat treatment was performed for 30 minutes at 150° C. under a nitrogen gas flow on a hot plate to form the first semiconductor layer 560 and the second semiconductor layer 561. Next, 5 μL of solution A for forming the second insulating layer was dropped onto the first semiconductor layer 560 so as to cover the first semiconductor layer, and heat treatment was performed for 30 minutes at 110° C. under a nitrogen gas flow to form the second insulating layer 58.

In this way, the semiconductor device of Example 1 was obtained. Next, an image of the first semiconductor layer was obtained using an atomic force microscope Dimension Icon (manufactured by Bruker AXS Co., Ltd.), and the lengths of all the CNT composites present per 1 μm ² at the center of the first semiconductor layer were measured and added up to 16 μm. Similarly, the total length of the CNT composites present per 1 μm ² in the second semiconductor layer was measured to be 11 μm. In addition, when the above evaluation was performed on this semiconductor device, the gain was 29, and the V _in at which V _out changed was 5.9 V.

Example 2
A semiconductor device was fabricated in the same manner as in Example 1, except that 10 μL of a 5% by mass propylene glycol 1-monomethyl ether 2-acetate solution of polystyrene (manufactured by Aldrich, weight average molecular weight (Mw): 192,000, hereinafter referred to as PS) was drop-cast onto the second semiconductor layer 561 of the second semiconductor element, and the solution was air-dried at 30° C. for 5 minutes, and then heat-treated at 120° C. for 30 minutes under a nitrogen stream on a hot plate to form a second semiconductor element having a third insulating layer. The total length of the CNT complexes present per 1 μm ² in the first semiconductor layer was measured in the same manner as in Example 1, and was found to be 16 μm. The total length of the CNT complexes present per 1 μm ² in the second semiconductor layer was measured and was found to be 11 μm. The above evaluation of this semiconductor device was also performed, and the gain was 30, and the V _in at which V _out changed was 5.7 V.

Example 3
A semiconductor device was fabricated in the same manner as in Example 1, except that the first semiconductor layer of the first semiconductor element was formed by dropping 250 pl of the semiconductor solution A1, and the second semiconductor layer of the second semiconductor element was formed by dropping 200 pl of the semiconductor solution A1. The total length of the CNT complexes present per 1 μm ² in the first semiconductor layer was measured in the same manner as in Example 1, and was found to be 18 μm. The total length of the CNT complexes present per 1 μm ² in the second semiconductor layer was measured, and was found to be 16 μm. The above evaluation of this semiconductor device was also performed, and the gain was 7, and the V _in at which V _out changed was 7.9 V.

Example 4
A semiconductor device was fabricated in the same manner as in Example 1, except that the first semiconductor layer of the first semiconductor element was formed by dropping 100 pl of the semiconductor solution A2, and the second semiconductor layer of the second semiconductor element was formed by dropping 250 pl of the semiconductor solution A1. The total length of the CNT complexes present per 1 μm ² in the first semiconductor layer was measured in the same manner as in Example 1, and was found to be 24 μm. The total length of the CNT complexes present per 1 μm ² in the second semiconductor layer was measured, and was found to be 18 μm. The above evaluation of this semiconductor device was also performed, and the gain was 19, and the V _in at which V _out changed was 6.1 V.

Example 5
A semiconductor device was fabricated in the same manner as in Example 1, except that the first semiconductor layer of the first semiconductor element was formed by dropping 100 pl of the semiconductor solution A2, and the second semiconductor layer of the second semiconductor element was formed by dropping 100 pl of the semiconductor solution A1. The total length of the CNT complexes present per 1 μm ² in the first semiconductor layer was measured in the same manner as in Example 1, and was found to be 24 μm. The total length of the CNT complexes present per 1 μm ² in the second semiconductor layer was measured, and was found to be 11 μm. The above evaluation of this semiconductor device was also performed, and the gain was 38, and the V _in at which V _out changed was 4.8 V.

Example 6
A semiconductor device was produced in the same manner as in Example 5, except that solution B for producing the second insulating layer was used instead of solution A for producing the second insulating layer, and the total length of the CNT composites present per 1 μm ² in the first semiconductor layer was measured in the same manner as in Example 1, and was found to be 24 μm. In addition, the total length of the CNT composites present per 1 μm ² in the second semiconductor layer was measured and was found to be 11 μm. In addition, when the above evaluation was performed on this semiconductor device, the gain was 34, and the V _in at which V _out changed was 4.5 V.

Example 7
A semiconductor device was fabricated in the same manner as in Example 1, except that the first semiconductor layer of the first semiconductor element was formed by dropping 3000 pl of the semiconductor solution A1, and the second semiconductor layer of the second semiconductor element was formed by dropping 100 pl of the semiconductor solution A2. The total length of the CNT complexes present per 1 μm ² in the first semiconductor layer was measured in the same manner as in Example 1, and was 80 μm. The total length of the CNT complexes present per 1 μm ² in the second semiconductor layer was measured, and was 24 μm. The above evaluation of this semiconductor device was also performed, and the gain was 18, and the V _in at which V _out changed was 3.8 V.

Example 8
A semiconductor device was fabricated in the same manner as in Example 1, except that the first semiconductor layer of the first semiconductor element was formed by dropping 1000 pl of the semiconductor solution A1, and the second semiconductor layer of the second semiconductor element was formed by dropping 70 pl of the semiconductor solution A1. The total length of the CNT complexes present per 1 μm ² in the first semiconductor layer was measured in the same manner as in Example 1, and was found to be 53 μm. The total length of the CNT complexes present per 1 μm ² in the second semiconductor layer was measured and was found to be 7 μm. The above evaluation of this semiconductor device was also performed, and the gain was 5, and the V _in at which V _out changed was 1.9 V.

Example 9
A semiconductor device was fabricated in the same manner as in Example 1, except that the first semiconductor layer of the first semiconductor element was formed by dropping 3000 pl of the semiconductor solution A1, and the second semiconductor layer of the second semiconductor element was formed by dropping 200 pl of the semiconductor solution A1. The total length of the CNT complexes present per 1 μm ^{2 in the first semiconductor layer was measured in the same manner as in Example 1, and was 80 μm. The total length of the CNT complexes present per 1 μm 2 in} the second semiconductor layer was measured, and was 16 μm. The above evaluation of this semiconductor device was also performed, and the gain was 15, and the V _in at which V _out changed was 3.2 V.

Examples 10 to 12
Semiconductor devices were fabricated in the same manner as in Example 2, except that third insulating layer solutions A, B, and C were used, respectively, as shown in Table 1, instead of the 5 mass % propylene glycol 1-monomethyl ether 2-acetate solution of PS. As in Example 1, the total length of the CNT hybrids present per ^μm2 in the first and second semiconductor layers was measured, and the above evaluation was performed on each semiconductor device.

Example 13
Except for setting the distance between source electrode 541 and drain electrode 551 of the second semiconductor element to 35 μm, semiconductor devices were fabricated in the same manner as in Example 1. As in Example 1, the total length of CNT hybrids present per ^μm2 in the first and second semiconductor layers was measured, and the above evaluation was performed on each semiconductor device.

Example 14
A semiconductor device was fabricated in the same manner as in Example 1, except that the second semiconductor layer of the second semiconductor element was formed by depositing 200 pl of semiconductor solution A1, and the distance between the electrodes of source electrode 541 and drain electrode 551 of the second semiconductor element was set to 60 μm. As in Example 1, the total length of the CNT complexes present per ^μm2 in the first and second semiconductor layers was measured, and the above evaluation was performed on each semiconductor device.

Example 15
Except for setting the distance between source electrode 541 and drain electrode 551 of the second semiconductor element to 130 μm, semiconductor devices were fabricated in the same manner as in Example 14. As in Example 1, the total length of the CNT complexes present per ^μm2 in the first and second semiconductor layers was measured, and the above evaluation was performed on each semiconductor device.

Example 16
Except for setting the distance between source electrode 540 and drain electrode 550 of the first semiconductor element to 10 μm and the distance between source electrode 541 and drain electrode 551 of the second semiconductor element to 100 μm, semiconductor devices were fabricated in the same manner as in Example 14. As in Example 1, the total length of the CNT complexes present per ^μm2 in the first and second semiconductor layers was measured, and the above evaluation was performed on each semiconductor device.

Example 17
Except for setting the distance between source electrode 540 and drain electrode 550 of the first semiconductor element to 30 μm and the distance between source electrode 541 and drain electrode 551 of the second semiconductor element to 35 μm, semiconductor devices were fabricated in the same manner as in Example 14. As in Example 1, the total length of the CNT complexes present per ^μm2 in the first and second semiconductor layers was measured, and the above evaluation was performed on each semiconductor device.

Example 18
Except for forming the second semiconductor layer of the second semiconductor element by depositing 100 pl of semiconductor solution A2, semiconductor devices were fabricated in the same manner as in Example 14. As in Example 1, the total length of the CNT complexes present per ^μm2 in the first and second semiconductor layers was measured, and the above evaluation was performed on each semiconductor device.

Example 19
A semiconductor device was fabricated in the same manner as in Example 14, except that 10 μL of the third insulating layer solution A was drop-cast onto the second semiconductor layer 561 of the second semiconductor element, air-dried at 30° C. for 5 minutes, and then heat-treated on a hot plate under a nitrogen stream at 120° C. for 30 minutes to form a second semiconductor element having a third insulating layer. As in Example 1, the total length of the CNT complexes present per μm ² in the first and second semiconductor layers was measured, and the above evaluation was performed on each semiconductor device.

Comparative Example 1
A semiconductor device was fabricated in the same manner as in Example 1, except that the first semiconductor layer of the first semiconductor element and the second semiconductor layer of the second semiconductor element were both formed by dropping 100 pl of semiconductor solution A1. The total lengths of the CNT complexes present per 1 ^μm2 in the first semiconductor layer and the second semiconductor layer were measured in the same manner as in Example 1, and both were 11 μm. In addition, when the above evaluation was performed on this semiconductor device, V _out only changed from 10 V to 4 V in response to a change in V _in from 0 to 10 V, and complete operation of the semiconductor device was not obtained.

10, 20, 30, 50 Substrate 11, 21, 31, 510, 511 Gate electrode 12, 22, 32, 520, 521 Gate insulating layer 13, 23, 33, 540, 541 Source electrode 14, 24, 34, 550, 551 Drain electrode 15, 35, 560 First semiconductor layer 16, 58 Second insulating layer 100, 200 Distance between source electrode and drain electrode of semiconductor element 25, 561 Second semiconductor layer 41, 500 First semiconductor element 42, 501 Second semiconductor element

Claims (14)

A semiconductor device including a first semiconductor element and a second semiconductor element provided on a substrate having an insulating surface,
the first semiconductor element is an n-type semiconductor element,
A source electrode;
A drain electrode;
A gate electrode;
a first semiconductor layer in contact with the source electrode and the drain electrode;
a gate insulating layer insulating the first semiconductor layer from the gate electrode;
Including,
the second semiconductor element is a p-type semiconductor element,
A source electrode;
A drain electrode;
A gate electrode;
a second semiconductor layer in contact with the source electrode and the drain electrode;
a gate insulating layer insulating the second semiconductor layer from the gate electrode;
Including,
the semiconductor device is a complementary semiconductor device including the n-type semiconductor element and the p-type semiconductor element,
the first semiconductor layer and the second semiconductor layer both contain carbon nanotubes;
A semiconductor device characterized in that a value (Cn/Ln) obtained by dividing the total length (Cn) of the carbon nanotubes present per 1 ^μm2 of the first semiconductor layer by the distance (Ln) between the source electrode and drain electrode of the first semiconductor element is different from a value (Cp/Lp) obtained by dividing the total length (Cp) of the carbon nanotubes present per 1 ^μm2 of the second semiconductor layer by the distance (Lp) between the source electrode and drain electrode of the second semiconductor element. 2. The semiconductor device according to claim 1, wherein a value (Cp/Lp) obtained by dividing a total length (Cp) of the carbon nanotubes present per 1 ^μm2 of the second semiconductor layer by a distance (Lp) between the source electrode and drain electrode of the second semiconductor element is smaller than a value (Cn/Ln) obtained by dividing a total length (Cn) of the carbon nanotubes present per 1 ^μm2 of the first semiconductor layer by a distance (Ln) between the source electrode and drain electrode of the first semiconductor element. 3. The semiconductor device according to claim 1, wherein a value (Cp/Lp) obtained by dividing the total length (Cp) of the carbon nanotubes present per 1 ^μm2 of the second semiconductor layer by the distance (Lp) between the source electrode and drain electrode of the second semiconductor element is 0.2 to 0.8 times a value (Cn/Ln) obtained by dividing the total length (Cn) of the carbon nanotubes present per 1 ^μm2 of the first semiconductor layer by the distance (Ln) between the source electrode and drain electrode of the first semiconductor element. A semiconductor device including a first semiconductor element and a second semiconductor element provided on a substrate having an insulating surface,
the first semiconductor element is an n-type semiconductor element,
A source electrode;
A drain electrode;
A gate electrode;
a first semiconductor layer in contact with the source electrode and the drain electrode;
a gate insulating layer insulating the first semiconductor layer from the gate electrode;
Including,
the second semiconductor element is a p-type semiconductor element,
A source electrode;
A drain electrode;
A gate electrode;
a second semiconductor layer in contact with the source electrode and the drain electrode;
a gate insulating layer insulating the second semiconductor layer from the gate electrode;
Including,
the semiconductor device is a complementary semiconductor device including the n-type semiconductor element and the p-type semiconductor element,
the first semiconductor layer and the second semiconductor layer both contain carbon nanotubes;
A semiconductor device, characterized in that a total length (Cn) of the carbon nanotubes present per ^{1 μm2} of the first semiconductor layer is different from a total length (Cp ⁾ of the carbon nanotubes present per 1 μm2 of the second semiconductor layer. 5. The semiconductor device according to claim 4, wherein a total length (Cp) of said carbon nanotubes present per 1 μm ² of said second semiconductor layer is shorter than a total length (Cn) of said carbon nanotubes present per 1 μm ² of said first semiconductor layer. 6. The semiconductor device according to claim ⁴ , wherein the total length (Cp) of the carbon nanotubes present per ^{1 μm2} of the second semiconductor layer is 0.2 to 0.8 times the total length (Cn) of the carbon nanotubes present per 1 μm2 of the first semiconductor layer. The semiconductor device according to any one of claims 1 to 6, wherein the first semiconductor element further includes a second insulating layer that contacts the first semiconductor layer on the side opposite the gate insulating layer with respect to the first semiconductor layer. The semiconductor device according to any one of claims 1 to 6, wherein the first semiconductor layer further contains an n-type modifier. 8. The semiconductor device according to claim 7, wherein the second semiconductor element has a third insulating layer different from the second insulating layer, and the third insulating layer contacts the second semiconductor layer on a side opposite to the gate insulating layer with respect to the second semiconductor layer. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising the steps of applying and drying the first semiconductor layer and the second semiconductor layer. The method for manufacturing a semiconductor device according to claim 10, wherein the first semiconductor layer and the second semiconductor layer are formed by coating and drying in the same process. The method for manufacturing a semiconductor device according to claim 10 or 11, wherein the composition used to form the first semiconductor layer and the composition used to form the second semiconductor layer are the same composition. The method for manufacturing a semiconductor device according to any one of claims 10 to 12, wherein the concentration of the composition used to form the first semiconductor layer is different from the concentration of the composition used to form the second semiconductor layer. The method for manufacturing a semiconductor device according to any one of claims 10 to 13, wherein the coating amount of the composition used to form the first semiconductor layer is different from the coating amount of the composition used to form the second semiconductor layer.

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