JP7520200B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a non-lead type semiconductor device and a manufacturing method thereof.

Semiconductor devices mounted on portable devices and IC cards are required to be smaller and thinner. It is well known that the mounting area of semiconductor devices can be reduced by using a non-lead type in which the lead terminals are the same length as the package end faces.

Figure 8 shows a cross section of a non-lead type semiconductor package. The die pad 121 and the leads 122 are joined with resin 130, the semiconductor element 170 mounted on the die pad 121 is electrically connected to the leads 122 with a plating film 150 formed on the upper surface via bonding wires 171, and sealed with sealing resin 180, so that the outer surface of the leads 122 and the side of the sealing resin 180 form the same plane.

In the illustrated non-lead type semiconductor package, the die pad 121 is hexagonal in cross section, with a bulging shape at the center in the thickness direction of the die pad 121. The lead 122 has a structure in which the width of the top surface to which the bonding wire 171 is connected is longer in the direction of the die pad 121 in cross section, and the width of the bottom surface is shorter. In other words, the top surface of the lead 122 has a convex eaves portion facing the die pad 121. This structure prevents the die pad 121 and the lead 122 from easily falling out of the resin 130 and the sealing resin 180 (see, for example, Patent Document 1).

JP 2003-309241 A

However, in the non-lead type semiconductor package described in Patent Document 1, by providing a convex eaves portion on the lead 122, the planar area of the top surface of the lead 122 becomes larger than the planar area of the bottom surface of the lead 122 exposed from the resin 130. Furthermore, in order to prevent the lead 122 from falling off, the eaves must be of a certain thickness, which makes the lead 122 itself thicker. As described above, providing eaves portions on the leads is an obstacle to miniaturization and thinning.

The present invention has been made in consideration of the above problems, and aims to provide a small, thin semiconductor device that prevents the leads from falling off from the sealing resin.

In order to solve the above problems, the present invention uses the following means:

A semiconductor chip;
leads arranged around the semiconductor chip;
a connection member for connecting the semiconductor chip and the leads;
a sealing resin that seals the semiconductor chip, the leads, and the connection members,
The semiconductor device is characterized in that the bottom surfaces of the leads are exposed from the sealing resin, and the side surfaces of the leads are provided with tapered through grooves that reach from the top surfaces of the leads to the bottom surfaces of the leads.
Also, a step of preparing a lead frame having leads with through grooves;
backgrinding the semiconductor wafer;
half-cut dicing from the back surface of the semiconductor wafer;
a step of attaching a back surface of the semiconductor wafer to a dicing tape and full-cut dicing the semiconductor wafer from a front surface;
a step of expanding the dicing tape to widen a dimension between the individual semiconductor chips to the same dimension as a pitch size of the lead frame;
a step of bonding the dicing tape and the lead frame;
connecting the semiconductor chip and the leads with a connecting member;
a step of sealing the semiconductor chip, the leads, and the connection members with a sealing resin;
cutting the sealing resin and the leads;
and peeling the dicing tape from the leads, the semiconductor chip, and the sealing resin.

By using the above method, it is possible to obtain a small and thin semiconductor device while preventing the leads and die pad from falling off from the sealing resin.

1A and 1B are a cross-sectional view and a bottom view of a semiconductor device according to a first embodiment of the present invention; 2 is an enlarged cross-sectional view of a groove of the semiconductor device according to the first embodiment of the present invention. FIG. 1A and 1B are a cross-sectional view and a bottom view of a semiconductor device according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention. 11A to 11C are schematic diagrams showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. 5A to 5C are schematic diagrams showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. FIG. 1 is a cross-sectional view of a conventional non-lead type semiconductor package.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will now be described with reference to the drawings.
First Embodiment
1A and 1B are a cross-sectional view and a bottom view of a semiconductor device according to a first embodiment of the present invention. First, the configuration of a semiconductor device 10 will be described with reference to the cross-sectional view of FIG. 1A. A semiconductor chip 1 is fixed onto a die pad 5 via a die attach layer 3. Leads 4 are provided around the die pad 5 at a distance from the die pad 5. An electrode pad (not shown) provided on the upper surface of the semiconductor chip 1 and the upper surface of the lead 4 are electrically connected via a bonding wire 2, which is a connecting member. Gold (Au) or copper (Cu) is used as the material for the bonding wire 2.

The semiconductor chip 1, die pad 5, and bonding wires 2 are covered with sealing resin 6, and the bottom surface of the die pad 5 is also covered with a thin sealing resin 6 that does not hinder the thinning of the semiconductor device 10. If it does hinder the thinning of the semiconductor device 10, the die pad 5 may be structured to be thin.

In contrast, in the case of the lead 4, the top surface of the lead 4 and the inner surface 4b of the lead 4 facing the die pad 5 are covered with the sealing resin 6, and the outer surface 4a, which is the side of the lead 4 that does not face the die pad 5, and the bottom surface of the lead 4 are exposed from the sealing resin 6. The semiconductor device 10 is rectangular in cross section, and most of the outer surface of the semiconductor device 10 is covered with the sealing resin 6, with the lead 4 partially exposed from the sealing resin 6. The bottom surface of the lead 4 and the bottom surface of the sealing resin 6 form the same plane, and the outer surface 4a of the lead 4 and the side surface of the sealing resin 6 form the same plane. In addition, although not shown, a plating film is applied to the bottom surface and outer surface 4a of the lead 4 exposed from the sealing resin 6, which improves the bonding between the semiconductor device 10 and the wiring board when mounted.

A through groove 7 is formed on the side of the lead 4 facing the front of the page, with a tapered side in cross section. The through groove 7 is a groove that reaches from the top surface to the bottom surface of the lead 4, and is filled with sealing resin 6. The sealing resin 6 filled in this through groove 7 is firmly connected to the sealing resin 6 that covers the periphery of the lead 4, including the top surface. This structure prevents the lead 4 from easily falling out of the sealing resin 6, improving the resistance of the lead 4 to falling out.

The through groove 7 shown in the figure is a semi-frustum shape with forward tapered side surfaces, and the opening width at the top surface of the lead 4 is smaller than the opening width at the bottom surface of the lead 4. In other words, in a plan view, the area opening at the top surface of the lead 4 is smaller than the area opening at the bottom surface of the lead 4.

Figure 1(b) is a bottom view of the semiconductor device shown in Figure 1(a) viewed from below. Four leads 4 are arranged on one side of the sealing resin 6, which has four sides, and the other four leads 4 are arranged on the opposing side. A semicircular through groove 7 is provided on the side 4c that is perpendicular to both the outer side 4a and the inner side 4b of each lead 4. The semicircle with the larger radius of curvature of the through groove 7 shown concentrically indicates the portion that opens into the bottom surface of the lead 4, and the semicircle with the smaller radius of curvature indicates the portion that opens into the top surface of the lead 4.

Each lead 4 has two through grooves 7, but the number of through grooves 7 may be increased to improve the resistance of the leads 4 to falling off. The top surface of the lead 4 to which the bonding wire 2 is bonded may be outside the semicircle with the small radius of curvature, i.e., outside the opening, and the bonding wire 2 may be partially bonded to the area defined between the semicircle with the small radius of curvature and the semicircle with the large radius of curvature. Note that the bottom surface of the die pad 5 is not shown in this bottom view because it is covered with a thin sealing resin 6.

To make semiconductor devices smaller and thinner, it is necessary to reduce the lead width and thickness. In particular, when making the thickness of a semiconductor device 200 μm or less, the lead thickness is 50 μm or less. However, in a structure with a convex eaves as shown in FIG. 8, the presence of the eaves is an obstacle to making the device smaller and thinner, making it difficult to make the lead thickness 50 μm or less.

In contrast, the semiconductor device 10 of the first embodiment of the present invention does not have a convex eaves portion, and has a structure in which the side of the lead 4 has a lead-fall-out prevention portion such as a concave through groove 7, so there is no need to increase the width of the lead 4 more than necessary, and therefore miniaturization can be achieved. Also, in a structure with an eaves portion, the eaves portion needs to be of a certain thickness to have sufficient fall-out prevention properties, and this makes the lead itself thicker, which hinders thinning. However, in the semiconductor device 10 of the first embodiment of the present invention, the vertical length of the through groove 7 is equivalent to the thickness of the lead, so fall-out prevention properties can be ensured without thickening the lead 4, and a thin structure can be achieved.

The above describes an embodiment in which leads are arranged on one side of the sealing resin 6, which has four sides, and the side opposite it, but it is also possible to apply this to a semiconductor device in which leads are arranged on all four sides.

Figure 2 is an enlarged cross-sectional view of a groove of a semiconductor device according to a first embodiment of the present invention. Figure 2(a) is an enlarged cross-sectional view of the through groove 7 in the shape of a semi-frustum cone with forward tapered side faces shown in Figure 1(a), and the inside of the through groove 7 is filled with sealing resin 6. Figure 2(b) shows the through groove 7 in the shape of an inverted semi-frustum cone with reverse tapered side faces. The opening width at the top surface of the lead 4 is larger than the opening width at the bottom surface of the lead 4. In other words, in a plan view, the area opening at the top surface of the lead 4 is larger than the area opening at the bottom surface of the lead 4. The through groove 7 is filled with sealing resin 6.

Figure 2(c) shows a lead 4 with a structure different from that shown in Figure 2(a) in that a step portion 11 is provided on the tapered side of the through groove 7, which is a semi-frustum of a cone with a forward tapered side. The step portion 11 is provided midway along the tapered side, resulting in a structure that further improves the prevention of falling off. This structure may also be applied to Figure 2(b), in which a step portion 11 is provided on the tapered side of the through groove 7, which is a semi-frustum of a cone with a reverse tapered side.

Figure 2(d) shows a lead 4 with a structure different from that shown in Figure 2(a) in that a spiral groove 12 is provided on the tapered side of a through groove 7 in the shape of a semi-frustum of a cone having a forward tapered side. By forming a plurality of spiral grooves 12 obliquely along the tapered side, the sealing resin 6 penetrates into the spiral groove 12, further improving the prevention of falling off. This structure may be applied to Figure 2(b) to form a structure in which a spiral groove 12 is provided on the tapered side of a through groove 7 in the shape of an inverted semi-frustum of a cone having a reverse tapered side.
Second Embodiment
3A and 3B are cross-sectional and bottom views of a semiconductor device according to a second embodiment of the present invention. First, the configuration of the semiconductor device 10 will be described with reference to the cross-sectional view of FIG. 3A. A semiconductor chip 1 is fixed onto a die pad 5 via a die attach layer 3. Leads 4 are provided around the die pad 5 at a distance from the die pad 5. An electrode pad (not shown) provided on the upper surface of the semiconductor chip 1 and the upper surface of the lead 4 are electrically connected via a bonding wire 2, which is a connecting member. Gold (Au) or copper (Cu) is used as the material for the bonding wire 2.

The semiconductor chip 1, die pad 5, and bonding wires 2 are covered with sealing resin 6, but the bottom surface of the die pad 5 is exposed from the sealing resin 6. A through groove 8 having a tapered side in cross section is formed on the side surface of the die pad 5 facing the viewer in the drawing. The through groove 8 is a groove that reaches from the top surface to the bottom surface of the die pad 5, and is filled with sealing resin 6. The sealing resin 6 filled in this through groove 8 is firmly connected to the sealing resin 6 that covers the periphery of the die pad 5, including the top surface. This structure prevents the die pad 5 from easily falling out of the sealing resin 6, improving the ability of the die pad 5 to prevent falling off.

In the case of the lead 4, the top surface of the lead 4 and the inner side surface 4b of the lead 4 facing the die pad 5 are covered with the sealing resin 6, and the outer side surface 4a, which is the side surface of the lead 4 that does not face the die pad 5, and the bottom surface of the lead 4 are exposed from the sealing resin 6. The semiconductor device 10 is rectangular in cross section, and most of the outer surface of the semiconductor device 10 is covered with the sealing resin 6, with the lead 4 partially exposed from the sealing resin 6. The bottom surface of the die pad 5, the bottom surface of the lead 4, and the bottom surface of the sealing resin 6 form the same plane, and the outer side surface 4a of the lead 4 and the side surface of the sealing resin 6 form the same plane. Although not shown, a plating film is applied to the bottom surface of the die pad 5 exposed from the sealing resin 6 and the bottom surface and outer side surface 4a of the lead 4, which are exposed from the sealing resin 6, to improve the bonding between the semiconductor device 10 and the wiring board when mounted.

A through groove 7 is formed on the side of the lead 4 facing the front of the page, with a tapered side in cross section. The through groove 7 is a groove that reaches from the top surface to the bottom surface of the lead 4, and is filled with sealing resin 6. The sealing resin 6 filled in this through groove 7 is firmly connected to the sealing resin 6 that covers the periphery of the lead 4, including the top surface. This structure prevents the lead 4 from easily falling out of the sealing resin 6, improving the resistance of the lead 4 to falling out.

The through groove 7 shown in the figure is a semi-frustum shape with forward tapered side surfaces, and the opening width at the top surface of the lead 4 is smaller than the opening width at the bottom surface of the lead 4. In other words, in a plan view, the area opening at the top surface of the lead 4 is smaller than the area opening at the bottom surface of the lead 4.

Figure 3(b) is a bottom view of the cross-sectional view shown in Figure 3(a) viewed from below. Four leads 4 are arranged on one side of the sealing resin 6, which has four sides, and the other four leads 4 are arranged on the opposing side. A semicircular through groove 7 is provided on the side 4c that is perpendicular to both the outer side 4a and the inner side 4b of each lead 4. The semicircle with the larger radius of curvature of the through groove 7 shown concentrically indicates the portion that opens into the bottom surface of the lead 4, and the semicircle with the smaller radius of curvature indicates the portion that opens into the top surface of the lead 4.

Each lead 4 has two through grooves 7, but the number of through grooves 7 may be increased to improve the resistance of the lead 4 to falling off, and through grooves 7 may be formed on the inner surface 4b of the lead 4 in addition to the two sides shown in the figure. The upper surface of the lead 4 to which the bonding wire 2 is bonded may be outside the semicircle with the small radius of curvature, i.e., outside the opening, and the bonding wire 2 may be partially bonded to the area defined between the semicircle with the small radius of curvature and the semicircle with the large radius of curvature.

Between the leads 4 arranged on one side and the leads 4 arranged along the other side, the die pad 5 is arranged at a distance from them. Of the four sides that make up the die pad 5, a through groove 8 is provided on each of two opposing sides. Here, the through grooves 8 provided in the die pad 5 are arranged parallel to the through grooves 7 provided in the leads 4. The area enclosed by a dotted line inside the die pad 5 is the area where the semiconductor chip 1 is projected onto a plane, but the through grooves 8 are formed outside this area. This is to prevent excess die attachment material from leaking into the through grooves 8 when the semiconductor chip 1 is die-bonded.

In the figure, a total of four through grooves 8 are provided on two opposing sides of the die pad 5, i.e., on two opposing side surfaces of the die pad 5, but the number of through grooves 8 may be increased to improve the ability of the die pad 5 to prevent it from falling off, and through grooves 8 may be formed on all four sides of the die pad 5, i.e., on all side surfaces of the die pad 5.

In the semiconductor device 10 according to the second embodiment of the present invention, the shape and arrangement of the leads 4 are the same as those of the semiconductor device 10 according to the first embodiment shown in Fig. 1, and further, the die pad 5 is also structured to be exposed from the sealing resin 6. As described above, the die pad 5 is also structured to have a lead-fall-out prevention portion such as a recessed through groove 8, so that it is not necessary to increase the width of the die pad 5 more than necessary, and therefore miniaturization can be achieved. In addition, since the vertical length of the through groove 8 provided in the die pad 5 is equivalent to the thickness of the die pad 5, it is possible to ensure fall-out prevention without making the die pad 5 thick, and a thin structure can also be achieved.
Third Embodiment
FIG. 4 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

The difference from the semiconductor device 10 shown in FIG. 3 is that the die pad 5 is not provided, and the bottom surface of the semiconductor chip 1 is directly exposed from the bottom surface of the sealing resin 6. However, the bottom edge of the semiconductor chip 1 has a chamfered portion to form an inverted mesa shape so that the semiconductor chip 1 does not fall out of the sealing resin 6. By making it in this shape, the sealing resin 6 penetrates into the edge of the bottom surface of the semiconductor chip 1 during resin sealing, and the semiconductor chip 1 can be held within the sealing resin 6, improving the prevention of the semiconductor chip 1 from falling out. The shape of the lead 4 is the same as that of the semiconductor device 10 of the second embodiment of the present invention described above. The bottom surface of the semiconductor chip 1, the bottom surface of the lead 4, and the bottom surface of the sealing resin 6 form the same plane, and the outer surface 4a of the lead 4 and the side surface of the sealing resin 6 form the same plane. In addition, although not shown, a plating film is applied to the bottom surface of the semiconductor chip 1 exposed from the sealing resin 6 and the bottom surface and outer surface 4a of the lead 4, which improve the bonding between the semiconductor device 10 and the wiring board when mounted.

Next, an example of a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to Figures 5 and 6.

First, as shown in FIG. 5(a), a metal plate made of copper or a copper alloy is prepared, and a tapered through hole is formed at a predetermined position by punching. In the next punching process, the plate is cut across the center of the through hole to produce a lead frame 20 equipped with leads 4 having through grooves 7. The leads 4 are connected to a frame 21, which is the frame of the lead frame 20. The leads 4 within one frame 21 are used as components of one semiconductor device. Therefore, the leads 4 provided adjacent to both sides of the frame 21 are components of different semiconductor devices (STEP 1).

Next, as shown in FIG. 5(b), the semiconductor wafer 30 is attached to the backgrind tape 51, and the semiconductor wafer 30 is backgrinded to a predetermined thickness. Then, half-cut dicing is performed from the backside of the semiconductor wafer 30 attached to the backgrind tape 51. The first blade 41 used in this process is wide and has a wide-angle pyramid shape at the tip, and only the pyramid portion penetrates into the semiconductor wafer 30 to dice it. The cutting tip angle A of the tip of the first blade 41 is in the range of 80 to 100 degrees, and a triangular cut groove 13 is formed on the backside of the semiconductor wafer 30 in cross section (STEP 2).

Next, as shown in FIG. 5(c), the back surface of the semiconductor wafer 30 is attached to a heat-resistant dicing tape 52, and full-cut dicing is performed from the front surface of the semiconductor wafer 30 using a second blade 42 to obtain an inverted mesa-shaped semiconductor chip 1. The dicing tape 52 used must be heat-resistant so that it will not decompose even at the temperature (200°C) that will be applied in the subsequent resin sealing process. The second blade 42 is narrower than the first blade 41. The cutting groove 14 formed by the second blade 42 has a straight shape and reaches from the front surface of the semiconductor wafer 30 to the top of the cutting groove 13.

When the thickness of the semiconductor wafer 30 after backgrinding is 100 μm, the thickness of the first blade 41 is in the range of 50 to 100 μm. The thickness of the second blade 42 is preferably in the range of 20 to 40 μm. When the thickness of the semiconductor wafer 30 after backgrinding is 150 μm, the thickness of the first blade 41 is preferably in the range of 100 to 150 μm, and the thickness of the second blade 42 is preferably in the range of 20 to 40 μm (STEP 3).

Next, as shown in FIG. 6(a), the dicing tape 52 is expanded after full-cut dicing to expand the dimension between the individual semiconductor chips 1 to the same dimension as the pitch size of the lead frame 20. Then, the lead frame 20 prepared in advance is attached to the expanded dicing tape 52. This allows the semiconductor chip 1 to be placed between the opposing leads 4 of the lead frame 20 (STEP 4).

Next, as shown in FIG. 6(b), the electrode pads provided on the upper surface of the semiconductor chip 1 and the upper surfaces of the leads 4 are electrically connected by bonding wires 2, which are connecting members, and then the semiconductor chip 1 and the leads 4 are attached to the dicing tape 52 and then sealed with resin (STEP 5).

Next, as shown in FIG. 6(c), after the resin sealing, the sealing resin 6 and the leads 4 are continuously cut with a third blade 43. At this time, the thickness of the third blade is made thicker than the width of the frame 21, and the frame 21 connecting the adjacent leads 4 is cut away and removed (STEP 6).

Finally, as shown in FIG. 6(d), the dicing tape 52 is peeled off the leads 4, the semiconductor chip 1, and the sealing resin 6, and then a plating film (not shown) is formed on the bottom and outer sides 4a of the leads 4 exposed from the sealing resin 6, and on the bottom surface of the semiconductor chip 1, to obtain the semiconductor device 10 (STEP 7).

Next, we will explain other manufacturing methods.

First, follow steps 1 and 2 in the previous example.

Next, heat-resistant tape 53 is attached to the back surface of the lead frame 20.

Next, carry out the process shown in STEP 3 of the previous example.

Next, the semiconductor wafer 30 after full-cut dicing is slightly expanded, and the individual semiconductor chips 1 are picked up and mounted at predetermined positions on the heat-resistant tape 53 attached to the lead frame 20. The predetermined position of the semiconductor chip 1 is between the opposing leads 4.

Next, follow steps 5 to 7 in the previous example.

By carrying out the steps described above, the semiconductor device 10 according to the third embodiment of the present invention is obtained. The semiconductor device 10 obtained by this manufacturing method is small and thin, and further has good mountability on a wiring board.
Fourth Embodiment
7 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device 10 of this embodiment does not have a die pad 5, and the semiconductor chip 1 is flip-chip connected to the leads 4 via bumps 9. When using bonding wires 2 as a connecting member, the loop height of the bonding wires 2 needs to be higher than the top surface of the semiconductor chip 1, but in the case of flip-chip connection using bumps 9 as a connecting member as in the semiconductor device 10 of this embodiment, the thickness equivalent to the loop height can be reduced. This makes it possible to realize a thin semiconductor device 10.

In addition, because the semiconductor chip 1 and the leads 4 are overlapped, the distance between the semiconductor chip 1 and the leads 4 can be shortened compared to wire connection, making it possible to realize an even smaller semiconductor device 10. As described above, the semiconductor device 10 of the fourth embodiment of the present invention can be made even smaller and thinner.

The semiconductor device according to the present invention can be used in portable toys, healthcare products, wearable terminals, mobile terminals, card terminals, home appliances, etc. It can also be used in harsh environments such as in-vehicle and outdoor applications.

REFERENCE SIGNS LIST 1 Semiconductor chip 2 Bonding wire 3 Die attach layer 4 Lead 4a Outer surface 4b Inner surface 4c Side surface 5 Die pad 6 Sealing resin 7, 8 Through groove 9 Bump 10 Semiconductor device 11 Step portion 12 Spiral groove 13, 14 Cut groove 20 Lead frame 21 Frame 30 Semiconductor wafer 41, 42, 43 Blade 51 Backgrind tape 52 Dicing tape 53 Heat-resistant tape A Cut tip angle

Claims (7)

A semiconductor chip;
leads arranged around the semiconductor chip;
a connection member for connecting the semiconductor chip and the leads;
a sealing resin that seals the semiconductor chip, the leads, and the connection members,
A semiconductor device characterized in that the bottom surface of the lead is exposed from the sealing resin, and the side surface of the lead is provided with a semi-frustum-shaped through groove having a tapered side surface that reaches from the top surface of the lead to the bottom surface of the lead. The semiconductor device according to claim 1, characterized in that the semiconductor chip is mounted on a die pad, the bottom surface of the die pad is exposed from the sealing resin, and the side surface of the die pad is provided with a semi-frustum-shaped through groove having a tapered side surface that reaches from the top surface of the die pad to the bottom surface of the die pad. The semiconductor device according to claim 1, characterized in that the semiconductor chip has a chamfered portion at the edge of its bottom surface, the bottom surface of the semiconductor chip is exposed from the sealing resin, and the chamfered portion is covered with the sealing resin. The semiconductor device according to claim 1, characterized in that the semiconductor chip is flip-chip connected to the leads. The semiconductor device according to any one of claims 1 to 4, characterized in that the area of the through groove opening to the top surface of the lead is larger than the area of the through groove opening to the bottom surface of the lead. The semiconductor device according to any one of claims 1 to 4, characterized in that the area of the through groove opening to the top surface of the lead is smaller than the area of the through groove opening to the bottom surface of the lead. The semiconductor device according to claim 5 or 6, characterized in that a spiral groove is provided on the side of the through groove.

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