JP7450367B2 - Synchronous acquisition circuit - Google Patents

Description

The present invention relates to a synchronization acquisition circuit used in a receiver that receives code-spread signals.

BACKGROUND ART Synchronization acquisition circuits for receivers of spread spectrum modulated waves using M-sequence or GOLD codes have been known (for example, see Patent Document 1).

The synchronization acquisition circuit described in Patent Document 1 generates a predetermined phase error vector in which integral loss due to phase change of information modulation is suppressed, based on a correlation calculation result between a received baseband signal and a spreading code of an M sequence or a GOLD code. is generated, and cyclic integration is performed on a predetermined phase error vector during correlation calculation. This synchronization acquisition circuit further generates a delay profile based on the signal sequence after cyclic integration, detects a code phase difference corresponding to the maximum value of the delay profile, and detects a code phase difference based on the code phase difference and the signal sequence after cyclic integration. to generate an error signal for frequency deviation correction.

Japanese Patent Application Publication No. 2006-261985

However, it may be difficult to implement a synchronization acquisition circuit for a receiver of a spread spectrum modulated wave using an M sequence or a GOLD code using an FPGA (Field Programmable Gate Array). Conventional synchronization acquisition circuits use many delay elements to perform correlation calculations between the spreading code and the received signal on a chip-by-chip basis. The delay element requires several logic elements. This is because the number of multipliers or logic elements required to implement the correlation processing function may exceed the number of multipliers or logic elements available in the FPGA.

Therefore, it is an object of the present invention to provide a synchronization acquisition circuit that is easy to implement using an FPGA.

The synchronization acquisition circuit according to the first aspect of the present invention includes a first spreading code that is a pseudorandom number having a first sequence length and changing in a first chip time, and a first spreading code having a second sequence length and a first spreading code that is a pseudorandom number that changes in a first chip time. The product of the first sequence length and the second sequence length obtained by multiplying the chip time by the second spreading code, which is a pseudo-random number that changes with the second chip time divided by the second sequence length. A spread spectrum receiver receives a signal spread by a cascaded spreading code which is a pseudo-random number that has a cascaded code sequence length of and changes in the second chip time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position in a cascade code sequence length of a cascade-coupled spreading code to be multiplied by a received signal of a second sequence length, the circuit comprising: a second correlation value calculation unit that calculates a second correlation value that is the sum of the products of the signal and each second spreading code; The second correlation value calculated by the second correlation value calculation unit by shifting the received signal by one time point is the number of storage units that is equal to or greater than the number obtained by multiplying the minimum number of units, which is the number obtained by subtracting 1 from the sequence length of 1. The sum of the products of each second correlation value of the number of first sequence lengths and each first spreading code calculated by the second correlation value storage unit and the number of first sequence lengths calculated by the second correlation value calculation unit at the time of each interval number. A first correlation value calculation section that calculates a certain first correlation value, a power calculation section that calculates the power of the first correlation value, and a power equal to the number of cascade-connected code sequence lengths calculated by shifting the received signal by one time point. and a peak detection unit that determines the synchronization sequence position based on the position where the maximum value of the power stored in the power storage unit is obtained. The second correlation value storage unit stores a number of second correlation values equal to or greater than the ordered first sequence length and stores a number of second correlation values obtained by adding 1 to the number of intervals calculated by the second correlation value calculation unit at consecutive points in time. , including DPRAM, which is a RAM that can be read and written at the same time. The first correlation value calculation unit calculates the second correlation values read out from the DPRAM in which the order is consecutive among the second correlation values read out one by one from the DPRAM in which the order of the number equal to or greater than the first sequence length is consecutive from the beginning. A first correlation value is calculated using a number of second correlation values with a sequence length of 1. A DPRAM in which a second correlation value that is not stored in the second correlation value storage unit is written to the first DPRAM, and which is not the last in the order among the DPRAMs from which the second correlation value is read when calculating the first correlation value. The second correlation value read from is written to the next sequential DPRAM.

A synchronization acquisition circuit according to a second aspect of the present invention includes a first spreading code that is a pseudorandom number having a first sequence length and changing in a first chip time, and a first spreading code having a second sequence length and a first spreading code that is a pseudorandom number that changes in a first chip time. The product of the first sequence length and the second sequence length obtained by multiplying the chip time by the second spreading code, which is a pseudo-random number that changes with the second chip time divided by the second sequence length. A spread spectrum receiver receives a signal spread by a cascaded spreading code which is a pseudo-random number that has a cascaded code sequence length of and changes in the second chip time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position in a cascade code sequence length of a cascade-coupled spreading code to be multiplied by a received signal of a second sequence length, the circuit comprising: a second correlation value calculation unit that calculates a second correlation value that is the sum of the products of the signal and each second spreading code; a first correlation value calculation unit that calculates a first correlation value that is the sum of the products of each second correlation value of the number of first sequence lengths calculated by the second correlation value calculation unit at a time point and each first spreading code; a power calculation unit that calculates the power of the first correlation value; a power storage unit that stores the power of the number of cascade-connected code sequence lengths calculated by shifting the received signal by one time point; and a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value. At least one of the second correlation value calculation section and the first correlation value calculation section is a selector that generates a signal that is the product of two input signals from one signal and switches and outputs a binary value depending on the other signal. including. When the second correlation value calculation section includes a selector, the selector outputs each received signal as it is when the code of each second spreading code is "+1", and outputs each received signal as is, and When the sign of is "-1", the two's complement number of each received signal is output.

According to the synchronization acquisition circuit of the first aspect of the present invention, the number of logic elements required to implement the correlation processing function can be reduced compared to the case where delay elements are used. Easier to implement.

According to the synchronization acquisition circuit according to the second aspect of the present invention, the number of multipliers required for implementing the correlation processing function can be reduced, so that the implementation of the synchronization acquisition circuit using FPGA is facilitated.

FIG. 3 is a diagram showing the configuration of a spreading code generator 300 that generates a cascade-connected spreading code PN in a spread spectrum transmitter. 3 is a diagram showing a sequence of first spreading codes CA generated by a CA generator 1001. FIG. FIG. 3 is a diagram showing a sequence of second spreading codes CB. FIG. 3 is a diagram showing a series of cascade-connected spreading codes PN. 1 is a block diagram showing the configuration of a spread spectrum receiver 1 according to the first embodiment. FIG. 2 is a diagram showing the configuration of an analog receiver 2. FIG. 3 is a diagram showing the configuration of a quadrature detector 4. FIG. 5 is a diagram showing the configuration of a timing corrector 5. FIG. It is a figure showing the structure of AGC6. 3 is a diagram showing the configuration of a despreader 7. FIG. 7 is a diagram showing the configuration of a spreading code generator 79. FIG. 3 is a diagram showing the configuration of a synchronous follow-up circuit 8. FIG. FIG. 3 is a diagram showing the relationship between timing error ΔTc and power difference ΔR ² . It is a figure showing the composition of synchronization acquisition circuit 9F of a reference example. 3 is a diagram showing a series of second correlation values B. FIG. 3 is a diagram showing a series of first correlation values A. FIG. FIG. 3 is a diagram showing a BB signal BBI3, a cascade-connected spreading code PN synchronized with the BB signal BBI3, and a despread BB signal BBI4 when the transmission data is "1". FIG. 3 is a diagram showing a BB signal BBI3, a cascade-connected spreading code PN synchronized with the BB signal BBI3, and a despread BB signal BBI4 when the transmission data is "-1". 3 is a diagram showing the configuration of a synchronization acquisition circuit 9 according to the first embodiment. FIG. 9 is a diagram showing the configuration of a chip correlation unit 903(i) in the first embodiment. FIG. 9 is a diagram showing the configuration of a chip correlation unit 912(i) in the first embodiment. FIG. 3 is a diagram for explaining the operation of DPRAM 911(i) in the first embodiment. FIG. 1 is a diagram illustrating a circuit that performs a conventional correlation process of M-sequence spreading codes; FIG. FIG. 2 is a block diagram showing the configuration of a spread spectrum receiver 1A according to Modification 1 of Embodiment 1. FIG. FIG. 3 is a diagram showing the configuration of a timing corrector 5A according to a first modification of the first embodiment. 7 is a diagram showing the configuration of a despreader 7A of a first modification of the first embodiment. FIG. FIG. 3 is a diagram showing the configuration of a synchronization acquisition circuit 9A according to a first modification of the first embodiment. 7 is a diagram for explaining the operation of DPRAM 911A(i) of Modification 1 of Embodiment 1. FIG. 9 is a diagram showing the configuration of a synchronization acquisition circuit 9P according to a second modification of the first embodiment. FIG. FIG. 9 is a diagram showing the configuration of a synchronization acquisition circuit 9Q according to a third modification of the first embodiment. 9 is a diagram showing a configuration of a synchronization acquisition circuit 9R of a fourth modification of the first embodiment. FIG. 9 is a diagram showing a configuration of a synchronization acquisition circuit 9B according to a second embodiment. FIG. FIG. 7 is a diagram showing allocation when number jw=1 of write RAM 914 in Embodiment 2. FIG. FIG. 7 is a diagram showing allocation when number jw=NA of RAM 914 for writing in the second embodiment. 12 is a diagram showing a configuration of a synchronization acquisition circuit 9C of a first modification of the second embodiment. FIG. 9 is a diagram showing the configuration of a synchronization acquisition circuit 9S of a second modification of the second embodiment. FIG. FIG. 7 is a diagram showing allocation when number jw=1 of RAM 914 for writing in Modification 2 of Embodiment 2; 12 is a diagram showing allocation when number jw of write RAM 914 is NA-1 in modification 2 of embodiment 2. FIG. 9 is a diagram showing the configuration of a synchronization acquisition circuit 9T according to a third modification of the second embodiment. FIG. 12 is a diagram showing allocation when number jw=NA of RAM 914 for writing in Modification 3 of Embodiment 2. FIG. FIG. 9 is a diagram showing allocation when number jw=1 of RAM 914 for writing in Modification 3 of Embodiment 2; 9 is a diagram showing the configuration of a synchronization acquisition circuit 9D according to the third embodiment. FIG. 9 is a diagram showing read control when write address jw=2NB*(NA-1) in Embodiment 3. FIG. 7 is a diagram showing read control when write address jw=1 in Embodiment 3. FIG. 12 is a diagram showing the configuration of a synchronization acquisition circuit 9E of a first modification of the third embodiment. FIG. 12 is a diagram showing read control when write address jw=NB*(NA-1) in Modification 1 of Embodiment 3. FIG. 9 is a diagram showing the configuration of a synchronization acquisition circuit 9U according to a second modification of the third embodiment. FIG. 12 is a diagram showing read control when write address jw=0 in Modification 2 of Embodiment 3. FIG.

Hereinafter, embodiments will be described with reference to the drawings.
Embodiment 1.
In this embodiment, a spread spectrum transmitter (not shown) spreads a transmission signal using a cascaded spreading code PN.
FIG. 1 is a diagram showing the configuration of a spreading code generator 300 that generates a cascade-connected spreading code PN in a spread spectrum transmitter.

Spreading code generator 300 includes a CA generator 1001, a CB generator 1002, and a multiplier 1003.
CA generator 1001 generates a first spreading code CA which is a pseudo-random number. CB generator 1002 generates a second spreading code CB that is a pseudo-random number. Multiplier 1003 generates a cascade-connected spreading code PN, which is a pseudo-random number, by multiplying the first spreading code CA and the second spreading code CB.

FIG. 2 is a diagram showing a sequence of first spreading codes CA generated by CA generator 1001.
The first spreading code CA is a pseudo-random number whose value is "+1" or "-1". The sequence length of the first spreading code CA is the first sequence length (NA chips). One period of the first spreading code CA is TA. The first spreading code CA changes at the first chip time SA (=TA/NA).

FIG. 3 is a diagram showing a sequence of second spreading codes CB generated by CB generator 1002.
The second spreading code CB is a pseudo-random number with a value of "+1" or "-1". The sequence length of the second spreading code CB is the second sequence length (NB chips). One period of the second spreading code CB is TB. The second spreading code CB changes at the second chip time SB (=TB/NB). Here, TB=SA and SB=SA/NB. That is, the second chip time SB is the value obtained by dividing the first chip time SA by the second sequence length NB. Since NB>2, SA>SB. One chip of the first spreading code CA corresponds to NB chips of the second spreading code CB.

FIG. 4 is a diagram showing a series of cascaded spreading codes PN generated by spreading code generator 3000.
The cascade-connected spreading code PN is a pseudo-random number whose value is "+1" or "-1". The sequence length of the cascade-connected spreading code PN is the third sequence length (NC chip). The third sequence length (NC chips) is the product of the first sequence length (NA chips) and the second sequence length (NB chips). That is, NC=NA*NB. One period of the cascade-connected spreading code PN is TP (=TA). The cascade spreading code PN changes at the second chip time SB. A series of cascade-connected spreading codes is also called a CAT (Concatenated) series.

FIG. 5 is a block diagram showing the configuration of the spread spectrum receiver 1 according to the first embodiment. The spread spectrum receiver 1 includes an analog receiver 2, an ADC (Analog-to-Digital Converter) 3, a quadrature detector 4, a timing corrector 5, an AGC (Auto Gain Control) 6, and a despreader. 7, a synchronization follow-up circuit 8, and a synchronization acquisition circuit 9.

The analog receiver 2 receives the intermediate frequency signal IF0 spread by the cascade-coupled spreading code PN transmitted from the spread spectrum transmitter, and outputs the intermediate frequency signal IF1.

The ADC 3 is connected in cascade after the analog receiver 2 and converts the analog intermediate frequency signal IF1 into a digital intermediate frequency signal IF2.

The quadrature detector 4 is connected in cascade after the ADC 3 and converts the intermediate frequency signal IF2 into a complex BB (hereinafter referred to as BB) signal (BBI1+jBBQ1).

The timing corrector 5 is connected in cascade after the quadrature detector 4, and uses the chip rate error (-ΔRc) detected by the synchronization tracking circuit 8 to correct the chip timing deviation of the complex BB signal (BBI1+jBBQ1). , outputs a complex BB signal (BBI2+jBBQ2).

The AGC 6 is cascade-connected to the timing corrector 5, controls the amplification factor so that the power of the complex BB signal (BBI2+jBBQ2) is at a constant level indicated by the reference value, and outputs the complex BB signal (BBI3+jBBQ3). .

The despreader 7 is cascade-connected to the AGC 6 and despreads the complex BB signal (BBI3+jBBQ3) to restore the signal before spectrum spreading by the cascade-connected spreading code PN in the spread spectrum transmitter. The despread complex BB signal (BBI4+jBBQ4) output from the despreader 7 is input to a demodulator (not shown). The demodulator demodulates the complex BB signal (BBI4+jBBQ4) according to the modulation method used in wireless communication. Further, the despreader 7 outputs the complex BB signal (BBI4P+jBBQ4P) and the complex BB signal (BBI4M+jBBQ4M) to the synchronous tracking circuit 8. The complex BB signal (BBI4P+jBBQ4P) is a signal obtained by despreading the complex BB signal (BBI4+jBBQ4) using a spreading code delayed by SB/2 from the spreading code used to despread the complex BB signal (BBI4+jBBQ4). The complex BB signal (BBI4M+jBBQ4M) is a signal obtained by despreading the complex BB signal (BBI4+jBBQ4) using a spreading code that is SB/2 faster than the spreading code used to despread the complex BB signal (BBI4+jBBQ4).

The synchronous follow-up circuit 8 estimates a chip rate error (-ΔRc) based on the signal output from the despreader 7 and outputs it to the timing corrector 5. The chip rate error (-ΔRc) is calculated by averaging the timing error (ΔTc) between the complex BB signal (BBI4+jBBQ4) and the cascade-connected spreading code PN, and calculates the chip rate (frequency) deviation (that is, the amount of phase change per double oversample). ) is the value converted to

The synchronization acquisition circuit 9 uses the output of the AGC 6 to perform synchronization acquisition processing of the modulated wave whose spectrum is spread by the cascade-connected spreading code PN. The synchronization acquisition circuit 9 obtains a spreading code phase correction value (-θ _PN ) for despreading at the start of communication with the spread spectrum transmitter.

FIG. 6 is a diagram showing the configuration of the analog receiver 2. As shown in FIG.
The analog receiver 2 includes a band pass filter (hereinafter referred to as BPF) 21, an amplification section (hereinafter referred to as AMP) 22, and a low pass filter (hereinafter referred to as LPF) 23.

The BPF 21 suppresses frequency components higher or lower than a frequency band determined from the intermediate frequency signal IF0, and removes noise and spurious.
AMP22 amplifies the level of the signal output from BPF21 to an appropriate value.
The LPF 23 suppresses frequency components higher than a determined frequency band, removes aliasing noise generated by the ADC 3, and outputs an intermediate frequency signal IF1.

FIG. 7 is a diagram showing the configuration of the quadrature detector 4. As shown in FIG.
The quadrature detector 4 detects the input intermediate frequency signal IF1 using two sine waves having a phase difference of 90 degrees that changes based on (-F-ΔF). (-ΔF) is a value obtained by inverting the sign of the frequency deviation estimated by a frequency deviation estimator (not shown). (-F) is a value obtained by inverting the sign of the carrier frequency of the predetermined intermediate frequency signal IF1.

The quadrature detector 4 includes an adder 49, a numerically controlled oscillator (hereinafter referred to as NCO) 46, a cos/-sin generator 45, a first multiplier 41, a second multiplier 42, and a low-pass filter. (hereinafter referred to as a first LPF) 43 and a low pass filter (hereinafter referred to as a second LPF) 44.

The adder 49 receives (-ΔF) and (-F) and outputs the sum thereof. The adder 49 outputs (-F-ΔF) to the NCO 46 every sampling period.
The NCO 46 integrates (-F-ΔF) output from the adder 49 every sampling period, and outputs the phase (ξ) of the carrier wave of the IF signal.

The cos/-sin generator 45 generates a complex local signal (cos ξ+jsin ξ) having a phase (ξ) that is output by the NCO 46.
The first multiplier 41 multiplies the intermediate frequency signal IF1 and cosξ. The second multiplier 42 multiplies the intermediate frequency signal IF1 by (-sinξ). The first LPF 43 removes harmonics from the output of the first multiplier 41 and outputs the BB signal BBI1. The second LPF 44 removes harmonics from the output of the second multiplier 42 and outputs the BB signal BBQ1.

FIG. 8 is a diagram showing the configuration of the timing corrector 5. As shown in FIG.
The timing corrector 5 converts the BB signals BBII and BBQ1 generated at the sampling frequency in the ADC 3 to an interval of 1/2 of the second chip time SB (=2 times the frequency corresponding to 1 chip of the second spreading code CB). BB signal BBI2 generated at twice the frequency). That is, the BB signals BBI2 and BBQ2 are twice oversampled signals. Further, the timing corrector 5 uses the value of the chip rate error (-ΔRc) detected by the synchronization follow-up circuit 8 to remove the timing error of the BB signals BBI2 and BBBQ2.

The timing corrector 5 includes a first FIR filter type resampler 51, a second FIR filter type resampler 52, a filter coefficient update section 53, an NCO 54, and an adder 55.

The adder 55, the NCO 54, and the filter coefficient update unit 53 determine the output timing of the sampling frequency of (2Rc-ΔRc). Rc is a frequency corresponding to one chip of the second spreading code CB. That is, Rc=1/SB.
Adder 55 adds 2Rc and (-ΔRc) and outputs the result to NCO 54.
The NCO 54 outputs Δθ _NCO , which is a value obtained by adding the numerical values output from the adder 55 at a predetermined period.

The first FIR filter type resampler 51 and the second FIR filter type resampler 52 interpolate and output values between adjacent sampling times by convolving and integrating a finite number of input value series and filter coefficients. do. Normally, as the filter coefficients of the first FIR filter type resampler 51 and the second FIR filter type resampler 52, a sinc function that is a time response of an ideal LPF can be used. Another filter coefficient may be used in consideration of conversion from a high number of oversamples to a low number of oversamples in the timing corrector 5, etc.

The filter coefficient updating unit 53 updates the filter coefficients of the first FIR filter resampler 51 and the second FIR filter resampler 52 to correct the difference based on the difference between the output timing and the input timing when Δθ _NCO becomes 2π. The calculated filter coefficients are set in the first FIR filter type resampler 51 and the second FIR filter type resampler 52. The filter coefficient updating unit 53 detects the output timing at which Δθ _NCO becomes 2π and the input timing closest to the output timing. The filter coefficient updating unit 53 calculates the deviation between the detected output timing and input timing. The filter coefficient updating unit 53 calculates filter coefficients to be set in the first FIR filter type resampler 51 and the second FIR filter type resampler 52 according to the calculated deviation. The filter coefficient updating unit 53 sets the calculated filter coefficients in the first FIR filter type resampler 51 and the second FIR filter type resampler 52. When the filter coefficients are set, the first FIR filter type resampler 51 and the second FIR filter type resampler 52 perform convolution integration using the filter coefficients and output BB signals BBI2 and BBQ2.

The first FIR filter type resampler 51 receives the BB signal BBI1 generated at the sampling frequency of the ADC 3 and outputs the BB signal BBI2 at the sampling frequency of (2Rc-ΔRc).
The second FIR filter type resampler 52 receives the BB signal BBQ1 generated at the sampling frequency of the ADC 3 and outputs the BB signal BBQ2 at the sampling frequency of (2Rc-ΔRc).

FIG. 9 is a diagram showing the configuration of the AGC 6.
The AGC 6 controls the amplification factor so that the power level of the BB signal input to the despreader 7 and the synchronization acquisition circuit 9 becomes a constant level indicated by a reference value. By keeping the level of the BB signal input to the despreader 7 and the synchronization acquisition circuit 9 constant, it becomes easy to detect the phase (chip) at which the correlation value calculated in the synchronization acquisition circuit 9 reaches its peak.

The AGC 6 includes a first multiplier 61a, a second multiplier 61b, a first square circuit 63a, a second square circuit 63b, an adder 64, and a first converter 65. It includes a subtracter 66, a third multiplier 67a, a fourth multiplier 67b, an LF (Loop Filter) section 68, and a second converter 69.

The first multiplier 61a multiplies the BB signal BBI2 by the output of the second converter 69 and outputs the BB signal BBI3. The second multiplier 61b multiplies the BB signal BBQ2 by the output of the second converter 69 and outputs the BB signal BBQ3.
The first square circuit 63a calculates the square of the BB signal BBI3. The second square circuit 63b calculates the square of the BB signal BBQ3. The adder 64 calculates the power P of the complex BB signal (BBI3+jBBQ3) by adding the square of the BB signal BBI3 and the square of the BB signal BBQ3.

The first converter 65 converts the power P into a dB value by calculating 10*log ₁₀ (P) for the power P.
The subtracter 66 subtracts the reference value REF from the dB value of the power P. The third multiplier 67a multiplies the output of the subtracter 66 by a minus sign for feedback control. The fourth multiplier 67b multiplies the output of the third multiplier 67a by the GAIN value. The LF section 68 averages the output of the fourth multiplier 67b in order to absorb variations due to noise.

The second converter 69 returns the dB value X to a voltage value by calculating 10 ^x/20 for the averaging processing result X, which is a dB value. By sending the output of the second converter 69 to the first multiplier 61a and the second multiplier 61b, feedback control is performed on the input BB signals BBI2 and BBQ2.

Note that the AGC 6 in FIG. 9 controls the power P to be at a constant level indicated by the reference value REF, but in order to reduce the bit length, the absolute value of the amplitude is controlled to be at a constant level indicated by the reference value REF. It may also be controlled to the level of the value.

FIG. 10 is a diagram showing the configuration of the despreader 7. As shown in FIG.
The despreader 7 multiplies the complex BB signal (BBI3+jBBQ3) by the cascade-connected spreading code PN synchronized with the cascade-connected spreading code PN, so that the complex BB signal (BBI4+jBBQ4) in the state before being multiplied by the cascade-connected spreading code PN is generated in the spread spectrum transmitter. ) is output. The cascade-connected spreading code PN is a code with a value of "+1" or "-1". Multiplying "+1" by "+1" becomes "+1", multiplying "-1" by "-1" becomes "+1", so multiply by the cascade-connected spreading code PN synchronized with the complex BB signal (BBI3+jBBQ3). By doing so, the diffusion component is eliminated. Using the phase correction value (-Δθ _PN ) of the cascaded spreading code PN estimated by the synchronization acquisition circuit 9, the phase of the cascaded spreading code PN and the phase of the complex BB signal (BBI3+jBBQ3) are matched. The cascade-connected spreading code PN changes in units of one chip (two samples).

The despreader 7 includes a spreading code generator 79, a first multiplier 71, a second multiplier 72, a third multiplier 73, a fourth multiplier 74, and a fifth multiplier. 75, a sixth multiplier 76, a first one-sample delay circuit 78, a second one-sample delay circuit 77, a first integration & decimation circuit 91, and a second integration & decimation circuit. 92, a third integration and decimation circuit 93, a fourth integration and decimation circuit 94, a fifth integration and decimation circuit 95, and a sixth integration and decimation circuit 96.

Spreading code generator 79 outputs a cascaded spreading code PN. The spreading code generator 79 outputs the cascade-connected spreading code PN at intervals of 1/2 of the second chip time SB (SB/2). However, the value of the cascade-connected spreading code PN output from the spreading code generator 79 changes in units of second chip time SB. After the synchronization acquisition is completed, the spreading code generator 79 shifts the phase of the cascaded spreading code PN by the spreading code phase correction value (-θ _PN ) output from the synchronization acquisition circuit 9. From then on, this shift amount is maintained. By shifting the phase of the cascade-connected spreading code PN by the spreading code phase correction value (-θ _PN ), the received signal (BBI3+jBBQ3) and the cascade-connected spreading code PN are synchronized, and the received signal (BBI3+jBBQ3) at discrete points in time is synchronized with the cascade-connected spreading code PN. ) can be despread.

The first one-sample delay circuit 78 delays the cascade-connected spreading code PN by one sample (SB/2). The second one-sample delay circuit 77 further delays the cascade-connected spreading code PN output from the first one-sample delay circuit 78 by one sample (SB/2).
The cascade-connected spreading code PN input to the third multiplier 73 and the fourth multiplier 74 is assumed to be PN(t). PN(t-SB/2) is input to the first multiplier 71 and the second multiplier 72. PN(t+SB/2) is input to the fifth multiplier 75 and the sixth multiplier 76.

A BB signal (BBI3) oversampled twice at the same time is input to the first multiplier 71, the third multiplier 73, and the fifth multiplier 75. The first multiplier 71, the third multiplier 73, and the fifth multiplier 75 each receive cascade-connected spreading codes PN whose timings differ by SB/2. The first multiplier 71, the third multiplier 73, and the fifth multiplier 75 despread the in-phase components of the complex BB signal (BBI3+jBBQ3) using cascade-connected spreading codes PN whose timings differ by SB/2. Output.

The second multiplier 72, the fourth multiplier 74, and the sixth multiplier 76 receive the BB signal (BBQ3) at the same time that has been oversampled twice. The second multiplier 72, the fourth multiplier 74, and the sixth multiplier 76 each receive cascade-connected spreading codes PN whose timings differ by SB/2. The second multiplier 72, the fourth multiplier 74, and the sixth multiplier 76 despread orthogonal components of the complex BB signal (BBI3+jBBQ3) using cascade-connected spreading codes PN whose timings differ by SB/2. Output the results.

The despreader 7 outputs the despreading result integrated over one symbol for each symbol. Therefore, the outputs of the first multiplier 71, the second multiplier 72, the third multiplier 73, the fourth multiplier 74, the fifth multiplier 75, and the sixth multiplier 76 are Integrating & decimating circuit 91, 2nd integrating & decimating circuit 92, 3rd integrating & decimating circuit 93, 4th integrating & decimating circuit 94, 5th integrating & decimating circuit 95, 6th integrating & decimating circuit 95, is input to the integration & thinning circuit 96.

Integrating & thinning circuits 91 to 96 integrate the despreading results output from multipliers 71 to 76 over one symbol period in chip clock units, and output the integrated value for one symbol period to the subsequent stage for each symbol. The first integration and thinning circuit 91 outputs the BB signal BBI4M, which is an integral value over one symbol period, to the synchronization tracking circuit 8. The second integration and thinning circuit 92 outputs the BB signal BBQ4M, which is an integral value over one symbol period, to the synchronous tracking circuit 8. The third integration and thinning circuit 93 outputs the BB signal BBI4, which is an integral value over one symbol period, to a demodulation section (not shown). The fourth integration and thinning circuit 94 outputs the BB signal BBQ4, which is an integral value over one symbol period, to a demodulation section (not shown). The fifth integration and thinning circuit 95 outputs the BB signal BBI4P, which is an integral value of one symbol period, to the synchronization follow-up circuit 8. The sixth integration and thinning circuit 96 outputs the BB signal BBQ4P, which is an integral value over one symbol period, to the synchronization follow-up circuit 8.

At the same time as outputting the integral value to the subsequent stage, a process of resetting the integral value to zero is performed. The output timing and reset timing are controlled by a control signal CT output by the spreading code generator 79. The reset timing is determined based on the timing at which the series of cascade-connected spreading codes PN returns to the beginning.

FIG. 11 is a diagram showing the configuration of the spreading code generator 79.
The spreading code generator 79 includes a CA generator 2001, a CB generator 2002, a multiplier 2003, and a phase correction section 2004.

CA generator 2001 generates a first spreading code CA which is a pseudo-random number. CB generator 2002 generates a second spreading code CB which is a pseudo-random number. Multiplier 2003 generates a cascade-connected spreading code PN, which is a pseudo-random number, by multiplying the first spreading code CA and the second spreading code CB. The phase correction unit 2004 shifts the phase of the cascade-connected spreading code PN by a phase correction value (-θ _PN ).

The first spreading code CA generated by CA generator 2001 is the same as the first spreading code CA generated by CA generator 1001. The second spreading code CB generated by CB generator 2002 is the same as the second spreading code CB generated by CB generator 1002. The cascaded spreading code PN generated by the spreading code generator 79 is the same as the cascaded spreading code PN generated by the spreading code generator 3000. Note that the phase of the cascade-connected spreading code PN generated by the spreading code generator 79 can be changed.

FIG. 12 is a diagram showing the configuration of the synchronous follow-up circuit 8. As shown in FIG.
The synchronous follow-up circuit 8 is generally called a DLL (Delay Locked Loop). The synchronous follow-up circuit 8 includes a first square circuit 81, a second square circuit 82, a first adder 85, a third square circuit 83, a fourth square circuit 84, It includes a second adder 86, a subtracter 87, a first multiplier 88a, a second multiplier 88b, and an LF section 89.

The first square circuit 81 calculates the square of the BB signal BBI4M. The second square circuit 82 calculates the square of the BB signal BBQ4M. The first adder 85 adds the square of the BB signal BBI4M and the square of the BB signal BBQ4M, thereby generating a complex BB signal (shifted by SB/2) that is 1/2 the second chip time earlier (shifted by SB/2). The power P1 of BBI4M+jBBQ4M) is calculated.

The third square circuit 83 calculates the square of the BB signal BBI4P. The fourth square circuit 84 calculates the square of the BB signal BBQ4P. The second adder 86 adds the square of the BB signal BBI4P and the square of the BB signal BBQ4P to generate a complex BB signal delayed by 1/2 of the second chip time (shifted by -SB/2). Calculate the power P2 of (BBI4P+jBBQ4P).
Subtractor 87 subtracts power P1 from power P2 and outputs a power difference ΔR ² .

FIG. 13 is a diagram showing the relationship between timing error ΔTc and power difference ΔR ² .
When the timing error ΔTc of the cascaded spreading code PN is in the range of -0.5 chips to 0.5 chips, the power difference ΔR ² has a property that the value increases as the timing error ΔTc of the cascaded spreading code PN increases. This property is generally called an S curve. When the timing error ΔTc=0, the power R ² after despreading becomes maximum. Power P1 and power P2 are powers that are reduced by the same amount from the maximum value of power ^R2 . Therefore, when ΔTc=0, the power difference ΔR ² =0. When ΔTc≠0, the power R ² after despreading decreases as the absolute value of the timing error ΔTc increases. In the case of ΔTc=-0.5 chips, the power P2 of the complex BB signal (BBI4P+jBBQ4P) delayed by 1/2 of the second chip time (shifted by -SB/2) is the power ^R2 in the case of ΔTc=0 Take the maximum value of . The power P1 becomes the reduced power ^R2 when ΔTc=1 chip. As a result, the power difference ΔR ² is positive and maximum. As ΔTc increases from ΔTc=-0.5 chip, power P2 decreases and power P1 increases. Therefore, as ΔTc increases from ΔTc=−0.5 chip, the power difference ΔR ² decreases. When ΔTc=0.5 chips, the power difference ΔR ² is negative and minimum.

The first multiplier 88a multiplies the power difference ΔR ² by a negative value for feedback control. The second multiplier 88b multiplies the output value of the first multiplier 88a by the GAIN value. The LF section 89 outputs a chip rate error (-ΔRc) by averaging the output of the second multiplier 88b in order to absorb variations due to noise. The chip rate error (-ΔRc) obtained by the averaging process is sent to the timing corrector 5, and feedback control is performed so that the power difference ΔR ² becomes zero.

(Reference example)
FIG. 14 is a diagram showing the configuration of a synchronization acquisition circuit 9F as a reference example.
The synchronization acquisition circuit 9F includes a CB correlation processing section 901F, a CA correlation processing section 910F, a power calculation section 920, a power storage section 930, and a peak detection section 940.

The CB correlation processing unit 901F receives the complex BB signal (BBI3+jBBQ3) output from the AGC 6 and oversampled twice every SB/2 time. The CB correlation processing unit 901F holds the second spreading code CB for one period [1:NB] output by the CB generator 2002 shown in FIG. 11.

The CB correlation processing unit 901F calculates the complex BB signal (BBI3+jBBQ3) of NB chips (=2NB samples) and the NB chips (=NB samples) every time a new complex BB signal (BBI3+jBBQ3) is input every SB/2 time. ) with the second spreading code CB. The kth BB signal is multiplied by the [(k+1)/2]th second spreading code CB. [X] is a Gaussian symbol and returns an integer not exceeding the real number X. The CB correlation processing section 901F outputs the calculated sum of products as a second correlation value B to the CA correlation processing section 910F every SB/2 time. Note that the second correlation value B is a complex number.

The CB correlation processing section 901F includes a delay processing section 121 and a second correlation value calculation section 222. The delay processing unit 121 includes 2NB D-type flip-flops 902(1) to 902(2NB). The second correlation value calculation unit 222 includes multipliers 803(1) to 803 (2NB) and an adder 904. The second correlation value calculation unit 222 calculates a second correlation value, which is the sum of the products of each complex BB signal of NB consecutive chips and each second spreading code CB.

The D-type flip-flop 902(i) outputs the held complex BB signal (BBI3+jBBQ3) to the D-type flip-flop 902(i-1) in the previous stage every SB/2 time, and The complex BB signal (BBI3+jBBQ3) sent from step 902(i+1) is held.

The multiplier 803(i) converts the complex BB signal (BBI3[i]+jBBQ3[i]) held in the D-type flip-flop 902(i) and the second spreading code according to equation (2) shown below. Multiply by CB[m]. m=[(k+1)/2].
(BBI3[i]+jBBQ3[i])*CB[m]...(2)
Adder 904 adds the outputs of 2NB multipliers 803(1) to 803(2NB) and outputs a second correlation value B that is the addition result. Note that the multiplier 803(i) includes a multiplier for BBI3 and a multiplier for BBQ3. The adder 904 also includes an adder for BBI3 and an adder for BBQ3.

A new second correlation value B is input to the CA correlation processing unit 910F every SB/2 time. The CA correlation processing unit 910F holds the first spreading code CA[1:NA] output from the CA generator 2001 in FIG. 11. The CA correlation processing unit 910F calculates the product sum (first correlation value) of the second correlation value B at an interval of NA NB chips (=2NB samples) and the NA first spreading code Calculate the value A). The second correlation value B is based on 2NB complex BB signals (BBI3[i]+jBBQ3[i], i=1 to 2NB) and the second spreading code CB[m], m=[(k+1)/2] , i=1 to 2NB). Therefore, the first correlation value A is the sum of the products of NB*NA complex BB signals (BBI3[i]+jBBQ3[i], i=1 to 2NB*NA) and the cascade-connected spreading code PN.

The CA correlation processing section 910F includes a delay processing section 223 and a first correlation value calculation section 224. The delay processing unit 223 includes NA delay processing units 820(1) to 820(NA). The delay processing unit 820(i) includes 2NB D-type flip-flops 811(i,1) to 811(i,2NB). However, i=1 to NA. The first correlation value calculation unit 224 includes NA multipliers 812(1) to 812(NA) and an adder 913. The first correlation value calculation unit calculates a first correlation value that is the sum of the products of NA second correlation values B and each first spreading code CA calculated by the second correlation value calculation unit 122 at every 2NB. Calculate A.

The D-type flip-flop 811 (i, j) outputs the held second correlation value B expressed as a complex number to the subsequent D-type flip-flop 811 (i, j-1) every SB/2 time. At the same time, the second correlation value B sent from the D-type flip-flop 811 (i, j+1) at the previous stage is held. The D-type flip-flop (i, 1) (i=2 to NA) at the last stage outputs the second correlation value B to the delay processing section 820 (i-1) at the next stage. The D-type flip-flop (i, 1) (i=1 to NA) at the last stage outputs the second correlation value B to the multiplier 812(i).

Multiplier 812(i) multiplies the second correlation value B output from delay processing unit 820(i) by first spreading code CA[i].
Adder 913 adds the outputs of NA multipliers 812(1) to 812(NA) and outputs a first correlation value A as the addition result. Note that the multiplier 812(i) includes a multiplier for the real part of the second correlation value B and a multiplier for the imaginary part of the second correlation value B. The adder 904 also includes an adder for the real part of the second correlation value B and an adder for the imaginary part of the second correlation value B.

The power calculation unit 920 calculates the sum of squares of the real part and the imaginary part of the first correlation value A, and outputs the power C of the first correlation value A.

The power storage unit 930 stores the power C of the NA*NB chips (=NA*2NB samples=2NC samples) at SB/2 intervals calculated by the power calculation unit 920. The power storage unit 930 stores power C of NC first correlation values A calculated by shifting the received signal by one time point (one sample).

The peak detection unit 940 detects the maximum value of the power C of the NA*NB chips (=NA*2NB samples) at SB/2 intervals stored in the power storage unit 930. The peak detection unit 940 determines the synchronization sequence position based on the detected position where the maximum value is obtained. The peak detection unit 940 determines a spreading code phase correction value (-θ _PN ) based on the synchronization sequence position and notifies the despreader 7 of the value. For example, if the 0th sample is the peak, θ _PN =0. The synchronization sequence position is the position in the cascade code sequence length of the cascade spread code PN to be multiplied by the received signal at a discrete point in time. The synchronization acquisition circuit 9 determines the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position.

After the communication starts, the synchronization acquisition circuit 9 does not notify the despreader 7 of the spreading code phase correction value (-θ _PN ). After the communication is interrupted, the synchronization acquisition circuit 9 operates again to obtain the spreading code phase correction value (-θ _PN ), and sends the obtained spreading code phase correction value (-θ _PN ) to the despreader 7. Notice.

FIG. 15 is a diagram showing a series of second correlation values B.
The second correlation value B has a peak every period TB of the second spreading code CB, that is, every NB chip (2NB samples). 2NB is the number of intervals that is the number of received signals included in the chips of the second sequence length NB.

FIG. 16 is a diagram showing a series of first correlation values A.
The first correlation value A has a peak every period TP of the cascade-connected spreading code PN, that is, every NA*NB chip (2NA*NB samples).

FIG. 17 is a diagram showing a BB signal BBI3, a cascade-connected spreading code PN synchronized with the BB signal BBI3, and a despread BB signal BBI4 when the transmission data is "1". . FIG. 18 is a diagram showing a BB signal BBI3, a cascade-connected spreading code PN synchronized with the BB signal BBI3, and a despread BB signal BBI4 when the transmission data is "-1". be.
BBI3 changes every SB/2 hours. BBI3 actually takes a value that deviates from "+1" and "-1". This is because the received IF signal IF0 undergoes processing such as filter processing and phase rotation to generate BBI3. Here, for convenience of explanation, the value of BBI3 is assumed to be "+1" or "-1".

As shown in FIGS. 17 and 18, BBI4 becomes a constant value in one symbol (one period TP) by synchronizing BBI3 and cascade-connected spreading code PN. One period TP corresponds to NB*NA chips (2*NB*NA samples). Here, synchronization between BBI3 and cascade-connected spreading code PN means that BBI3 is synchronized with both first spreading code CA and second spreading code CB.

The synchronization acquisition circuit 9F of the reference example has the following problems.
The first problem is that in the CB correlation processing section 901F, the second correlation value calculation section 222 is composed of 2NB multipliers 803(1) to 803(2NB).
The second problem is that in the CA correlation processing section 910F, the first correlation value calculation section 224 is composed of NA multipliers 812(1) to 812(NA).
The third problem is that in the CA correlation processing section 910F, the delay processing section 121 is composed of 2NB D-type flip-flops 811(i,1) to 811(i,2NB).

Using an IC called FPGA (Field Programmable Gate Array) allows for free logic and functional design within a pre-given scale, so FPGAs are widely used to realize functions using H/W. ing.
The FPGA is composed of logic elements (hereinafter referred to as LEs), memory blocks, multipliers, I/O elements, and the like. There are restrictions on the multipliers and LEs that can be used in FPGAs. Therefore, when the CB correlation processing section 901F and the CA correlation processing section 910F are configured by FPGA, the following problems occur.

There are cases where the number of multipliers for chip correlation processing is greater than the number of multipliers that can be used in the FPGA (first and second problems).
Further, the D-type flip-flop can be configured using LEs of FPGA. There are cases where the number of D-type flip-flops is greater than the number of usable LEs in the FPGA (third problem).

The synchronization acquisition circuit 9 of this embodiment can solve the first to third problems.
FIG. 19 is a diagram showing the configuration of the synchronization acquisition circuit 9 of the first embodiment.
The synchronization acquisition circuit 9 of the first embodiment differs from the synchronization acquisition circuit 9F of the reference example in the following points.

The CB correlation processing section 901 includes a second correlation value calculation section 122 instead of the second correlation value calculation section 222. The second correlation value calculation unit 122 includes chip correlation units 903(1) to 903(2NB) instead of multipliers 803(1) to 803(2NB).

The CA correlation processing section 910 includes a first correlation value calculation section 124 instead of the first correlation value calculation section 224. The first correlation value calculation unit 124 includes chip correlation units 912(1) to 912(NA) instead of multipliers 812(1) to 812(NA).

The CA correlation processing section 910 includes a memory 123 instead of the delay processing section 223. The memory 123 corresponds to a second correlation value storage section. The memory 123 includes NA DPRAMs (Dual Port RAM) 911(1) to 911(NA).

FIG. 20 is a diagram showing the configuration of chip correlation section 903(i) in the first embodiment.
The chip correlation unit 903(i) includes a two's complement arithmetic unit 951 and a selector (SEL) 952. Note that the two's complement arithmetic unit 951 includes a BBI3 arithmetic unit and a BBQ3 arithmetic unit.

The two's complement calculator 951 outputs the two's complement value of the complex BB signal (BBI3+jBBQ3).
When the value of the second spreading code CB[i] is "+1", the selector 952 outputs the normal rotation value of the complex BB signal (BBI3+jBBQ3), that is, outputs the complex BB signal (BBI3+jBBQ3) as it is.
When the value of the second spreading code CB[i] is "-1", the selector 952 outputs the two's complement value of the complex BB signal (BBI3+jBBQ3) output from the two's complement calculator 951. .

The two's complement arithmetic unit 951 and the selector 952 can be implemented by LEs of FPGA. This makes it possible to avoid using a multiplier to implement the second correlation value calculation unit 122.

FIG. 21 is a diagram showing the configuration of chip correlation section 912(i) in the first embodiment.
The chip correlation unit 912(i) includes a two's complement arithmetic unit 961 and a selector (SEL) 962. Note that the two's complement arithmetic unit 961 includes an arithmetic unit for the real part of the second correlation value B and an arithmetic unit for the imaginary part of the second correlation value B.

The two's complement calculator 961 outputs a two's complement value of the second correlation value B.
When the value of the first spreading code CA[i] is "+1", the selector 962 outputs the normal rotation value of the second correlation value B, that is, outputs the second correlation value B as is.
When the value of the first spreading code CA[i] is "-1", the selector 962 outputs the two's complement value of the second correlation value B output from the two's complement calculator 951.

The two's complement arithmetic unit 961 and the selector 962 can be implemented by LEs of FPGA. This makes it possible to avoid using a multiplier to implement the first correlation value calculation unit 124.

Referring again to FIG. 19, NA DPRAMs 911(1) to 911(NA) are connected in series. The DPRAM 911(i) (i=1 to NA) has (2NB+1) addresses of 0 to 2NB and stores (2NB+1) second correlation values B.
The second correlation value B output from the CB correlation processing section 901 is written into the first DPRAM 911 (NA). The second correlation value B read from the DPRAM 911(i) (i=2 to NA) is written to the subsequent DPRAM 911(i-1). The second correlation value B read from the DPRAM 911(i) (i=1 to NA) is sent to the chip correlation unit 912(i). The fact that the second correlation value B read from the DPRAM is written to a predetermined other DPRAM in this manner is called that the DPRAM is ordered. The second correlation value B, which is not stored in the memory 123, is written to the first DPRAM among the ordered DPRAMs. The second correlation value B read from the DPRAM not last in the order is written to the DPRAM in the next order. Multiple DPRAMs that are ordered are also referred to as cascaded.

The value read from the DPRAM 911(i) is the second correlation value B written second oldest in the DPRAM 911(i). The position written into the DPRAM 911(i) is the oldest position in the DPRAM 911(i) where the second correlation value B was written.

FIG. 22 is a diagram for explaining the operation of DPRAM 911(i) according to the first embodiment.
DPRAM 911(i) has a circular write pointer WP and a circular read pointer RP for specifying a write position and a read position. The second correlation value B is written to the address specified by the circular write pointer WP. The second correlation value B is read from the address specified by the circular read pointer RP. The circular write pointer WP and the circular read pointer RP are controlled by the address control section 954.

The address specified by the circular write pointer WP increases by one data every time the second correlation value B is written to the DPRAM 911(i). When the address specified by the circular write pointer WP is "2NB", the next address specified by the circular write pointer WP is "0".The address specified by the circular read pointer RP is the second address from the DPRAM 911(i). Each time the correlation value B is read, it increases by one data. When the address specified by the circular read pointer RP is "2NB", the next address specified by the circular read pointer RP becomes "0". The address specified by the circular read pointer RP is one larger than the address specified by the circular write pointer WP.

As shown in FIG. 22, when the circular write pointer WP specifies the address "2NB", the circular read pointer RP specifies the address "0". At this time, the second correlation value B is written to the address "2NB", and the second correlation value B is read from the address "0".
When the circular write pointer WP specifies address "0", the circular read pointer RP specifies address "1". At this time, the second correlation value B is written to the address "0", and the second correlation value B is read from the address "1".
When the circular write pointer WP specifies the address "2NB-1", the circular read pointer RP specifies the address "2NB". At this time, the second correlation value B is written to the address "2NB-1", and the second correlation value B is read from the address "2NB".

Referring again to FIG. 19, the second correlation value B read from DPRAM(i) is input to chip correlation unit 912(i) (i=1 to NA). The chip correlation unit 912(i) outputs the product of the input second correlation value B and the first spreading code CA[i].
Adder 913 adds the outputs of NA chip correlation units 912(1) to 912(NA) and outputs a first correlation value A.

DPRAM 911(1) to 911(NA) can be implemented by memory blocks instead of LEs of FPGA. The CA correlation processing unit 910 includes a DPRAM 911(i) instead of the D-type flip-flops 811(i,1) to 811(i,2NB), so that the LE of the FPGA can be used to implement the D-type flip-flops. You can avoid using it.

(comparison)
Next, we will compare the numbers of multipliers and LEs in the correlation processing of the conventional M-sequence spreading code, the correlation processing of the cascaded spreading code PN of the reference example, and the correlation processing of the cascaded spreading code PN of this embodiment. do.

FIG. 23 is a diagram showing a circuit that performs a conventional correlation process of M-sequence spreading codes.
(multiplier)
The number of multipliers required for conventional M-sequence spreading code correlation processing is (NA*NB) chips*2ch*2OS. (NA*NB) is the number of chips for one period of the M sequence. 2ch means two channels, an I channel and a Q channel. 2OS means 2x author bumpling.

The number of multipliers required for the correlation processing (reference example) of the cascade-connected spreading code PN is as follows. In the CB correlation processing section, multipliers for (NB chips*2 channels*2 OS) are required. In the CA correlation processing section, multipliers for (NA chips*2 channels*2 OS) are required. Therefore, the number of multipliers required for correlation processing of the cascade-connected spreading code PN is ((NA+NB) chips*2ch*2OS).

Here, in the case of NB=511 and NA=31, the number of multipliers is as follows.
The number of multipliers required for correlation processing of M-sequence spreading codes is 15,841 chips*2 channels*2 OS. The number of multipliers required for correlation processing of the cascade-connected spreading code PN is 542 chips*2ch*2OS. The number of multipliers required for the correlation processing of the cascade-connected spreading code PN of the reference example can be smaller than the number of multipliers required for the correlation processing of the M-sequence spreading code.

However, as described above, there is a restriction on the number of multipliers in an FPGA, so it is desirable to use as few multipliers as possible. In this embodiment, chip correlation processing of the second spreading code CB is performed by a two's complement arithmetic unit 951 and a selector 952 that can be implemented in an LE. Further, in this embodiment, chip correlation processing of the first spreading code CA is executed by a two's complement arithmetic unit 961 and a selector 962 that can be implemented in an LE. Thereby, correlation processing of the spreading code of the cascade-connected spreading code PN can be realized without using a multiplier in the FPGA. The number of multipliers used in the synchronization acquisition circuit 9 can be reduced. As a result, there is some leeway with respect to the restriction on the number of multipliers within the FPGA.

For example, if you use INTEL's 5CEA4 as an FPGA, you can use 132 18-bit * 18-bit multipliers, 49K LEs, and 3,080K-bit memory block (Intel's FPGA products (See page 29 of the Catalog, Version 18.1).

The number of multipliers required for the correlation processing of the cascade-connected spreading code PN in the reference example is 542 chips*2ch*2OS, so if 5CEA4 is used as the FPGA, there will be a shortage of multipliers. Therefore, in the reference example, correlation processing of the cascade-connected spreading code PN cannot be implemented using 5CEA4.

In this embodiment, the Ich signal and Qch signal each have 6 bits, the two's complement arithmetic units 951 and 961 are each implemented with one LE, and the selectors 952 and 962 are each implemented with one LE. can be done. In this case, the number of LEs required for correlation processing of the cascade-connected spreading code PN is 6 bits*542*2ch*2OS+6 bits*542*2ch*2OS (=26.016K). This is smaller than the number of LEs (49K) in 5CEA4. Therefore, even when 5CEA4 is used as the FPGA, correlation processing of the cascade-connected spreading code PN can be implemented in this embodiment.

(LE)
The number of D-type flip-flops (hereinafter referred to as DFF) required for conventional M-sequence spreading code correlation processing is (NA*NB)*2ch*2OS.
The number of DFFs required for correlation processing (reference example) of the cascade-connected spreading code PN is as follows. In the CB correlation processing section, DFFs for (NB chips*2 channels*2 OS) are required. In the CA correlation processing section, DFFs for ((NB*NA)chips*2ch*2OS) are required. Therefore, the number of DFFs required for correlation processing of the cascade-connected spreading code PN is ((NB*NA+NB) chips*2ch*2OS).

Here, in the case of NB=511 and NA=31, the number of DFFs is as follows.
The number of DFFs required for correlation processing of M-sequence spreading codes is 15,841 chips*2 channels*2 OS. The number of DFFs required for the correlation processing of the cascade-connected spreading code PN of the reference example is 16,352 chips*2 channels*2 OS. The number of DFFs required for correlation processing of the cascade-connected spreading code PN of the reference example is increased by 511 chips*2ch*2OS than the number of DFFs required for correlation processing of the M-sequence spreading code.

In this embodiment, NA delay processing units in the CA correlation processing unit 910 are configured by DPRAM 911(i) that can be implemented as a memory block. As a result, in this embodiment, the DFFs for ((NB*NA) chips*2ch*2OS) in the CA correlation processing section are replaced with DPRAMs, so the number of DFFs required for correlation processing of the cascade-connected spreading code PN is reduced. , only (511 chips*2 channels*2 OS) of the CB correlation processing section. As a result, there is some leeway with respect to the restriction on the number of LEs within the FPGA.

For example, if INTEL's 5CEA4 is used as the FPGA, 132 18-bit*18-bit multipliers and 49K LEs can be used.

It is assumed that the Ich signal and the Qch signal each have 6 bits. The number of DFFs required for correlation processing of the cascade-connected spreading code PN in the reference example is 6 bits*16352 chips*2 channels*2 OS (=392.448K). Assuming that the DFF is implemented using one LE, the synchronization acquisition circuit 9F of the reference example cannot be implemented using 49K 5CEA4.

In this embodiment, the number of DFFs required for correlation processing of the cascade-connected spreading code PN is 6 bits*511 chips*2 channels*2 OS (=12.264K). Additionally, 32 6-bit*511*2ch*2OS (=12.264K bits) DPRAMs are required. In conversion, a memory area of 380.184K bits is required. This is smaller than the capacity of the 5CEA4 memory block (3,080K bits). Therefore, even when 5CEA4 is used as the FPGA, correlation processing of the cascade-connected spreading code PN can be implemented in this embodiment.

As described above, in the first embodiment, by using a DPRAM instead of a DFF and using a two's complement arithmetic unit and a selector instead of a multiplier, the circuit scale can be reduced more than in the reference example. . Furthermore, when a DFF is used, an operation is required for each chip, which increases power consumption. On the other hand, when a DPRAM is used, the storage address of the memory is operated only once in one cycle, so power consumption is further reduced. In the first embodiment, a comparatively small FPGA has been described as an example, but the capacity may be selected depending on the intended use. In the first embodiment, an example in which a DPRAM is used as the delay processing circuit has been described, but a FIFO (First In First Out) or a single port RAM that outputs data one cycle before may be used. In this first embodiment, the number of DPRAMs is (NA+1), but it may be (NA-1) or more.

The first correlation value calculation unit calculates the NA number of second correlation values B read out from the DPRAMs in consecutive order among the second correlation values B read out one by one from the DPRAMs in consecutive order in number of NA or more from the beginning. Any method that calculates the first correlation value A using the second correlation value B may be used. It may be a single-port RAM instead of a DPRAM.

Furthermore, in this embodiment, by oversampling the received signal, tracking processing can be appropriately performed, and the despreading timing can be detected even when the sampling timing is set close to the chip separation. and can be corrected. As a result, the received signal can be properly despread and decoded.

Modification 1 of Embodiment 1.
This modification is a modification of the spread spectrum receiver of Embodiment 1 so as not to perform oversampling. The spread spectrum receiver 1A of this modification can operate appropriately when the absolute value |ΔTc| of the timing error amount of the spreading code is significantly different from SB/2.

FIG. 24 is a block diagram showing the configuration of a spread spectrum receiver 1A according to a first modification of the first embodiment. The spread spectrum receiver 1A of this modification differs from the spread spectrum receiver 1 of the first embodiment in the following points.
The spread spectrum receiver 1A includes a timing corrector 5A, a despreader 7A, and a synchronization acquisition circuit 9A in place of the timing corrector 5, despreader 7, and synchronization acquisition circuit 9 of the first embodiment. The spread spectrum receiver 1A does not include the synchronous tracking circuit 8 of the first embodiment.

FIG. 25 is a diagram showing the configuration of the timing corrector 5A.
The timing corrector 5A is different from the timing corrector 5 of the first embodiment in that Rc is input to the NCO 54 instead of (2Rc-ΔRc). The timing corrector 5A does not oversample BBI1 and BBQ1 twice.

FIG. 26 is a diagram showing the configuration of the despreader 7A.
The despreader 7A is different from the despreader 7 of the first embodiment in that a first multiplier 71, a second multiplier 72, a fifth multiplier 75, a sixth multiplier 76, and a 1 1-sample delay circuit 78, 2nd 1-sample delay circuit 77, 1st integration & decimation circuit 91, 2nd integration & decimation circuit 92, 5th integration & decimation circuit 95, 6th 1-sample delay circuit 78, The point is that the integration and thinning circuit 96 is not provided. This is because the despreader 7A only needs to output the complex BB signal (BBI4+jBBQ4) since oversampling is not performed.

FIG. 27 is a diagram showing the configuration of the synchronization acquisition circuit 9A.
This synchronization acquisition circuit 9A differs from the synchronization acquisition circuit 9 of the first embodiment in the following points.
The synchronization acquisition circuit 9A includes a CB correlation processing section 901A and a CA correlation processing section 910A in place of the CB correlation processing section 901 and the CA correlation processing section 910 of the first embodiment.

The CB correlation processing unit 901A receives the non-oversampled complex BB signal (BBI3+jBBQ3) output from the AGC 6 for each SB time. The CB correlation processing unit 901A holds the second spreading code CB[1:NB] output from the CB generator 3002. The CB correlation processing unit 901A converts the complex BB signal (BBI3+jBBQ3) of NB chips (=NB samples) and the second spreading code of NB chips (=NB samples) every time a new complex BB signal (BBI3+jBBQ3) is input. The sum of products with CB is calculated and output as a second correlation value B to the CA correlation processing section 910A. NB is the number of intervals that is the number of received signals included in the chip of the second sequence length NB in the first modification of the first embodiment.

The CB correlation processing section 901A includes a delay processing section 121A and a second correlation value calculation section 122A. The delay processing unit 121A includes NB D-type flip-flops 902(1) to 902(NB). The second correlation value calculation unit 122A includes chip correlation units 903(1) to 903(NB) and an adder 904.

The D-type flip-flop 902(i) outputs the held complex BB signal (BBI3+jBBQ3) to the D-type flip-flop 902(i-1) in the subsequent stage, and outputs the complex BB signal (BBI3+jBBQ3) to the D-type flip-flop 902 in the previous stage at each SB time. Holds the complex BB signal (BBI3+jBBQ3) sent from (i+1).

Chip correlation unit 903(i) includes a two's complement arithmetic unit 951 and a selector 952, as in the first embodiment.

Adder 904 adds the outputs of NB chip correlation units 903(1) to 903(NB) and outputs a second correlation value B as the addition result.

A new second correlation value B is input to the CA correlation processing unit 910A every SB time. The CA correlation processing unit 910A calculates the product sum (first correlation value A) of the second correlation value B at an interval of NA NB chips (=NB samples) and the NA first spreading codes ).

The CA correlation processing section 910A includes a memory 123A and a first correlation value calculation section 124 similar to the first embodiment. The memory 123A includes NA DPRAMs 911A(1) to 911A(NA).
The DPRAM 911A(i) (i=1 to NA) has (NB+1) addresses from 0 to NB, and stores (NB+1) second correlation values B.

NA DPRAMs 911A(1) to 911A(NA) are connected in series. The second correlation value B output from the CB correlation processing section 901A is written into the first DPRAM 911A (NA). The second correlation value B read from the DPRAM 911A(i) (i=2 to NA) is written to the subsequent DPRAM 911A(i-1). The second correlation value B read from the DPRAM 911A(i) (i=1 to NA) is sent to the chip correlation unit 912(i).

The value read from DPRAM 911A(i) is the second correlation value B written second oldest in DPRAM 911A(i). The position written in the DPRAM 911A(i) is the oldest position in the DPRAM 911A(i) where the second correlation value B was written.

FIG. 28 is a diagram for explaining the operation of DPRAM 911A(i) of Modification 1 of Embodiment 1.
DPRAM 911A(i) has a circular write pointer WP and a circular read pointer RP for specifying a write position and a read position. The second correlation value B is written to the address specified by the circular write pointer WP. The second correlation value B is read from the address specified by the circular read pointer RP.

The address designated by the circular write pointer WP increases by one data every time the second correlation value B is written to the DPRAM 911A(i). When the address specified by the circular write pointer WP is "NB", the next address specified by the circular write pointer WP is "0".The address specified by the circular read pointer RP is the second address from the DPRAM911A(i). Each time the correlation value B is read, it increases by one data.When the address specified by the circular read pointer RP is "NB", the next address specified by the circular read pointer RP becomes "0".The circular read pointer RP The address specified by is larger by 1 than the address specified by the circular write pointer WP.

As shown in FIG. 28, when the circular write pointer WP specifies the address "NB", the circular read pointer RP specifies the address "0". At this time, the second correlation value B is written to the address "NB", and the second correlation value B is read from the address "0".
When the circular write pointer WP specifies address "0", the circular read pointer RP specifies address "1". At this time, the second correlation value B is written to the address "0", and the second correlation value B is read from the address "1".
When the circular write pointer WP specifies the address "NB-1", the circular read pointer RP specifies the address "NB". At this time, the second correlation value B is written to the address "NB-1", and the second correlation value B is read from the address "NB".

Modification 2 of Embodiment 1.
In this modification, Embodiment 1 is modified in the following two points.
(1) The number of DPRAMs is reduced by one, and the second correlation value B before being stored in the memory 123P is used for calculating the first correlation value A.
(2) The CB correlation processing unit 901P uses one received signal for one chip to calculate the second correlation value B.

FIG. 29 is a diagram showing the configuration of the synchronization acquisition circuit 9P of the second modification of the first embodiment. In the synchronization acquisition circuit 9P, the CB correlation processing section 901P and the CA correlation processing section 910P are changed. The CB correlation processing unit 901P calculates the second correlation value B by summing the products of a total of NB received signals and spreading codes CB, one per chip. The CB correlation processing section 901P includes a delay processing section 121P and a second correlation value calculation section 122P. The delay processing unit 121P has (2NB-1) D-type flip-flops 902(1) to (2NB-1) connected in series. A complex BB signal (BBI3+jBBQ3) is input to the D-type flip-flop 902 (2NB-1).

The second correlation value calculation unit 122P includes NB chip correlation units 903(1), (3) to (2NB-1). Chip correlation section 903 (2NB-1) outputs the product of the output of D-type flip-flop 902 (2NB-1) and spreading code CB[NB]. The output of the D-type flip-flop 902 (2NB-2) is not input to the chip correlation section 903. Chip correlation section 903 (2i-1) takes the product of the output of D-type flip-flop 902 (2i-1) and spreading code CB[i]. The output of the D-type flip-flop 902 (2i-2) is not input to the chip correlation section 903. The complex BB signal (BBI3+jBBQ3) output from the odd-numbered D-type flip-flop 902 (2i-1) is multiplied by the spreading code CB[i] in the chip correlation unit 903 (2i-1). Adder 904 adds the outputs of NB chip correlation units 903(1), (3) to (2NB-1).

The CA correlation processing unit 910P includes a memory 123P having (NA-1) DPRAMs 911(1) to 911(NA-1). The product of the second correlation value B read from the DPRAM 911(1) and the spreading code CA[1] is calculated by the chip correlation unit 912(1). The product of the second correlation value B read from the DPRAM 911(i) and the spreading code CA[i] is calculated by the chip correlation unit 912(i). The chip correlation unit 912 (NA-1) calculates the product of the second correlation value B read from the DPRAM 911 (NA-1) and the spreading code CA[NA-1]. A second correlation value B calculated by the CB correlation processing unit 901P and not yet stored in the memory 123P is input to the chip correlation unit 912 (NA). The chip correlation unit 912 (NA) outputs the product of the second correlation value B calculated by the CB correlation processing unit 901P and not yet stored in the memory 123P and the spreading code CA[NA].

The second correlation value B calculated by the CB correlation processing unit 901P and not yet stored in the memory 123P is written to the DPRAM 911 (NA-1). The second correlation value B read from DPRAM 911 (NA-1) is written to DPRAM 911 (NA-2). The second correlation value B read from DPRAM 911(i) is written to DPRAM 911(i-1). The second correlation value B read from DPRAM 911(2) is written to DPRAM 911(1). Writing and reading of the second correlation value B to and from the DPRAMs 911(1) to 911(NA-1) can be performed simultaneously.

The synchronization acquisition circuit 9P, which is the second modification of the first embodiment, can determine the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position. The number of DPRAMs 911 can be reduced to (NA-1) compared to the synchronization acquisition circuit 9 of the first embodiment.

Modification 3 of Embodiment 1.
In this modification, Embodiment 1 is modified in the following points.
(1) The number of DPRAMs is increased by one, and the second correlation value B read from the DPRAM in which the second correlation value B calculated by the CB correlation processing unit 901 is written is not used by the first correlation value calculation unit 124. .

FIG. 30 is a diagram showing the configuration of the synchronization acquisition circuit 9Q of the third modification of the first embodiment. The synchronization acquisition circuit 9Q has a modified CA correlation processing section 910Q. The CA correlation processing unit 910Q has a memory 23Q. The memory 123Q has (NA+1) DPRAMs 911(1) to 911(NA+1). The second correlation values B read from the DPRAMs 911(1) to 911(NA) are input to chip correlation units 912(1) to 912(NA), respectively. Each of the chip correlation units 912(1) to 912(NA) calculates the product of the second correlation value B read from the DPRAMs 911(1) to 911(NA) and the spreading codes CA[1] to CA[NA]. Output.

The second correlation value B calculated by the CB correlation processing unit 901P is written to the DPRAM 911 (NA+1). The second correlation value B read from DPRAM 911 (NA+1) is written to DPRAM 911 (NA). The second correlation value B read from DPRAM 911(i) is written to DPRAM 911(i-1). The second correlation value B read from DPRAM 911(2) is written to DPRAM 911(1). Writing and reading of the second correlation value B to and from the DPRAMs 911(1) to 911(NA+1) can be performed simultaneously.

The synchronization acquisition circuit 9Q can also determine the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position. As shown in the first embodiment and its second and third modifications, the number of DPRAMs 911 included in the CA correlation processing section may be (NA-1) or more.

Modification 4 of Embodiment 1.
In this modification, Embodiment 1 is changed in the following three points.
(1) Change DPRAM to RAM, and read and write the second correlation value B from the RAM at different timings.
(2) The number of RAMs is set to (NA-1), and the second correlation value B before being stored in the memory 123R is used for calculating the first correlation value A.
(3) The CB correlation processing unit 901P calculates the second correlation value B using one received signal for one chip.

FIG. 31 is a diagram showing the configuration of the synchronization acquisition circuit 9R of the fourth modification of the first embodiment. The synchronization acquisition circuit 9R has a CB correlation processing section 901P similar to the second modification. The synchronization acquisition circuit 9R has a modified CA correlation processing section 910R. The CA correlation processing unit 910R has a memory 123R. The memory 123R includes (NA-1) RAMs (Random Access Memories) 914(1) to 914(NA-1). The RAM 914(i) has a single port and can store 2NB second correlation values B. RAM 914(i) can only be read or written at one time. (NA-1) is the minimum number of units that is the number obtained by subtracting 1 from the first sequence length NA. The memory 123R is a second correlation value storage unit that stores a number of second correlation values B that is greater than or equal to the product of 2NB times (NA-1) units. The second correlation value B stored in the memory 123R is calculated by the second correlation value calculating section 122P by shifting the received signal by one time point.

The product of the second correlation value B read from the RAM 914(1) and the spreading code CA[1] is calculated by the chip correlation unit 912(1). The product of the second correlation value B read from the RAM 914(i) and the spreading code CA[i] is calculated by the chip correlation unit 912(i). The chip correlation unit 912 (NA-1) calculates the product of the second correlation value B read from the RAM 914 (NA-1) and the spreading code CA[NA-1]. The second correlation value B calculated by the CB correlation processing unit 901P and not yet stored in the memory 123R is input to the chip correlation unit 912 (NA). The chip correlation unit 912 (NA) outputs the product of the second correlation value B calculated by the CB correlation processing unit 901P and not yet stored in the memory 123R and the spreading code CA[NA].

When the CB correlation processing unit 901P calculates the second correlation value B, the second correlation value B is input to the chip correlation unit 912 (NA). At the same time, the second correlation values B are read from (NA-1) RAMs 914(1) to 914(NA-1). Processing is performed to obtain the products of NA chip correlation units 912(1) to 912(NA). A process of writing the second correlation value B used by the chip correlation units 912(2) to 912(NA) into (NA-1) RAMs 914(1) to 914(NA-1) is performed. This process is repeated every time the complex BB signal (BBI3+jBBQ3) is input.

The synchronization acquisition circuit 9R of the fourth modification of the first embodiment can determine the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position. Since a single-port RAM is used, reading and writing of the second correlation value B in each RAM are performed at different timings.

Embodiment 2.
FIG. 32 is a diagram showing the configuration of the synchronization acquisition circuit 9B of the second embodiment.
The synchronization acquisition circuit 9B of the second embodiment differs from the synchronization acquisition circuit 9 of the first embodiment in the following points.
The CA correlation processing unit 910B includes a selection unit 915, a memory 123B, and an allocation unit 916 in place of the memory 123 configured by NA DPRAMs 911(1) to 911(NA). The memory 123B includes (NA+1) RAMs 914(1) to 914(NA+1).

The RAM 914(i) has a single port and can store 2NB second correlation values B. RAM 914(i) can only be read or written at one time.

The second correlation value B output by the CB correlation processing unit 901 is written into one of the RAMs 914(1) to 914(NA). The selection unit 915 selects one of the (NA+1) RAMs 914(1) to 914(NA+1) for writing.

The selection unit 915 selects the write RAM 914(jw) from among the (NA+1) RAMs 914(1) to 914(NA+1). jw represents the number of RAM 914 for writing. jw=1 to NA+1. jw is sequentially increased by 1. After jw=NA+1, it returns to jw=1. The fact that the RAM is ordered in such a way that jw takes 1 after the maximum value is called that the RAM is cyclically ordered.

2NB second correlation values B are sequentially written into the RAM 914 (jw) selected for writing. For example, the address control unit 954 sequentially increases the specified address of the circular write pointer WP from address 0 to address (2NB-1) in the RAM 914 (jw), so that 2NB second correlation values B are stored in the RAM 914 (jw). jw). After that, the selection unit 915 increases jw by 1.

One second correlation value B is read from each of the NA RAMs 914 (jr[k]) that are not for writing. jr[k] represents the number of RAM 914 that is not for writing. jr[k]=1~NA+1, jr[k]≠jw, k=1~NA. The second correlation value B read from the RAM 914 (jr[k]) and the second correlation value B read from the RAM 914 (jr[k+1]) are outputted by the CB correlation processing unit 901 with an interval of 2NB. It is something. For example, the address control unit 954 sequentially increases the designated address of the circular read pointer RP from address 0 to address (2NB-1) in NA RAMs 914 (jr[k]). When the circular read pointer RP specifies address X, the second correlation value B of address X in NA RAMs (jr[k]), k=1 to NA, is read. These NA second correlation values B are the calculation results of 2NB intervals in the CB correlation processing unit 901. Also in the write RAM 914 (jw), the circular write pointer WP writes the second correlation value B at the address X position. When the address X becomes (2NB-1), the 2NBth second correlation value B is written in the write RAM 914 (jw), and then jw is updated. Further, the second correlation value B at the address (2NB-1) is read from each of the NA RAMs 914 (jr[k]), and jr[k] is updated.

The allocation unit 916 allocates the second correlation value B read from the RAM 914 (jr[k]) with the number jr[k] to the chip correlation unit 912(k) with the number k according to equation (3). Here, the RAM number assigned to the chip correlating unit 912(k) with number k is expressed as jr[k].
jr[k]=1+mod(jw+NA+k, NA+1)...(3)

FIG. 33 is a diagram showing allocation when number jw=1 of RAM 914 for writing in the second embodiment.
When jw=1, for example, when k=1, jr[1]=2, when k=2, jr[2]=3, and when k=NA, jr[NA]=NA+1. Become. Therefore, the second correlation value B read from the RAM 914(2) is sent to the chip correlation unit 912(1). The second correlation value B read from the RAM 914(3) is sent to the chip correlation unit 912(2). The second correlation value B read from the RAM 914 (NA+1) is sent to the chip correlation section 912 (NA).

FIG. 34 is a diagram showing allocation when number jw=NA of RAM 914 for writing in the second embodiment.
When jw=NA, for example, when k=1, jr[1]=NA+1, when k=2, jr[2]=1, and when k=NA, jr[NA]=NA- It becomes 1. Therefore, the second correlation value B read from the RAM 914 (NA+1) is sent to the chip correlation section 912(1). The second correlation value B read from the RAM 914(1) is sent to the chip correlation unit 912(2). The second correlation value B read from the RAM 914 (NA-1) is sent to the chip correlation section 912 (NA).

The first correlation value calculation unit calculates the first correlation value using the second correlation value B read out one by one from each of the NA RAMs 912 in a cyclically consecutive order that are not selected as write RAMs. Calculate A.

Writing the second correlation value B to the RAM 914 for writing (jw) and NA RAMs 914 not for writing (jr[k]), jr[k]=1 to NA+1, jr[k]≠jw , k=1 to NA may be read out simultaneously or at different timings.

In this embodiment, the synchronization acquisition circuit 9B uses a single-port RAM 914, so the configuration and operation are simpler than the synchronization acquisition circuit 9 of the first embodiment. Furthermore, in the synchronization acquisition circuit 9 of the first embodiment, the second correlation value B is written into the DPRAM NA times every time the first correlation value A is calculated once. In contrast, in the synchronization acquisition circuit 9A of the present embodiment, the second correlation value B is written into the RAM only once every time the first correlation value A is calculated once.

Modification 1 of Embodiment 2.
FIG. 35 is a diagram showing the configuration of a synchronization acquisition circuit 9C according to a modification of the second embodiment. Modification 1 of Embodiment 2 is a case where oversampling is not performed.
The synchronization acquisition circuit 9C includes a CB correlation processing section 901A similarly to the synchronization acquisition circuit 9A of the first modification of the first embodiment.
The difference between the CA correlation processing unit 910C of the first modification of the second embodiment and the CA correlation processing unit 910B of the second embodiment is that the selection unit 915C, the memory 123B, and the allocation unit 916 are replaced by a selection unit 915C, It includes a memory 123C and an allocation section 916C.

The memory 123C includes (NA+1) RAMs 914C(1) to 914C(NA+1). The RAM 914C(i) has a single port and stores NB second correlation values B. RAM 914C(i) can only be read or written at one time.

The second correlation value B output by the CB correlation processing unit 901A is written into one of the RAMs 914C(1) to 914C(NA). The selection unit 915C selects one of the (NA+1) RAMs 914C(1) to 914C(NA+1) for writing.

The selection unit 915C selects the write RAM 914C(jw) from among the (NA+1) RAMs 914C(1) to 914C(NA+1). jw=1 to NA+1. jw is sequentially increased by 1. After jw=NA+1, it returns to jw=1.

NB second correlation values B are sequentially written into the selected RAM 914C (jw). For example, the address control unit 954 sequentially increases the specified address of the circular write pointer WP from address 0 to address (NB-1) in the RAM 914C (jw), so that NB second correlation values are stored in the RAM 914C (jw). ) is written to. After that, the selection unit 915C increases jw by 1.

One second correlation value B is read from each of the NA RAMs 914C (jr[k]) that are not for writing. jr[k]=1~NA+1, jr≠jw, k=1~NA.

The second correlation value B read from the RAM 914C(i) and the second correlation value B read from the RAM 914C(i+1) are outputted by the CB correlation processing unit 901A with an interval of NB. For example, the address control unit 954 sequentially increases the designated address of the circular read pointer RP from address 0 to address (NB-1) in the NA RAMs 914C (jr). When the circular read pointer RP specifies the address X, the second correlation value B of the address X in the NA RAMs (jr) is read. These NA second correlation values B are the calculation results of the NB intervals in the CB correlation processing section 901A.

The allocation unit 916C allocates the second correlation value B read from the RAM 914C (jr[k]) to the chip correlation unit 912(k) according to equation (3).
jr[k]=1+mod(jw+NA+k, NA+1)...(3)

The synchronization acquisition circuit 9R of the first modification of the second embodiment can determine the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position.

Modification 2 of Embodiment 2.
In the second modification, the second embodiment is modified in the following points.
(1) The number of RAMs is reduced by two, and the second correlation value B before being stored in the memory 123S is used for calculating the first correlation value A.

FIG. 36 is a diagram showing the configuration of a synchronization acquisition circuit 9S according to a second modification of the second embodiment. The synchronization acquisition circuit 9S has a modified CA correlation processing section 910S. The CA correlation processing unit 910S has a modified memory 123S, selection unit 915S, and allocation unit 916S. The memory 123S has (NA-1) RAMs 914(1) to 914(NA-1).

The selection unit 915S selects one of the (NA-1) RAMs 914(1) to 914(NA-1) for writing. The selection unit 915S selects the RAM 914(jw) for writing from among the (NA-1) RAMs 914(1) to 914(NA-1). jw=1 to NA-1. jw is sequentially increased by 1. After jw=NA-1, it returns to jw=1.

The allocation unit 916S reads one second correlation value B from each of the (NA-1) RAMs 914 (jr[k]). jr[k]=1 to NA-1, k=1 to NA-1. The second correlation value B read from the RAM 914 (jr[k]) and the second correlation value B read from the RAM 914 (jr[k+1]) are outputted by the CB correlation processing unit 901 with an interval of 2NB. It is something. The second correlation value B calculated by the CB correlation processing unit 901P and not yet stored in the memory 123S is separated by 2NB intervals from the second correlation value B read out from the RAM 914 (jr[NA-1]). This is what the CB correlation processing unit 901 outputs.

The allocation unit 916S allocates the second correlation value B read from the RAM 914 (jr[k]) to the chip correlation unit 912(k) according to equation (3A). Note that jr[1]=jw.
jr[k]=1+mod(jw-2+NA-1+k, NA-1)...(3A)

FIG. 37 is a diagram showing the allocation when number jw=1 of the write RAM 914 in the second modification of the second embodiment. When jw=1, for example, when k=1, jr[1]=1, when k=2, jr[2]=2, and when k=NA-1, jr[NA-1]= It becomes NA-1.
FIG. 38 is a diagram showing allocation when number jw=NA-1 of RAM 914 for writing in the second modification of the second embodiment. When jw=NA-1, for example, when k=1, jr[1]=NA-1, when k=2, jr[2]=1, and when k=NA-1, jr[NA -1]=NA-2.

When the CB correlation processing unit 901 calculates the second correlation value B, the calculated second correlation value B (not yet stored in the RAM 914) is input to the chip correlation unit 912 (NA). The allocation unit 916C reads one second correlation value B from each of the (NA-1) RAMs 914 (jr[k]), k=1 to NA-1, and sends it to the chip correlation unit 912(k). input. The chip correlation unit 912(k), k=1 to NA, multiplies the input second correlation value B and the spreading code CA[k]. Adder 913 adds the outputs of NA chip correlation units 912(1) to 912(NA) and outputs a first correlation value A.

When the first correlation value A is calculated, the second correlation value B calculated by the CB correlation processing unit 901 and not yet stored in the memory 123S is read out into the RAM 914 (jw). Write to the memorized location. Thereafter, the second correlation value B at the next point in time is calculated by the CB correlation processing unit 901, and the same process is repeated.

The synchronization acquisition circuit 9S of the second modification of the second embodiment can determine the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position. In the second modification of the second embodiment, the number of single-port RAMs can be reduced by two compared to the second embodiment.

Modification 3 of Embodiment 2.
In the third modification, the second embodiment is modified in the following points.
(1) The number of RAMs is reduced by one, and NA second correlation values B stored in the memory 123T are used to calculate the first correlation value A.
(2) The CB correlation processing unit 901P uses one received signal for one chip to calculate the second correlation value B.

FIG. 39 is a diagram showing the configuration of the synchronization acquisition circuit 9T of the third modification of the second embodiment. The synchronization acquisition circuit 9T has a modified CA correlation processing section 910T. The CA correlation processing unit 910T has a modified memory 123T, selection unit 915T, and allocation unit 916T. The memory 123T has NA RAMs 914(1) to 914(NA).

The selection unit 915T selects one of the NA RAMs 914(1) to 914(NA) for writing. The selection unit 915T selects the write RAM 914(jw) from among the NA RAMs 914(1) to 914(NA). jw=1 to NA. jw is sequentially increased by 1. After jw=NA, it returns to jw=1.

The allocation unit 916T reads one second correlation value B from each of the NA RAMs 914 (jr[k]). jr[k]=1~NA, k=1~NA. The second correlation value B read from the RAM 914 (jr[k]) and the second correlation value B read from the RAM 914 (jr[k+1]) are outputted by the CB correlation processing unit 901 with an interval of 2NB. It is something.

The allocation unit 916T allocates the second correlation value B read from the RAM 914 (jr[k]) to the chip correlation unit 912(k) according to equation (3B). Note that jr[NA]=jw.
jr[k]=1+mod(jw-1+NA+k, NA)...(3B)

FIG. 40 is a diagram showing allocation when number jw=NA of RAM 914 for writing in the third modification of the second embodiment. When jw=NA, for example, when k=1, jr[1]=1, when k=2, jr[2]=2, and when k=NA-1, jr[NA-1]= NA-1, and when k=NA, jr[NA]=NA.
FIG. 41 is a diagram showing the allocation when number jw=1 of the write RAM 914 in the third modification of the second embodiment. When jw=1, for example, when k=1, jr[1]=2, when k=2, jr[2]=3, and when k=NA-1, jr[NA-1]= NA, and when k=NA, jr[NA]=1.

When the CB correlation processing unit 901P calculates the second correlation value B, it is written into the RAM 914 (jw) selected by the selection unit 915T. The allocation unit 916T allocates the second correlation value B read from the RAM 914 (jr[k]), k=1 to NA, to the chip correlation unit 912(k) according to equation (3B). Note that the second correlation value B read from the RAM 914 (jw) is one that was written recently. The chip correlation unit 912(k), k=1 to NA, outputs the product of the input second correlation value B and the spreading code CA[k]. Adder 913 adds the outputs of NA chip correlation units 912(1) to 912(NA) and outputs a first correlation value A. Such processing is repeated.

The synchronization acquisition circuit 9T of the third modification of the second embodiment can determine the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position.

In the write RAM 914 (jw), the address XW pointed to by the circular write pointer WP may be different from the address XR pointed to by the circular read pointer RP. When the address XW pointed to by the circular write pointer WP is different from the address XR pointed to by the circular read pointer RP, the timing to update jw and the timing to update jr[k], k=1 to NA are different. It turns out.

If jr[NA]=jw, then XW>XR. When XW becomes "2NB", jw=jw+1 and XW="0". However, if jw>NA, then jw=1. When jw is updated by adding 1, jr[1]=jw. If jr[1]=jw, then XW<XR. In this state, when XR becomes "2NB", jr[k], k=1 to NA are updated as follows to set XR="0".
jr[k]=jr[k+1], k=1~NA-1
jr[NA]=jr[1]
When jr[k] is updated, the state becomes jr[NA]=jw, XW>XR.

Differentiating the address XW pointed to by the circular write pointer WP and the address XR pointed to by the circular read pointer RP can also be applied when the number of write RAMs 914 is (NA+1) or more.

Embodiment 3.
The synchronization acquisition circuit of the third embodiment uses one RAM.
FIG. 42 is a diagram showing the configuration of synchronization acquisition circuit 9D according to the third embodiment.
The synchronization acquisition circuit 9D of the third embodiment differs from the synchronization acquisition circuit 9 of the first embodiment in the following points.
The CA correlation processing unit 910D includes a write control unit 917, a RAM 123D, and a read control unit 918 in place of the memory 123 configured by NA DPRAMs 911(1) to 911(NA). The write control section 917, RAM 123D, and read control section 918 constitute a second correlation value storage section.

The RAM 123D has a single port and can store NN2 second correlation values B. However, NN2≧2NB*(NA-1)+1. RAM 123D can only be read or written at one time. Here, N _ALW =NN2-(2NB*(NA-1)+1). _NALW represents how much larger the number NN2 of the second correlation values B that can be stored in the RAM 123D is than the required minimum number that can be stored. N _ALW ≧0.

The write control unit 917 writes the second correlation value B to the address specified by jw in the RAM 123D. jw=0 to NN2-1. jw is sequentially increased by 1. After jw=NN2-1, it returns to jw=0. The write control unit 917 is a write circuit that writes the second correlation value B that is not stored in the RAM 123D.

After writing the second correlation value B to the address specified by jw in the RAM 123D, the read control unit 918 reads the NA second correlation values B output by the CB correlation processing unit 901 with an interval of 2NB. Read from RAM123D. The read control unit 918 outputs the second correlation value B read from the address jr[k], k=1 to NA in the RAM 123D to the chip correlation unit 912(k) according to equation (4). Here, the difference between jw and jr[NA] is represented by a variable _NOST . N _ALW ≧N _OST ≧0.
jr[k]=mod(jw-N _OST +2NB*(k-1), NN2)...(4)

An example of read control when N _ALW =N _OST =0 will be described.
FIG. 43 is a diagram showing read control when write address jw=2NB*(NA-1) in the third embodiment.
When jw=NN2-1=2NB*(NA-1), for example, when k=1, jr=0, when k=2, jr=2NB, and when k=NA-1, jr= 2NB*(NA-2), and when k=NA, jr=2NB*(NA-1).
Therefore, the second correlation value B read from the address "0" is sent to the chip correlation section 912(1). The second correlation value B read from the address "2NB" is sent to the chip correlation unit 912(2). The second correlation value B read from the address "2NB*(NA-2)" is sent to the chip correlation unit 912 (NA-1). The second correlation value B read from the address "2NB*(NA-1)" is sent to the chip correlation unit 912 (NA).

FIG. 44 is a diagram showing read control when write address jw=1 in the third embodiment.
When jw=1, for example, when k=1, jr=2, when k=2, jr=2NB+2, when k=NA-1, jr=2NB*(NA-2)+2, When k=NA, jr=1.
Therefore, the second correlation value B read from address "2" is sent to chip correlation section 912(1). The second correlation value B read from the address "2NB+2" is sent to the chip correlation unit 912(2). The second correlation value B read from the address "2NB*(NA-2)+2" is sent to the chip correlation unit 912 (NA-1). The second correlation value B read from address "1" is sent to the chip correlation unit 912 (NA).

The synchronization acquisition circuit 9D of the third embodiment can determine the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position.

The readout control unit 918 is a readout circuit that reads out the second correlation value B calculated by the second correlation value calculation unit 122 at every NA 2NB time point.

If N _ALW ≧ N _OST > 0, the read control unit 918 reads the NA second correlation values B output by the CB correlation processing unit 901 with an interval of 2NB, and then performs the write operation. The control unit 917 may write the second correlation value B to the address specified by jw in the RAM 123D.

Modification 1 of Embodiment 3.
FIG. 45 is a diagram showing the configuration of a synchronization acquisition circuit 9E according to a modification of the third embodiment. Modification 1 of Embodiment 3 is a case where oversampling is not performed.
The synchronization acquisition circuit 9E includes a CB correlation processing section 901A similarly to the synchronization acquisition circuit 9A of the first modification of the first embodiment.
The difference between the CA correlation processing unit 910E of the first modification of the third embodiment and the CA correlation processing unit 910D of the third embodiment is that a write control unit 917, a RAM 123D, and a read control unit 918 are replaced with a It includes a control section 917E, a RAM 123E, and a read control section 918E.

The RAM 123E has a single port and can store NN second correlation values B. However, NN≧NB*(NA-1)+1. RAM 123E can only be read or written at one time. Here, N _ALW =NN-(NB*(NA-1)+1). N _ALW represents how much larger the number NN of second correlation values B that can be stored in the RAM 123E is than the required minimum number that can be stored. N _ALW ≧0.

The write control unit 917E writes the second correlation value B to the address specified by jw in the RAM 123E. jw=0 to NN-1. jw is sequentially increased by 1. After jw=NN-1, it returns to jw=0.

After writing the second correlation value B to the address specified by jw in the RAM 123E, the read control unit 918E reads NA second correlation values B for each NB from the RAM 123E. The read control unit 918E outputs the second correlation value B read from the address jr[k], k=1 to NA in the RAM 123E to the chip correlation unit 912(k) according to equation (5).
jr[k]=mod(jw-N _OST +NB*(k-1), NN)...(5)

An example of read control when N _ALW =N _OST =0 will be described.
FIG. 46 is a diagram showing read control when write address jw=NN-1=NB*(NA-1) in Modification 1 of Embodiment 3.
When jw=NB*(NA-1), for example, when k=1, jr=0, when k=2, jr=NB, and when k=NA-1, jr=NB*(NA -2), and when k=NA, jr=NB*(NA-1).
Therefore, the second correlation value B read from the address "0" is sent to the chip correlation section 912(1). The second correlation value B read from the address "NB" is sent to the chip correlation section 912 (NA-2). The second correlation value B read from the address "NB*(NA-2)" is sent to the chip correlation unit 912 (NA-1). The second correlation value B read from the address "NB*(NA-1)" is sent to the chip correlation unit 912 (NA).

The synchronization acquisition circuit 9E of the first modification of the third embodiment can determine the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position.

The readout control unit 918E is a readout circuit that reads out the second correlation value B calculated by the second correlation value calculation unit 122 at each time point of NA NB.

If N _ALW ≧ N _OST > 0, the read control unit 918E reads the NA second correlation values B output by the CB correlation processing unit 901 with NB intervals, and then performs the write operation. The control unit 917E may write the second correlation value B to the address specified by jw in the RAM 123E.

Modification 2 of Embodiment 3.
In the second modification, the third embodiment is modified in the following points.
(1) The second correlation value B before being stored in the memory is used to calculate the first correlation value A.
(2) The CB correlation processing unit 901P uses one received signal for one chip to calculate the second correlation value B.

FIG. 47 is a diagram showing the configuration of the synchronization acquisition circuit 9U according to the second modification of the third embodiment. The synchronization acquisition circuit 9U has a CB correlation processing section 901P similar to the second modification of the first embodiment. In the synchronization acquisition circuit 9U, the write control section 917U, RAM 123U, and read control section 918U are changed.

The RAM 123U has a single port and can store NN2U second correlation values B. However, NN2U=2NB*(NA-1). RAM 123U can only be read or written at one time.

The read control unit 918U reads (NA-1) second correlation values B outputted by the CB correlation processing unit 901P at intervals of 2NB from the RAM 123U. The read control unit 918U outputs the second correlation value B read from the address jr[k], k=1 to NA-1 in the RAM 123U, to the chip correlation unit 912(k) according to equation (4A). Note that jr[1]=jw.
jr[k]=mod(jw+2NB*(k-1), NN2U)...(4A)

FIG. 48 is a diagram showing read control when write address jw=0 in Modification 1 of Embodiment 3. When jw=0, for example, jr=0 when k=1, jr=2NB when k=2, and jr=2NB*(NA-2) when k=NA-1.

The second correlation value B calculated by the CB correlation processing unit 901P and not yet stored in the RAM 123U is input to the chip correlation unit 912 (NA). The chip correlation unit 912(k), k=1 to NA, multiplies the input second correlation value B and the spreading code CA[k]. Adder 913 adds the outputs of NA chip correlation units 912(1) to 912(NA) and outputs a first correlation value A.

When the first correlation value A is calculated, the second correlation value B calculated by the CB correlation processing unit 901P and not yet stored in the RAM 123U is written to the address jw of the RAM 123U. Thereafter, the second correlation value B at the next point in time is calculated by the CB correlation processing unit 901, and the same process is repeated.

The read control unit 918U obtains the second correlation value B calculated by the second correlation value calculation unit 122 at every NA 2NB time point, including the time point at which the second correlation value B not stored in the RAM 123U is calculated. This is a readout circuit that reads out the second correlation values B for the minimum number of devices that can be used.

The synchronization acquisition circuit 9U of the second modification of the third embodiment can determine the spreading code phase correction value (-θ _PN ), that is, the synchronization sequence position.

(Other variations)
The present invention is not limited to the above-described embodiments, and includes, for example, the following modifications.
(1) When the second spreading code CB is "-1", the chip correlation unit inverts the bits of the complex BB signal (in other words, converts it into a 1's complement) instead of converting it into a 2's complement of the input signal. It is also possible to output a value obtained by adding 1 at the end. Alternatively, by using the fact that the numbers of positive and negative signs of the input data are stochastically equal, it is assumed that there are NB/2 negative numbers, and the chip correlation unit calculates the second spreading code CB. is "-1", the value obtained by inverting the bits of the complex BB signal is output, and the adder adds NB/2 to the sum of the outputs of the 2NB chip correlation units 903(1) to 903(2NB). You may add a constant of .

(2) The CA correlation processing section may include the chip correlation section 912, and the CB correlation processing section may include the multiplier 803. Alternatively, the CA correlation processing section may include the multiplier 812, and the CB correlation processing section may include the chip correlation section 903.

(3) Power C may be averaged over multiple symbols. For example, the averaging processing unit calculates the average power D of the j-th sample by averaging the power C of the j-th sample (j=1-2*NA*NB) of the N i-th symbols (i=1-N). (j) may also be calculated. By averaging the power C, the influence of noise can be reduced.

(4) The synchronization acquisition circuit 9 may calculate a complex correlation value (ΣI+jΣQ) and output it to the demodulator. The demodulator may calculate θ=atan ⁻¹ (ΣQ/ΣI) and perform initial phase correction (fixed rotation of the phase in the −θ direction) in the demodulator.

The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims rather than the above description, and it is intended that all changes within the meaning and range equivalent to the claims are included.

1, 1A spread spectrum receiver, 2 analog receiver, 3 ADC, 4 quadrature detector, 5, 5A timing corrector, 6 AGC, 7, 7A despreader, 8 synchronous follow-up circuit, 9, 9A, 9B, 9C, 9D, 9E, 9F, 9P, 9Q, 9R, 9S, 9T, 9U Synchronization acquisition circuit, 21 BPF, 22 AMP, 23, 43, 44 LPF, 41, 42, 61a, 61b, 67a, 67b, 71, 72, 73, 74, 75, 76, 88a, 88b, 803, 812, 1003, 2003, 3003 Multiplier, 45 cos/-sin generator, 46, 54 NCO, 49, 55, 64, 85, 86, 904 , 913 Adder, 51, 52 FIR filter type resampler, 53 Filter coefficient update unit, 63a, 63b, 81, 82, 83, 84 Square circuit, 65 First converter, 66, 87 Subtractor, 68, 89 LF section, 69 Second converter, 77, 78 1 sample delay circuit, 79, 300 Spreading code generator, 91, 92, 93, 94, 95, 96 Integrating & thinning circuit, 121, 121A, 121P, 223 Delay processing unit, 122, 122A, 122P, 222 Second correlation value calculation unit, 123, 123A, 123B, 123C, 123P, 123Q, 123R, 123S, 123T Memory, 124, 224 First correlation value calculation unit, 811, 902 D-type flip-flop, 820 Delay processing unit, 901, 901A, 901F, 901P CB correlation processing unit, 910, 910A, 910B, 910C, 910D, 910E, 910F, 910P, 910Q, 910R, 910S, 910T, 910U CA correlation processing Section, 903, 912 Chip correlation section, 911, 911A DPRAM, 123D, 123E, 123U, 914, 914C RAM, 915, 915C Selection section, 916, 916C Allocation section, 917, 917E, 917U Write control section, 918, 918E , 918U read control unit, 920 power calculation unit, 930 power storage unit, 940 peak detection unit, 951, 961 two's complement arithmetic unit, 952, 962 selector, 954 address control unit, 1001, 2001 CA generator, 1002, 2002 CB generator, 2004 phase correction section.

Claims (14)

a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
A storage number that is greater than or equal to the product of the number of intervals, which is the number of received signals included in the chip of the second sequence length, and the minimum number, which is the number obtained by subtracting 1 from the first sequence length. , a second correlation value storage unit that stores the second correlation value calculated by the second correlation value calculation unit by shifting the received signal one time at a time;
a first correlation value that is the sum of the products of each of the second correlation values of the number of first sequence lengths and each of the first spreading codes calculated by the second correlation value calculation unit at the time of each number of intervals; a first correlation value calculation unit that calculates
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit ;
The second correlation value storage unit stores the second correlation values in a number obtained by adding 1 to the interval number calculated by the second correlation value calculation unit at successive points in time, and stores the ordered first series. Including DPRAM which is RAM that can read and write at the same time,
The first correlation value calculation unit reads out the second correlation values from the DPRAM in which the order of the second correlation values is consecutive, one by one, from the top of the DPRAM in which the number is equal to or greater than the first sequence length. Calculating the first correlation value using the second correlation value of the number of read first sequence lengths,
The second correlation value that is not stored in the second correlation value storage unit is written to the first DPRAM, and the second correlation value is read out from the DPRAM when calculating the first correlation value. The second correlation value read from the DPRAM that is not last in order is written to the DPRAM that is next in order . a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
A storage number that is greater than or equal to the product of the number of intervals, which is the number of received signals included in the chip of the second sequence length, and the minimum number, which is the number obtained by subtracting 1 from the first sequence length. , a second correlation value storage unit that stores the second correlation value calculated by the second correlation value calculation unit by shifting the received signal one time at a time;
a first correlation value that is the sum of the products of each of the second correlation values of the number of first sequence lengths and each of the first spreading codes calculated by the second correlation value calculation unit at the time of each number of intervals; a first correlation value calculation unit that calculates
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
The second correlation value storage unit stores the second correlation values of the number obtained by adding 1 to the interval number calculated by the second correlation value calculation unit at consecutive points in time, and stores the ordered minimum number of units. Including DPRAM, which is a RAM that can be read and written at the same time,
The first correlation value calculation unit calculates the first correlation value using the second correlation value not stored in the second correlation value storage unit and the second correlation value read out one by one from the DPRAM. Calculate,
After calculating the first correlation value, the second correlation value that is not stored in the second correlation value storage section is written to the first DPRAM, and the second correlation value is used when calculating the first correlation value. The second correlation value read from the DPRAM which is not last in the order among the DPRAMs from which the second correlation value is read is written to the next DPRAM in the order. a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
A storage number that is greater than or equal to the product of the number of intervals, which is the number of received signals included in the chip of the second sequence length, and the minimum number, which is the number obtained by subtracting 1 from the first sequence length. , a second correlation value storage unit that stores the second correlation value calculated by the second correlation value calculation unit by shifting the received signal one time at a time;
a first correlation value that is the sum of the products of each of the second correlation values of the number of first sequence lengths and each of the first spreading codes calculated by the second correlation value calculation unit at the time of each number of intervals; a first correlation value calculation unit that calculates
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
The second correlation value storage unit stores the minimum number of ordered single ports for storing the second correlation values of the interval number calculated by the second correlation value calculation unit at consecutive points in time. including RAM,
The first correlation value calculation unit calculates the first correlation value using the second correlation value not stored in the second correlation value storage unit and the second correlation value read out one by one from the RAM. Calculate,
After calculating the first correlation value, the second correlation value that is not stored in the second correlation value storage section is written to the RAM at the beginning, and when calculating the first correlation value, the second correlation value is A synchronization acquisition circuit, wherein the second correlation value read from the RAM which is not last in the order among the RAMs read out is written to the RAM in the next order. a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
A storage number that is greater than or equal to the product of the number of intervals, which is the number of received signals included in the chip of the second sequence length, and the minimum number, which is the number obtained by subtracting 1 from the first sequence length. , a second correlation value storage unit that stores the second correlation value calculated by the second correlation value calculation unit by shifting the received signal one time at a time;
a first correlation value that is the sum of the products of each of the second correlation values of the number of first sequence lengths and each of the first spreading codes calculated by the second correlation value calculation unit at the time of each number of intervals; a first correlation value calculation unit that calculates
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
The second correlation value storage unit stores the second correlation values of the number of intervals calculated by the second correlation value calculation unit at consecutive time points, the number of which is greater than or equal to the ordered first sequence length. Contains single-port RAM of
The first correlation value calculation unit calculates the first sequence length of the second correlation values read out one by one from the RAM in which the order of the first sequence length or more is consecutive from the beginning. calculating the first correlation value using the second correlation values read from the RAM in which the order of numbers is continuous;
The second correlation value that is not stored in the second correlation value storage section is written to the first RAM, and the second correlation value is read out from the RAM when calculating the first correlation value. The second correlation value read from the RAM that is not last in order is written to the RAM that is next in order. a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
A storage number that is greater than or equal to the product of the number of intervals, which is the number of received signals included in the chip of the second sequence length, and the minimum number, which is the number obtained by subtracting 1 from the first sequence length. , a second correlation value storage unit that stores the second correlation value calculated by the second correlation value calculation unit by shifting the received signal one time at a time;
a first correlation value that is the sum of the products of each of the second correlation values of the number of first sequence lengths and each of the first spreading codes calculated by the second correlation value calculation unit at the time of each number of intervals; a first correlation value calculation unit that calculates
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
The second correlation value storage unit stores the second correlation values of the number of intervals calculated by the second correlation value calculation unit at successive points in time, and stores the first series in a cyclical order. Contains a number of single-port RAMs greater than or equal to the length plus 1,
a selection unit that selects a write RAM, which is the RAM to which the second correlation value calculated by the second correlation value calculation unit is written, in a cyclical order;
The first correlation value calculating unit is configured to calculate the second correlation value that is read out one by one from each of the first sequence lengths that are cyclically consecutive and that are not selected as the write RAM. A synchronization acquisition circuit that calculates the first correlation value using the correlation value. a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
A storage number that is greater than or equal to the product of the number of intervals, which is the number of received signals included in the chip of the second sequence length, and the minimum number, which is the number obtained by subtracting 1 from the first sequence length. , a second correlation value storage unit that stores the second correlation value calculated by the second correlation value calculation unit by shifting the received signal one time at a time;
a first correlation value that is the sum of the products of each of the second correlation values of the number of first sequence lengths and each of the first spreading codes calculated by the second correlation value calculation unit at the time of each number of intervals; a first correlation value calculation unit that calculates
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
The second correlation value storage unit stores the second correlation values of the number of intervals calculated by the second correlation value calculation unit at consecutive points in time, and stores the number of the minimum number of units in a cyclically ordered manner. Contains single-port RAM
a selection unit that selects a write RAM, which is the RAM to which the second correlation value not stored in the second correlation value storage unit is written, in a cyclical order;
The first correlation value calculation unit reads out the second correlation values not stored in the second correlation value storage unit and the minimum number of units in a cyclical order from each of the RAMs, one by one. The synchronization acquisition circuit calculates the first correlation value using the second correlation value. a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
A storage number that is greater than or equal to the product of the number of intervals, which is the number of received signals included in the chip of the second sequence length, and the minimum number, which is the number obtained by subtracting 1 from the first sequence length. , a second correlation value storage unit that stores the second correlation value calculated by the second correlation value calculation unit by shifting the received signal one time at a time;
a first correlation value that is the sum of the products of each of the second correlation values of the number of first sequence lengths and each of the first spreading codes calculated by the second correlation value calculation unit at the time of each number of intervals; a first correlation value calculation unit that calculates
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
The second correlation value storage unit stores the second correlation values of the number of intervals calculated by the second correlation value calculation unit at consecutive points in time, and stores the first sequence length that is cyclically ordered. including the number of single-port RAMs,
comprising a selection unit that selects a write RAM, which is the RAM to which the second correlation value not stored in the second correlation value storage unit is written, in a cyclical order;
The first correlation value calculation unit calculates the first correlation value using the second correlation values read out one by one from each of the RAMs of the number of first sequence lengths that are cyclically consecutive. A synchronous acquisition circuit that calculates. a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
A storage number that is greater than or equal to the product of the number of intervals, which is the number of received signals included in the chip of the second sequence length, and the minimum number, which is the number obtained by subtracting 1 from the first sequence length. , a second correlation value storage unit that stores the second correlation value calculated by the second correlation value calculation unit by shifting the received signal one time at a time;
a first correlation value that is the sum of the products of each of the second correlation values of the number of first sequence lengths and each of the first spreading codes calculated by the second correlation value calculation unit at the time of each number of intervals; a first correlation value calculation unit that calculates
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
The number of storage units is the number obtained by multiplying the number of intervals and the minimum number of units,
The second correlation value storage unit includes one RAM that stores the stored number of second correlation values calculated by the second correlation value calculation unit at consecutive times, and a RAM that stores the second correlation values that are not stored in the RAM. a write circuit that writes a correlation value to the RAM; and a write circuit that writes the correlation value to the RAM, and the write circuit that writes the correlation value to the RAM, and the write circuit that writes the correlation value to the RAM at a time point for each of the number of intervals of the number of the first sequence lengths, including the time point at which the second correlation value that is not stored in the RAM is calculated. including a readout circuit that reads out the second correlation value of the minimum number of units such that the second correlation value calculated by the second correlation value calculation unit can be obtained;
The first correlation value calculation unit calculates the first correlation value using the second correlation value not stored in the RAM and the second correlation values of the minimum number read by the readout circuit. calculate,
A synchronization acquisition circuit, wherein after calculating the first correlation value, the second correlation value that is not stored in the second correlation value storage section is written to the RAM. a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
A storage number that is greater than or equal to the product of the number of intervals, which is the number of received signals included in the chip of the second sequence length, and the minimum number, which is the number obtained by subtracting 1 from the first sequence length. , a second correlation value storage unit that stores the second correlation value calculated by the second correlation value calculation unit by shifting the received signal one time at a time;
a first correlation value that is the sum of the products of each of the second correlation values of the number of first sequence lengths and each of the first spreading codes calculated by the second correlation value calculation unit at the time of each number of intervals; a first correlation value calculation unit that calculates
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
The number of storage units is larger than the product of the number of intervals and the minimum number of units,
The second correlation value storage unit includes one RAM that stores the stored number of second correlation values calculated by the second correlation value calculation unit at consecutive times, and a RAM that stores the second correlation values that are not stored in the RAM. a write circuit that writes a correlation value to the RAM; and a read circuit that reads the second correlation value calculated by the second correlation value calculation unit at each time point of the number of intervals of the number of the first sequence lengths. ,
The first correlation value calculation unit is a synchronization acquisition circuit that calculates the first correlation value using the second correlation values of the first sequence length read by the readout circuit. a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
each of the second correlation values of the number of the first sequence length calculated by the second correlation value calculation unit at the time of each interval number which is the number of the received signals included in the chips of the second sequence length; a first correlation value calculation unit that calculates a first correlation value that is a sum of products of each of the first spreading codes;
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
At least one of the second correlation value calculation unit and the first correlation value calculation unit switches a binary value that generates a signal that is a product of two input signals from one of the signals using the other signal. includes a selector to output ,
When the second correlation value calculation unit includes the selector,
The selector outputs each received signal as is when the code of each second spreading code is "+1", and outputs each received signal as is when the code of each second spreading code is "-1". A synchronization acquisition circuit outputting a two's complement of the received signal . a first spreading code that is a pseudo-random number that has a first sequence length and changes in a first chip time; and a first spreading code that has a second sequence length and divides the first chip time by the second sequence length. has a cascade-connected code sequence length that is the product of the first sequence length and the second sequence length, which is obtained by multiplying by a second spreading code that is a pseudo-random number that changes with the second chip time. A spread spectrum receiver that receives a signal spread by a cascade spread code, which is a pseudo-random number that changes with the second chip time, calculates the number of received signals equal to the cascade code sequence length at discrete points in time. A synchronization acquisition circuit that calculates a synchronization sequence position that is a position of the cascaded spreading code to be multiplied in the cascaded code sequence length,
a second correlation value calculation unit that calculates a second correlation value that is a sum of products of each of the received signals and each of the second spreading codes of consecutive chips of the number of the second sequence length;
each of the second correlation values of the number of the first sequence length calculated by the second correlation value calculation unit at the time of each interval number which is the number of the received signals included in the chips of the second sequence length; a first correlation value calculation unit that calculates a first correlation value that is a sum of products of each of the first spreading codes;
a power calculation unit that calculates the power of the first correlation value;
a power storage unit that stores the power as many times as the cascade-connected code sequence length calculated by shifting the received signal one time at a time;
a peak detection unit that determines the synchronization sequence position based on the position where the power has a maximum value stored in the power storage unit;
At least one of the second correlation value calculation unit and the first correlation value calculation unit switches a binary value that generates a signal that is a product of two input signals from one of the signals using the other signal. includes a selector to output,
When the first correlation value calculation unit includes the selector,
The selector outputs each of the second correlation values as is when the code of each of the first spreading codes is "+1", and outputs each of the second correlation values as is when the code of each of the first spreading codes is "-1". , a synchronization acquisition circuit that outputs a two's complement number of each of the second correlation values. 12. The synchronization acquisition circuit according to claim 1, wherein the received signal is oversampled. The second correlation value calculation unit calculates the second correlation value as a sum of products of each of the received signals of the interval number and each of the second spreading codes determined for each chip in which each of the received signals is included. 13. The synchronization acquisition circuit according to claim 12 . The second correlation value calculation unit calculates the second correlation value as the sum of products of each of the received signals at a point in time for each of the second sequence lengths and each of the second spreading codes determined for each chip in which each of the received signals is included. 13. The synchronization acquisition circuit of claim 12 , wherein the synchronization acquisition circuit calculates two correlation values.

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