JP4945747B2 - Asynchronous code modulation signal receiver - Google Patents

Description

  The present invention relates to an asynchronous code modulation signal receiving apparatus that is used in, for example, a digital communication system and decodes a received asynchronous code modulation signal.

  In the receiving apparatus according to the related art, the data determination of the modulated signal and the detection of the synchronization point (timing) of the signal are performed in separate processes. Since a device for data determination and synchronization point detection must be prepared separately, the system becomes complicated. There are cases where data cannot be determined because synchronization cannot be achieved, or that data is erroneously determined even if synchronization is established.

  In a communication system according to the prior art in which signal timing synchronization and data determination are performed by separate processes and circuits, the receiver performs two steps of acquisition of synchronization and synchronization holding in order to match the timing of the signal. It is common. For synchronization acquisition, for example, an IQ matched filter bank is used, and when the timing of the signals coincides, the matched filter outputs an output signal having a larger value. Then, the output signal is input to the logic circuit, and the synchronization point is detected by determining the threshold value. When a synchronization point is detected, synchronization is held, and clock timing is adjusted by a delay locked loop (hereinafter referred to as DLL). This is a loop that delays the phase of the local oscillator, and controls to advance the phase if there is a delay phase and its correlation. In the logic circuit, if there is at least one code and time point synchronized by the threshold determination, the logic circuit shifts to synchronization holding, and control by DLL is performed. If there is no code and time point synchronized by the threshold value determination, the state is asynchronous, so the synchronization acquisition mode is entered again to detect the synchronization point.

  FIG. 14 is a block diagram showing a configuration of a code modulation apparatus according to the prior art disclosed in Patent Document 1, and FIG. 15 is a block diagram showing a configuration of a code modulation signal receiving apparatus according to the prior art disclosed in Patent Document 1. FIG. 16 is a block diagram showing the configuration of the correlator 74 in FIG. 15. FIG. 17 is a block diagram showing the configuration of the correlator 74A using a logic circuit that is a modification of the correlator 74 in FIG. 18 is a block diagram showing the configuration of the demodulator 76 of FIG. Further, FIG. 19 is a block diagram showing a configuration of the computers 114 and 124 of FIG. 18, and FIG. 20 is a block diagram showing a configuration of the computers 113 and 123 of FIG.

  The code modulation apparatus of FIG. 14 includes N code generators 70-1 to 70-N that respectively generate a plurality of N codes, a serial / parallel converter (hereinafter referred to as an S / P converter) 71, and the like. , And a switch 72. In the code modulation apparatus on the transmission side, N codes C1 to CN are generated by code generators 70-1 to 70-N, respectively, and an input data signal input via an input terminal T11 is converted to an S / P converter 71. By performing S / P conversion every m bits and controlling the switching of the switch 72 based on the S / P converted signal, n (<N) number of data bits of the m-bit input data signal are controlled. The code is modulated by synthesizing the code and transmitted through the output terminal T12.

  15 on the reception side includes a reception interface 73, a correlator 74, a synchronization controller 75, a demodulator 76, and a carrier detector 77. In the code modulation signal receiving apparatus, the reception signal input via the input terminal T21 is subjected to predetermined signal conversion by the reception interface 73, and then a correlation output signal of each code is obtained by the correlator 74.

  FIG. 16 is a diagram showing a configuration of a correlator 74 using SAW convolution units 78-1 to 78-N of surface acoustic wave (hereinafter referred to as SAW) filters. The correlator 74 stores a signal sequence of in-phase components in advance, and is not configured to combine with a correlation of signal sequences of quadrature components. In order to obtain a signal sequence of quadrature components, it is necessary to divide the received signal input via the input terminal T21 into two components of in-phase and quadrature in the signal processing at the reception interface 73. For this reason, this system has a configuration that assumes a communication system in which the phase is corrected in the reception interface 73 or does not involve a frequency shift, or a communication system that does not change phase between transmitters and receivers such as wired communication. It has become.

JP-A-9-069800. Marubayashi et al., “Spread Spectrum Communication and its Applications”, published by IEICE, pp. 94-146, issued May 10, 1998. D. A. Gandolfo et al., “Analog-binary CCD Correlator: a VLSI signal processor”, IEEE Transaction on Electron Devices, Vol. 26, No. 4, pp. 596-603, April 1979. P. Bosshart, "An Integrated Analog Correlator using Charge-Coupled Devices", Proceedings of IEEE ISSCC '76, pp. 198-199, February 20, 1976.

  In Non-Patent Document 1, several correlators are shown in addition to the correlator 74 of FIG. 16, for example, a correlator 74A using a logic circuit shown in FIG. In FIG. 17, the correlator 74 </ b> A includes two shift registers 81 and 82 and a logic circuit 84 including exclusive OR gates XOR <b> 1 to XORN and a signal addition amplifier 83. None of the correlators disclosed in Non-Patent Document 1 has a configuration in which orthogonal component signals are taken into consideration. In addition, after performing code determination using a threshold value at the chip level, a correlation output is obtained. Even when only in-phase components such as communication without frequency shift need to be considered, communication performance is normal. There was a problem that it was worse than the device.

FIG. 18 shows a demodulator 76 described in Non-Patent Document 1. In FIG. 18, the demodulator 76 includes two latch circuits 111 and 121, absolute value calculators 112 and 122, a P ₁ calculator 113, an A ₁ calculator 114, a P ₂ calculator 123, and an A ₂ calculator 124. And multipliers 115 and 116 and a comparator 117. Here, one data period T (equal to one cycle of the code) of the output signal from the correlator 74 can be divided into a window portion W at the center and end portions E at both ends thereof. 19 and 20 show peak value calculators 114 and 124 and maximum value calculators 113 and 123 which are maximum value holding circuits for the window W, respectively. In FIG. 19, the computer 115 includes a latch circuit 84 and a comparator 85. In FIG. 20, the computer 116 includes an adder 86 and a latch circuit 87. Here, if the duration of the code is T,
[Equation 1]
(T−d) = 2 <t <(T + d) = 2, (d <T) (1)
The end E is
[Equation 2]
0 <t <(Td) = 2 (2)
And [Equation 3]
(T + d) = 2 <t <T (3)
It is a section.

  In this specification, the number number of the black brackets in which the mathematical formula is imaged and the formula number of the square brackets in which the mathematical formula is input are used in combination. The formula number is assigned to the last part of the formula using the formula (1) as the formula number (there is also a formula that is not given).

  Demodulated data when the number of codes used in this embodiment is N = 2 is obtained by the following procedure.

(1) The output signal P ₁ from the P ₁ computer is set to the maximum value of the window W of the first correlator output,
(2) The output signal P ₂ from the P ₂ computer is set to the maximum value of the window W of the second correlator output,
(3) The output signal A ₁ from the A ₁ computer is set as the integrated value (added value) of the end E of the first correlator output,
(4) when the output signal A ₂ from A ₂ computer integrated value of the second correlator output end E with (added value),
[Equation 4]
P ₂ · A ₁ > P ₁ · A ₂ (4)
If so, the judgment output data from the comparator 117 is “1”.
[Equation 5]
P ₂ · A ₁ <P ₁ · A ₂ (5)
If so, the determination output data is “0”.

In this method, the correlation signals peak values P ₁ and P ₂ are multiplied by two signals A ₂ and A ₁ each obtained by adding a correlation value from a position shifted by d / 2 from the multiplication timing. A comparison is made. When the correlation output signal P ₁ has a peak, A ₁ <A ₂ is satisfied, and thus good performance is obtained. Since the correlation characteristics differ depending on the code set used, when the correlation output signal P ₁ described here is a peak, the relationship of A ₁ <A ₂ is not necessarily established. When the timings do not match, the sum of the cross-correlations with the code transmitted before or after the code to be determined is used, so that the performance is greatly deteriorated depending on the situation. In synchronization detection, only the magnitudes are compared, and here, comparison is made by multiplying the sum of the correlation value and the side lobe. As described above, multiplying the sum of the side lobes does not necessarily achieve good performance, and depending on the code used and the communication environment, it may cause a deterioration in performance. there were.

  An object of the present invention is to provide an asynchronous code modulation signal receiving apparatus that solves the above-described problems and has a simple configuration as compared with the prior art and can decode an asynchronous code modulation signal more accurately. It is in.

An asynchronous code modulation signal receiving apparatus according to the present invention receives and decodes a code modulation signal, which is code-modulated according to a data signal, as a reception signal using a predetermined code modulation method using a plurality of predetermined codes. In the asynchronous code modulation signal receiving device,
Converting means for converting the received signal received into two signals substantially orthogonal to each other;
A correlator that multiplies the two signals converted by the conversion means after multiplying the plurality of codes and adds them, and calculates the likelihood of the correlation value with the plurality of codes based on the output value signal of the addition result Means,
Synchronization determining means for determining and outputting a decoded data signal by determining the sign and synchronization point of the received signal based on the likelihood of the correlation value calculated by the correlator means. Features.

In the asynchronous code modulation signal receiving apparatus, the correlator means calculates the likelihood of correlation values with the plurality of codes based on an input clock,
The synchronization determination unit detects a synchronization point based on the likelihood calculated by the correlator unit and the received signal, and verifies whether the detected synchronization point is accurate based on the received signal. A delay locked loop circuit that outputs a data signal by decoding at the synchronization point by adjusting the generation timing of the clock based on the received signal when it is determined to be accurate .

  Further, in the asynchronous code modulation signal receiving apparatus, the likelihood of the correlation value is based on output value signals of adjacent symbol intervals, and the likelihood at a predetermined time point is assumed to be a predetermined random variable. Based on the likelihood and the probability of occurrence of the code when it is assumed that the information bits of the code are independent, this is the likelihood of the correlation value calculated in consideration of the determination prior probability. Instead, in the asynchronous code modulation signal receiving apparatus, the likelihood of the correlation value is based on output value signals of adjacent symbol intervals, and the likelihood at a predetermined time point is assumed to be a predetermined random variable. It is the likelihood of the correlation value calculated in consideration of self and cross-correlation based on the likelihood when the code information is assumed and the occurrence probability of the code when it is assumed that the information bits of the code are independent. And Further, in the asynchronous code modulation signal receiving apparatus, the likelihood of the correlation value is a predetermined maximum likelihood sequence estimation related to a time point and a code based on an output value signal of a code sequence at a plurality of time points adjacent to each other. It is the likelihood of the correlation value calculated using the likelihood function.

  According to the asynchronous code modulation signal receiving apparatus according to the present invention, the converted two signals are multiplied by the plurality of codes and then added, and based on the output value signal of the addition result, Since the likelihood of the correlation value is calculated, and the decoded data signal is determined and output by determining the code and the synchronization point of the received signal based on the calculated likelihood of the correlation value. This is simpler than the prior art, and has a specific effect that it can be determined and decoded more accurately.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  In the embodiment according to the present invention, focusing on the characteristics of a communication system using asynchronous code modulation (Non-Coherent Code Shift Keying), signal synchronization acquisition and data determination usually performed in different circuits and processes are collectively performed. Providing a communication system that improves the reliability of received data, and that synchronization supplementation and data determination can be realized with the same circuit configuration, and a communication system, data, and synchronization point determination method with reduced system complexity is doing. A signal used in communication generally has an in-phase component and a quadrature component, and the phases do not match between the receiver and the transmitter. In the synchronous communication system, the receiver needs to correct this phase by some method, but in the asynchronous communication, it is not necessary to correct this phase. The embodiment according to the present invention relates to a code modulation receiver that belongs to the latter and does not require a phase of an in-phase signal and a quadrature signal.

First embodiment.
FIG. 1 is a block diagram showing a configuration of an asynchronous code modulation signal receiving apparatus according to the first embodiment of the present invention. In FIG. 1, the asynchronous code modulation signal receiving apparatus according to the first embodiment includes an antenna 1, a low noise amplifier (LNA) 2, an orthogonal signal frequency conversion circuit 20, two A / D converters 6a, 6b, a signal processor 9, a digital correlator 10, and a synchronization determiner 11. Here, the orthogonal signal frequency conversion circuit 20 includes a signal distributor 2, two mixers 4 a and 4 b, a local oscillator 7, a π / 2 phase shifter 8, and two low-pass filters (LPF). ) 5a and 5b.

In FIG. 1, a code modulation signal that is CSK code modulated by, for example, spread spectrum using a plurality of N PN code sequences generated by the code modulation device of FIG. ) Is received by the asynchronous code modulation signal receiving apparatus. In code modulation on the transmitter side, information bits are mapped to a code composed of a plurality of symbols, subjected to processing such as frequency shift and filtering, and then transmitted wirelessly. In asynchronous code modulation, a code vector c _i of length N _l used in the transmitter is expressed by [Equation 6].
c _i = (c _{i, 1} , c _{i, 2} ,..., c _{i, Nl} ), (1 ≦ i ≦ N _l ) (6)
Then, in the code vector c _i ′,
[Equation 7]
c _i '≠ c _i · exp (jθ), ∀ _{i', i} (i '≠ i) (7)
Must be met.

  The radio reception signal received via the communication path is multiplied by a sine wave signal having the same carrier frequency as that used in the transmitter by the mixers 4a and 4b, and processed by the low-pass filters 5a and 5b. After that, the original baseband band is converted to a baseband signal. The received signal has an in-phase component of the I channel signal and a quadrature component of the Q channel signal, and both are input to the digital correlator 10 via the signal processor 9. In FIG. 1, the radio reception signal received by the antenna 1 is input to the signal distributor 3 through the low noise amplifier 2 and divided into two, while one radio reception signal is input to the mixer 4a. The other radio reception signal is input to the mixer 4b. Here, the mixers 4a and 4b are constituted by multipliers. On the other hand, the local oscillator generates a local oscillation signal having substantially the same frequency as the carrier frequency of the radio reception signal and outputs the local oscillation signal to the mixer 4a, and also to the mixer 4b via the π / 2 phase shifter 8. Output. The mixer 4a mixes and multiplies two input signals, and outputs a mixed result signal to the A / D converter 6a via the low-pass filter 5a, and the mixer 4b receives the two input signals. Are mixed and multiplied, and the resulting signal is output to the A / D converter 6b via the low-pass filter 5b. As a result, the radio reception signal is converted into two baseband signals orthogonal to each other by the orthogonal signal frequency conversion circuit 20, and then A / D converted by the A / D converters 6a and 6b, respectively, to obtain a signal as a discrete digital signal. It is output to the processor 9.

  For example, when the communication apparatus uses the OFDM system, the signal processor 9 is a fast Fourier transform circuit, and when the communication apparatus uses a Hadamard code, for example, the CDMA system, the signal processor 9 is a high-speed inverse Walsh transform circuit. In addition to these, in order to reduce the influence of the communication path, the signal processor 9 is composed of a signal equalization circuit and the like. The signal processor 9 performs predetermined signal processing on the input baseband signal and outputs the baseband signal after the signal processing to the digital correlator 10. The digital correlator 10 calculates a correlation value between the baseband signal of the in-phase component and the quadrature component and a code used in the transmitter, and calculates and outputs a square of them. That is, the digital correlator 10 calculates the same number of correlation values as the codes used for transmission, and outputs them to the synchronization determiner 11 in parallel at predetermined time intervals. The synchronization determiner 11 stores the output value from the digital correlator 10 for a predetermined period of time, determines a synchronization point and a transmission code according to a predetermined synchronization determination method described in detail later, and outputs the determined digital data signal to the output terminal T1. Output via.

  Next, four synchronization determination methods that can be used in the synchronization determiner 11 will be described below.

(1) First synchronization determination method: a synchronization determination method considering a determination prior probability.
In the symbol section immediately before the symbol section that is currently determined (referred to as the symbol section to be processed, hereinafter referred to as the processing symbol section), the synchronization point n _p at the determined sample time and the code m at that time are stored. . The likelihood p (n) of the sample time point n is calculated based on the sample time point n determined in the processing symbol interval and the synchronization point n _p determined as the synchronization point in the previous symbol interval. Here, the likelihood p (n) of the sampling time point n is expressed by the following expression, for example, assuming that the clock timing shift is a random variable that follows a Gaussian distribution.

Here, σ _s ² is a variance value of the code reproduction clock timing deviation, T _s is a sampling time interval, T is a code duration, and n _p is a time point determined as a synchronization point in the previous symbol interval. To express. Further, the occurrence probability p (m) of the code is calculated as follows. That is, the occurrence probability p (m) of a code is expressed by the following expression in a system using M codes, assuming that input information bits are independent.

Further, the likelihood p (y _{m, n} | m, n) at the sample time point _n for determining the output value ym _{, n} output from the digital correlator 10 is expressed as follows when the code is a predetermined known code: This is the probability of outputting the output value ym _{, n} at the sampling time n with the code m, and can be expressed and calculated in advance by a predetermined function as in the following equation. A specific example of the third synchronization determination method will be described later in detail.

[Equation 8]
p (y _{m, n} | m, n) = f (y _{m, n} , m, n) (10)

In the first synchronization determination method, the likelihood p (y _{m, n} | m, n) p (m) p (n) at the sample time point _n for determining the output value ym _{, n} is calculated for each code. By comparing them, a code having the maximum likelihood p (y _{m, n} | m, n) p (m) p (n) is set as a transmission code, and a sample determination time point n of the transmission code is set as a synchronization point. judge.

(2) Second synchronization determination method: a synchronization determination method considering prior probabilities.
The determined synchronization point n _p and the code m at that time are stored in the symbol section immediately before the processing symbol section. Similar to the first synchronization determination method, the likelihood p (n) of the sample time point n and the occurrence probability p (m) of the code are calculated, and a plurality of codes m _i output from the digital correlator 10 are calculated. Like the first synchronization determination method _{, the} likelihood p (y _{mi, nj} | m, n) based on the sample time point n for determining the plurality of output values y _{mi, nj} in all combinations of the sample time point and the plurality of sample time points n _j is the same as in the first synchronization determination method. To calculate. In the second synchronization determination method, the likelihood П _{i, j} {p (y _{mi, nj} | m, n) p (m) p (n)} at the sample time point _n for determining the output value _ym , n (here , П _{i, j} represents the total product of all combinations of i and j with respect to the argument.) Is calculated for each code, and the maximum likelihood П _{i, j} {p A code having (y _{mi, nj} | m, n) p (m) p (n)} is set as a transmission code, and a sample determination time point n of the transmission code is determined as a synchronization point.

(3) Third synchronization determination method: determination considering auto and cross-correlation.
The determined synchronization point n _p and the code m at that time are stored in the symbol section immediately before the processing symbol section. Similar to the first synchronization determination method, the likelihood p (n) of the sample time point n and the occurrence probability p (m) of the code are calculated, and the code m output from the digital correlator 10 and the sample time point n are calculated. The likelihood p (y _{m, n} | m, n) at the sample time point _n for determining the output value y _{m, n} at and is calculated in the same manner as in the first synchronization determination method. Also, at a sample time point n ′ to be compared different from the sample time point n (for example, a sample time point one code length before and a sample time point two or three code lengths ago), the sample time point n ′. Sample time for calculating the output value y _{m ′, n ′} of the code m ′ output from the digital correlator 10 while calculating the likelihood p (n ′) and the occurrence probability p (m ′) of the code Likelihood p by n (y _{m ′, n ′} | m, n) is calculated in the same manner.

Then, when it is 'code m in' synchronization point n, the output value for sample period n is _{y m,} a _n likelihood _{p (y m,} n | m ', n'), and in synchronization point n After calculating the likelihood p (y _{m ′, n ′} | m, n) that the output value at the sampling time point n ′ becomes y _{m ′, n ′} when the code is m, the two likelihoods of the following equations are calculated. Calculate

[Equation 9]
p (y _{m, n} | m, n) p (y _{m ′, n ′} | m, n) p (m) p (n) (11)
[Equation 10]
p (y _{m, n} | m ′, n ′) p (y _{m ′, n ′} | m ′, n ′) p (m ′) p (n ′)
(12)

  The two likelihoods are compared and the larger one is selected. By repeating this comparison with a plurality of combinations (combination of synchronization point and code), the code having the maximum likelihood and the time point are determined as the transmission code and the synchronization point, respectively.

Hereinafter, a specific example of the likelihood function of the likelihood p (ym _{, n} | m ′, n ′) will be described. For example, in the receiving apparatus that squares and adds each of the in-phase component and the quadrature component of the received signal, the output value y _{m, n} from the digital correlator 10 follows the χ ² distribution and the likelihood p (y _{m, n} | M ′, n ′) is expressed by the following equation.

ここで、

here,

Also, σ ² is the noise variance, and the correlation function R (•) is expressed by the following equation.

Here, N _s represents the number of sample points in one code, and a represents the amplitude of the received signal.

(4) Fourth synchronization determination method: determination method using maximum likelihood sequence estimation.
First, each time interval output value ym _{, n} corresponding to a plurality of codes is stored. From the digital correlator 10 when the code vector m = (m ₁ , m ₂ , m ₃ ,..., _{M N} ) in the synchronization point vector n = (n ₁ , n ₂ , n ₃ ,..., _{N N} ), respectively. Likelihood p (y | m, n) is calculated such that the output value y of In the synchronization determination method, the output value vector y, the synchronization point vector n, and the code vector m are each a vector having a plurality of elements, and the output value vector y ′, the synchronization point vector n ′, and the code vector m ′ are also respectively. A vector having a plurality of elements.

Next, the synchronization vector n ′ = (n ₁ ^′ , n ₂ ^′ , n ₃ ^′ ,..., _{N N} ^′ ) to be compared and the code vector m ′ = (m ₁ ^′ , m ₂ ^′ , m ₃ ^′ ,. When m _N ^′ ), the likelihood p (y | m, n) is calculated so that the output value vector y ′ becomes the following equation.

  Then, when the code vector is m at the synchronization point vector n, the likelihood p (y ′ | m, n) that the output value vector of the code vector m ′ becomes y ′ at the sampling time n ′, and the synchronization point vector n When 'is a code vector m', the likelihood p (y | m ', n') is calculated such that the output value vector of the code vector m is y at the synchronization point vector n. These two likelihoods p (y | m, n) p (y '| m, n) p (m) p (n), p (y | m', n ') p (y' | m ', n ') P (m') p (n ') is compared and selected with greater likelihood, and this is repeated in multiple combinations (referring to multiple combinations of syncpoint vectors and code vectors). The synchronization point vector having the maximum likelihood and the code vector are determined as a synchronization point vector and a transmission code vector (corresponding to transmission code sequences corresponding to a plurality of transmission codes) to be output, respectively.

  The likelihood function p (y | m ′, n ′) used for code sequence estimation is expressed by the following equation.

Here, the likelihood _p in the formula _{(21) (y mi, ni} | m i ', n i') (i = 1,2, ..., N) is expressed by the following equation.

Here, the correlation function _{R (m i, m i '} , n i -n i') is expressed by the following equation.

[Equation 11]
_{R (m i, m 'i} , n i -n' i)
= R (m _i , m ′ _i , n _i −n ′ _i ) + R (m ′ _i−1 , m _i , N _s − (n _i −n ′ _i ))
When n _i −n ′ _i ≧ 0 = R (m _i , m ′ _i , n _i −n ′ _i ) + R (m _i , m ′ _{i + 1} , N _s + (n _i −n ′ _i ))
When n _i −n ′ _i <0 (23)

  Therefore, the likelihood p (n) of the synchronization point vector n is expressed by the following equation.

[Equation 12]
p (n)
= P (n _N , n _N−1 ,..., N ₁ )
= P (n _N | n _N−1 ,..., N ₁ ) p (n _N−1 ,..., N ₁ )
= P (n _N | n _N−1 ,..., N ₁ ) p (n _N−1 | n _N−2 ,..., N ₁ )
p (n _N−2 | n _N−3 ,..., n ₁ )... p (n ₂ | n ₁ ) p (n ₁ ) (24)

In the above specific example, the likelihood function using the function of χ ² distribution is shown, but the present invention is not limited to this, and the likelihood function may be calculated using a predetermined mathematical approximation formula. Good. Further, a predetermined likelihood function (for example, Equation (10)) may be determined in advance according to the code modulation method.

  According to the asynchronous code modulation signal receiving apparatus according to the first embodiment configured as described above, the digital correlator 10 generates a predetermined likelihood based on the code of the code modulation scheme used on the transmission side for the received signal. Since the calculation and the determination of the code and the synchronization point are performed by the synchronization determiner 11 based on the calculated likelihood, it is simpler than the prior art, and more accurately determined and decoded. It has a unique effect that it can.

Second embodiment.
FIG. 2 is a block diagram showing a configuration of an asynchronous code modulation signal receiving apparatus according to the second embodiment of the present invention, and FIG. 3 is a block diagram showing a detailed configuration of the digital IQ matched filter bank circuit 30 of FIG. 4 is a block diagram showing a detailed configuration of the IQ matched filter circuit 31-m in FIG. The asynchronous code modulation signal receiving apparatus according to the second embodiment includes a digital IQ matched filter bank circuit 30 instead of the signal processor 9 and the digital correlator 10 as compared with the first embodiment of FIG. Instead of the synchronization determiner 11, a synchronization determiner 11A is provided.

  In FIG. 2, two orthogonal baseband signals are converted into discrete digital baseband signals by A / D converters 6a and 6b, respectively, and then input to the digital IQ matched filter bank circuit 30. As shown in FIG. 3, the digital IQ matched filter bank circuit 30 includes a plurality of M IQ matched filter circuits 31-m (m = 1, 2,..., M). -M each includes a matched filter that matches the same code used by the transmitter. In a communication system that transmits information using M codes, the discrete digital baseband signals that are orthogonal to each other and input to the digital IQ matched filter bank circuit 30 are branched into M branches, respectively. Is output after passing through an IQ matched filter circuit 31-m including a matched filter corresponding to.

  In FIG. 4, the m-th IQ matched filter circuit 31-m is configured to include matched filters 32 a and 32 b with a sign Cm, square calculators 33 a and 33 b, and an adder 34. Discrete digital baseband signals, which are in-phase component (I channel) and quadrature component (Q channel) sample signals, are input via input terminals T2-1 and T2-2, respectively, and a matched filter 32a corresponding to the mth code. , 32b and the signals after passing through are squared by the square calculators 33a, 33b, respectively, and then added by the adder 34. The adder 34 adds the two input signals and outputs the addition result signal via the output terminal T3.

As shown in FIG. 3, since M IQ matched filter circuits 31-m are prepared and processed in parallel, an output signal from the digital IQ matched filter bank circuit 30 is output as an output terminal T3- 1 to T3-M and output to the synchronization determination unit 11A. The synchronization determiner 11A accumulates the output signal from the digital IQ matched filter bank circuit 30 for a predetermined time interval corresponding to one code, and an output value y _m corresponding to the mth code nth sample time point. _{, N} are compared, the code of the maximum output value is determined as the transmission code, the sampling time is determined as the synchronization point, and the binary data signal corresponding to the determination result is restored and output via the output terminal T1. Output.

According to the asynchronous code modulation signal receiving apparatus according to the second embodiment configured as described above, the IQ matched filter circuit 31- corresponding to a plurality of codes provided in the digital IQ matched filter bank circuit 30 of FIG. 1 to 31-M is used to determine whether or not the code of the code modulation scheme used on the transmission side is matched, and the output value ym _{, n} of the determination result is compared by the synchronization determination unit 11A. Since the code of the maximum output value is determined as the transmission code and the sampling time is determined as the synchronization point, and the binary data signal corresponding to the determination result is restored, it is simpler than in the prior art. In addition, it has a specific effect that it can be determined and decoded more accurately.

Third embodiment.
FIG. 5 is a block diagram showing a configuration of an asynchronous code modulation signal receiving apparatus according to the third embodiment of the present invention. As compared with the second embodiment of FIG. 2, the asynchronous code modulation signal receiving apparatus according to the third embodiment has a shift register 12a, 12b and an inverse Walsh converter (after the A / D converters 6a, 6b). IWT) 13a and 13b are added. Hereinafter, differences from the second embodiment will be described in detail.

  The asynchronous code modulation signal receiving apparatus in FIG. 5 is a communication apparatus using, for example, a CDMA system. In FIG. 5, an I channel signal, which is a discrete digital baseband signal output from the A / D converter 6a, is input to the shift register 12a and subjected to signal processing such as parallel / serial conversion, and then reverse Walsh. Input to the converter 13a. The inverse Walsh transformer 13 a performs a known inverse Walsh transform process on the input parallel baseband signal and then outputs the result to the digital correlator 10. The Q channel signal, which is a discrete digital baseband signal output from the A / D converter 6b, is input to the shift register 12b and subjected to signal processing such as parallel / serial conversion, and then an inverse Walsh converter. 13b. The inverse Walsh transformer 13b performs a known inverse Walsh transform process on the input parallel baseband signal, and then outputs it to the digital correlator 10A.

  For example, the digital correlator 10A has the configuration shown in FIG. In FIG. 6, the digital correlator 10 </ b> A includes two P / S converters 14 a and 14 b and a digital IQ matched filter bank circuit 30. In FIG. 6, the I channel signal inversely Walsh converted by the inverse Walsh converter 13a is P / S converted by the P / S converter 14a, and then input to the digital IQ matched filter bank circuit 30. The Q channel signal subjected to inverse Walsh conversion by the converter 13b is P / S converted by the P / S converter 14b and then input to the digital IQ matched filter bank circuit 30. The digital IQ matched filter bank circuit 30 operates in the same manner as in FIG. 2 and outputs the processed parallel signal to the synchronization determiner 11A. Then, similarly to the second embodiment, the synchronization determiner 11A determines a transmission code and a synchronization point, and outputs a binary data signal whose determination result is restored.

  According to the asynchronous code modulation signal receiving apparatus according to the third embodiment configured as described above, the digital correlator 10A and the synchronization determiner 11A including the digital IQ matched filter bank circuit 30 of FIG. 6 are used. Since the binary data signal having the determination result restored is obtained by determining the transmission code and the synchronization point, it is simpler than the prior art and can be more accurately determined and decoded. It has a specific effect.

Fourth embodiment.
FIG. 7 is a block diagram showing a configuration of an asynchronous code modulation signal receiving apparatus according to the fourth embodiment of the present invention. The asynchronous code modulation signal receiving apparatus according to the fourth embodiment includes a fast Fourier transformer 9A instead of the inverse Walsh transformers 13a and 13b, as compared with the third embodiment of FIG. It is said. The asynchronous code modulation signal receiving apparatus of FIG. 7 according to the present embodiment is a communication apparatus using, for example, an OFDM system, and after performing fast Fourier transform on parallel baseband signals from the shift registers 12a and 12b, digital correlation is performed for each band. 10A is executed, and the transmission code and the synchronization point are detected as in the second and third embodiments. Therefore, according to the asynchronous code modulation signal receiving apparatus according to the fourth embodiment, as in the second and third embodiments, it is simpler than the prior art, and more accurately determined and decoded. It has a specific effect that it can be made.

Fifth embodiment.
FIG. 8 is a block diagram showing a configuration of an asynchronous code modulation signal receiving apparatus according to the fifth embodiment of the present invention, and FIG. 9 is a block diagram showing a configuration of the DLL circuit 23 of FIG. In FIG. 8, the asynchronous code modulation signal receiving apparatus according to the fifth embodiment includes an antenna 1, a low noise amplifier 2, an orthogonal signal frequency conversion circuit 20, an analog correlator 22A, a DLL circuit 23, and a logic circuit. 24. It is characterized by comprising.

  In FIG. 8, the I-channel baseband signal output from the low-pass filter 5a of the orthogonal signal frequency conversion circuit 20 and the Q-channel baseband signal output from the low-pass filter 5b are input to the analog correlator 22A. The The radio reception signal distributed by the signal distributor 3 is input to the DLL circuit 23. The analog correlator 22A calculates a correlation value representing the likelihood of all the codes used in the transmitter for the input baseband signal, and then sends the correlation value signal representing the correlation value to the logic circuit 24. Output. The logic circuit 24 stores the correlation value signal for each code from the analog correlator 22A for a predetermined time, selects a correlation value signal having the maximum correlation value among them, and sets the correlation value as a predetermined threshold value. It is determined that the synchronization point has been detected when the comparison is greater than the threshold value. When the synchronization point is detected, the process proceeds to the confirmation mode, and the accuracy of the interval synchronization point of a certain number of codes is verified. If synchronization cannot be established by this verification, the synchronization point is calculated from the output of the correlation value signal. If the verification is correct, the data circuit is determined in the logic circuit 24 and, at the same time, the clock timing is adjusted by the DLL circuit 23. In the asynchronous code modulation method, the DLL circuit 23 does not require phase synchronization. An asynchronous DLL circuit used in a spread spectrum communication system using only one code is disclosed in Non-Patent Document 1, for example, and is well known.

  In FIG. 9, a DLL circuit 23 includes a plurality of M signal processing circuits 41-m (m = 1, 2,..., M), an adder 42, a loop filter 43 that is a low-pass filter, and voltage control. A VCC generator 44 that generates a clock (hereinafter referred to as VCC) and a code generator 40 are provided. Here, each signal processing circuit 41-m includes mixers 45a and 45b that are multipliers, bandpass filters 46a and 46b that perform bandpass filtering of only a predetermined carrier component, and envelope detectors 47a and 47b. The subtractor 48 and the switch circuit 49 are provided. The radio reception signal from the signal distributor 3 of the orthogonal signal frequency conversion circuit 20 is input to each signal processing circuit 41-m via the input terminal T4. In each signal processing circuit 41-m, a plurality of M codes Cm (m = 1, 2,..., M) generated by the code generator 40 with respect to the radio reception signal (for example, in the spread spectrum modulation method, PN code), which is obtained by multiplying each of the two code signals shifted by a predetermined time interval Δ from each other and detecting the envelope curve, based on the code selection signal from the logic circuit 24, One of the M signals output from the signal processing circuit 41-m is selected by the switch circuit 49 and output to the VCC generator 44 via the adder 42 and the loop filter 43, It is used as a reference signal for generating VCC. A plurality of M codes generated by the code generator 40 are output to the analog correlator 22A.

  Since the asynchronous code modulation signal receiving apparatus configured as described above uses envelope detectors 47a and 47b, phase synchronization is not required. As a result, in order to adjust the clock timing, in the DLL circuit 23, if the codes to be multiplied are synchronized, the output signals from the two band-pass filters 46a and 46b become larger values, but the synchronization is achieved. If not, these values will be smaller. The timing of the spreading code to be multiplied is shifted by a predetermined time interval Δ, the difference between the output signals is calculated by the subtractor 48, and the clock timing is adjusted from this output signal using the loop filter 43 and the VCC generator 44. The spread code is generated by the code generator 40. The generated spreading code is input to the analog correlator 22A, and data is determined in the logic circuit 24 based on the obtained output signal.

  According to the asynchronous code modulation signal receiving apparatus according to the fifth embodiment configured as described above, the transmission code and the synchronization point are determined using the analog correlator 22A, the logic circuit 24, and the DLL circuit 23. Since the binary data signal with the restored determination result is obtained, it is simpler than the prior art, and has a specific effect that it can be determined and decoded more accurately.

Sixth embodiment.
FIG. 10 is a block diagram showing the configuration of an asynchronous code modulation signal receiving apparatus according to the sixth embodiment of the present invention, and FIG. 11 is a block diagram showing the configuration of the DLL circuit 23A of FIG. As compared with the fifth embodiment of FIG. 8, the asynchronous code modulation signal receiving apparatus of the sixth embodiment replaces the DLL circuit 23 using the envelope detectors 47a and 47b with CCD correlators 52a, 52b, A DLL circuit 23A using 53a and 53b is provided. As a signal processing signal of the DLL circuit 23A, an orthogonal baseband signal (an I-channel baseband signal and a Q-channel baseband signal) from the low-pass filters 5a and 5b is used. ) Is used as a quadrature baseband signal distributed by the signal distributors 21a and 12b. Hereinafter, the configuration and operation of the DLL circuit 23A will be described.

  11, a DLL circuit 23A includes a plurality of M signal processing circuits 51-m (m = 1, 2,..., M), an adder 59, a loop filter 43, a VCC generator 60, a PN code, and the like. And generators 61 and 62. Here, each signal processing circuit 51-m includes four CCD correlators 52a, 52b, 53a, 53b disclosed in Non-Patent Document 2 and configured using charge-coupled devices (CCDs), respectively, and a square operation. Units 54a, 54b, 55a, 55b, adders 56, 57, and a subtractor 58. The PN code generators 61 and 62 generate PN codes which are different from each other by a time interval Δ based on the VCC generated by the VCC generator 60 and are specified by the logic circuit 24, respectively. It outputs to 52a, 53a and 53a, 53b. The VCC generator 60 outputs VCC to the analog correlator 22A.

  Since the asynchronous code modulation signal receiving apparatus configured as described above uses the CCD correlators 52a, 52b, 53a, and 53b, phase synchronization is not required. Thus, in order to adjust the clock timing, if the code to be multiplied is synchronized in the DLL circuit 23A, the orthogonal baseband signals from the signal distributors 21a and 21b become larger values, but are synchronized. Otherwise, these values will be smaller. The timing of the spreading code to be multiplied is shifted by a predetermined time interval Δ, the difference between the output signals is calculated by the subtractor 58, and the clock timing is adjusted from this output signal using the loop filter 43 and the VCC generator 60. The PN code is generated by the code generators 61 and 62. The generated spreading code is input to the analog correlator 22A, and data is determined in the logic circuit 24 based on the obtained output signal.

  According to the asynchronous code modulation signal receiving apparatus according to the sixth embodiment configured as described above, the transmission code and the synchronization point are determined using the analog correlator 22A, the logic circuit 24, and the DLL circuit 23A. Since the binary data signal with the restored determination result is obtained, it is simpler than the prior art, and has a specific effect that it can be determined and decoded more accurately.

Seventh embodiment.
FIG. 12 is a block diagram showing a configuration of an asynchronous code modulation signal receiving apparatus according to the seventh embodiment of the present invention. The asynchronous code modulation signal receiving apparatus according to the seventh embodiment differs from the fifth embodiment of FIG. 8 in the following points.
(1) A digital correlator 22 is provided instead of the analog correlator 22A.
(2) Instead of the analog DLL circuit 23, a digital DLL circuit 23B is provided.
(3) An A / D converter 6c for A / D converting the radio reception signal from the signal distributor 3 and outputting it to the DLL circuit 23B is provided.

  In the asynchronous code modulation signal receiving apparatus according to the seventh embodiment configured as described above, the operations of the correlator and the DLL circuit are digitalized as compared with the fifth embodiment of FIG. The processing operation is the same. Therefore, since the digital correlator 22, the logic circuit 24, and the DLL circuit 23B are used to determine the transmission code and the synchronization point and obtain the binary data signal whose determination result is restored, the conventional technique is used. Compared to the above, the present invention has a unique effect that it is simpler and can be more accurately determined and decoded.

Eighth embodiment.
FIG. 13 is a block diagram showing a configuration of an asynchronous code modulation signal receiving apparatus according to the eighth embodiment of the present invention. The asynchronous code modulation signal receiving apparatus according to the eighth embodiment differs from the sixth embodiment of FIG. 10 in the following points.
(1) A digital correlator 22 is provided instead of the analog correlator 22A.
(2) A digital DLL circuit 23C is provided instead of the analog DLL circuit 23A.
(3) An A / D converter 6a is inserted between the low-pass filter 5a and the signal distributor 21a, and an A / D converter 6b is inserted between the low-pass filter 5b and the signal distributor 21b. .

  In the asynchronous code modulation signal receiving apparatus according to the eighth embodiment configured as described above, the operations of the correlator and the DLL circuit are digitally processed as compared with the sixth embodiment of FIG. The processing operation is the same. Therefore, since the digital correlator 22, the logic circuit 24, and the DLL circuit 23C are used to determine the transmission code and the synchronization point and obtain the binary data signal whose determination result is restored, the conventional technique is used. Compared to the above, the present invention has a unique effect that it is simpler and can be more accurately determined and decoded.

Modified example.
In the fifth to eighth embodiments described above, the asynchronous code modulation signal receiving apparatus using the DLL circuit has been described. However, the processing of the digital correlator and the analog correlator is described in the first to fourth embodiments. You may apply the synchronization determination method in a form.

  As described above in detail, according to the asynchronous code modulation signal receiving apparatus according to the present invention, the converted two signals are multiplied by the plurality of codes and then added, and based on the output value signal of the addition result. Calculating a likelihood of a correlation value with the plurality of codes, and determining a decoded data signal by determining a code and a synchronization point of the received signal based on the calculated likelihood of the correlation value Since it is configured to output, it is simpler than the prior art, and can be determined and decoded more accurately.

It is a block diagram which shows the structure of the asynchronous code modulation signal receiver which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the asynchronous code modulation signal receiver which concerns on the 2nd Embodiment of this invention. FIG. 3 is a block diagram showing a detailed configuration of a digital IQ matched filter bank circuit 30 in FIG. 2. FIG. 4 is a block diagram illustrating a detailed configuration of an IQ matched filter circuit 31-m in FIG. 3. It is a block diagram which shows the structure of the asynchronous code modulation signal receiver which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the digital correlator 10 of FIG. It is a block diagram which shows the structure of the asynchronous code modulation signal receiver which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the asynchronous code modulation signal receiver which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the structure of the DLL circuit 23 of FIG. It is a block diagram which shows the structure of the asynchronous code modulation signal receiver which concerns on the 6th Embodiment of this invention. FIG. 11 is a block diagram showing a configuration of a DLL circuit 23A of FIG. It is a block diagram which shows the structure of the asynchronous code modulation signal receiver which concerns on the 7th Embodiment of this invention. It is a block diagram which shows the structure of the asynchronous code modulation signal receiver which concerns on the 8th Embodiment of this invention. It is a block diagram which shows the structure of the code modulation apparatus which concerns on the prior art disclosed in patent document 1. FIG. It is a block diagram which shows the structure of the code modulation signal receiver which concerns on the prior art disclosed in patent document 1. FIG. It is a block diagram which shows the structure of the correlator 74 of FIG. FIG. 16 is a block diagram showing a configuration of a correlator 74A using a logic circuit that is a modification of the correlator 74 of FIG. 15; It is a block diagram which shows the structure of the demodulator 76 of FIG. It is a block diagram which shows the structure of the computers 114 and 124 of FIG. It is a block diagram which shows the structure of the computers 113 and 123 of FIG.

Explanation of symbols

1 ... antenna,
2. Low noise amplifier (LNA),
3 ... Signal distributor,
4a, 4b ... mixers,
5a, 5b ... low pass filter (LPF),
6a, 6b ... A / D converter,
7 ... Local oscillator,
8 ... π / 2 phase shifter,
9: Signal processor,
9A: Fast Fourier transform,
10, 10A ... digital correlator,
11, 11A ... synchronization determination unit,
12a, 12b ... shift registers,
13a, 13b ... Inverse Walsh Transformer (IWT),
14a, 14b ... Parallel / serial converter (S / P converter),
20: Orthogonal signal frequency conversion circuit,
21a, 21b ... signal distributors,
22: Digital correlator,
22A ... analog correlator,
23, 23A, 23B, 23C,... DLL circuit,
24. Logic circuit,
30: Digital IQ matched filter bank circuit,
31-1 to 31-M... IQ matched filter circuit,
32a, 32b ... matched filter,
33a, 33b ... square calculator,
34. Adder,
40: Code generator,
41-1 to 41-M ... signal processing circuit,
42 ... adder,
43 ... Loop filter,
44 ... VCC generator,
45a, 45b ... mixers,
46a, 46b ... band pass filters,
47a, 47b envelope detectors,
48 ... adder,
49 ... Switch circuit,
51-1 to 51-M ... signal processing circuit,
52a, 52b, 53a, 53b ... CCD correlator,
54a, 54b, 55a, 55b ... square calculator,
56, 57 ... adder,
58 ... subtractor,
59 ... adder,
60 ... VCC generator,
61, 62 ... PN code generator,
T1 ... output terminal,
T2-1, T2-2 ... input terminals,
T3, T3-1 to T3-M ... output terminals,
T4 ... input terminal,
T5: Output terminal,
T6, T7 ... input terminals,
T8: Output terminal.

Claims (5)

In an asynchronous code modulation signal receiving apparatus that receives and decodes a code modulation signal that is code-modulated according to a data signal as a reception signal, using a predetermined code modulation scheme that uses a plurality of predetermined codes,
Converting means for converting the received signal received into two signals substantially orthogonal to each other;
A correlator that multiplies the two signals converted by the conversion means after multiplying the plurality of codes and adds them, and calculates the likelihood of the correlation value with the plurality of codes based on the output value signal of the addition result Means,
Synchronization determining means for determining and outputting a decoded data signal by determining the sign and synchronization point of the received signal based on the likelihood of the correlation value calculated by the correlator means. Asynchronous code modulation signal receiving apparatus. The correlator means calculates the likelihood of correlation values with the plurality of codes based on the input clock,
The synchronization determination unit detects a synchronization point based on the likelihood calculated by the correlator unit and the received signal, and verifies whether the detected synchronization point is accurate based on the received signal. A delay locked loop circuit that outputs a data signal by decoding at the synchronization point by adjusting the generation timing of the clock based on the received signal when it is determined to be accurate The asynchronous code modulation signal receiving apparatus according to claim 1.   The likelihood of the correlation value is based on the output value signals of adjacent symbol intervals, and the likelihood when the likelihood at a predetermined time is assumed to be a predetermined random variable and the information bits of the code are independent. 3. The asynchronous code-modulated signal receiving apparatus according to claim 1, wherein the likelihood of the correlation value is calculated based on a probability of occurrence of a code when it is assumed that there is a prior determination probability. .   The likelihood of the correlation value is based on the output value signals of adjacent symbol intervals, and the likelihood when the likelihood at a predetermined time is assumed to be a predetermined random variable and the information bits of the code are independent. 3. Asynchronous code modulation signal reception according to claim 1 or 2, wherein the likelihood of the correlation value is calculated based on the occurrence probability of the code when it is assumed to be present, taking into account self and cross-correlation. apparatus. The likelihood of the correlation value is a correlation value calculated using a predetermined maximum likelihood sequence estimation likelihood function for the time and code based on the output signal of the code sequence at a series of adjacent time points. The asynchronous code modulation signal receiving apparatus according to claim 1 or 2, wherein

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