JP7445541B2 - Semiconductor devices and step-down multiphase DC/DC converters - Google Patents

Description

The present disclosure relates to a semiconductor device and a step-down multiphase DC/DC converter.

A step-down multi-phase DC/DC converter, which is a type of step-down DC/DC converter, has multiple output stage circuits that switch the input voltage, and provides a phase difference in the switching of the multiple output stage circuits to drive their switching. By doing so, one stabilized output voltage is obtained.

Japanese Patent Application Publication No. 2015-128345

Although various circuit configurations have been proposed as detailed configurations of step-down multiphase DC/DC converters, there is still room for improvement in terms of power supply characteristics (for example, load response performance or power supply efficiency).

The present disclosure aims to provide a semiconductor device and a step-down multiphase DC/DC converter that contribute to improved characteristics.

A semiconductor device according to the present disclosure is a semiconductor device used in a step-down multi-phase DC/DC converter that steps down an input voltage and generates an output voltage based on a plurality of switch voltages, the semiconductor device switching the input voltage. a plurality of output stage circuits that generate the plurality of switch voltages at a plurality of switch terminals, and an error that generates an error voltage corresponding to the difference between a voltage proportional to a feedback voltage corresponding to the output voltage and a predetermined reference voltage. a voltage generation section; a feedback pulsating voltage generation section that generates a plurality of feedback pulsating voltages that vary in conjunction with the plurality of switch voltages based on the feedback voltage; and the error voltage and the plurality of feedback pulsating currents. an on-timing sequence generation unit that generates an on-timing sequence consisting of a plurality of on-timings based on a voltage; and switching of the plurality of output stage circuits by sequentially driving the plurality of output stage circuits based on the on-timing sequence. This is a configuration (first configuration) including a switching control section that provides a phase difference to drive.

In the semiconductor device according to the first configuration, an output transistor is provided between the input voltage application terminal and the corresponding switch terminal in each output stage circuit, so that a plurality of output transistors are provided in the plurality of output stage circuits. The switching control section has an on-time setting section that sets the on-time of each output transistor, and has a configuration (second configuration).

In the semiconductor device according to the second configuration, the on-timing sequence generating section is configured to generate a plurality of on-timing sequence generators each time the level relationship between the error voltage and the average voltage of the plurality of feedback pulsating voltages changes from a first relationship to a second relationship. The on-timing sequence is generated by setting the on-timing, and the switching control section sequentially turns on the plurality of output transistors one by one at a plurality of consecutive on-timings included in the on-timing sequence. It may be a configuration (third configuration) that repeatedly executes.

In the semiconductor device according to the second or third configuration, the on-time setting section sets the on-period and off-period of the plurality of output transistors based on the setting contents of the on-time of each output transistor and the on-timing sequence. The switching control unit includes a switching drive unit that generates a plurality of specified drive control signals, the switching control unit turns on/off the plurality of output transistors according to the plurality of drive control signals, and the on-time setting unit is configured to control a PLL circuit. A configuration (fourth configuration) in which the on-time of each output transistor is set so that the frequency of the plurality of drive control signals corresponding to the switching frequency of the plurality of output transistors matches or approaches a predetermined reference frequency. It's okay to have one.

In the semiconductor device according to any of the second to fourth configurations, the switching control section includes a current detection section that detects a plurality of target currents flowing through the plurality of switch terminals, and a detection result of the current detection section. a current balance signal generation section that generates a current balance signal according to the magnitude relationship of the plurality of target currents based on the current balance signal, and the on-time setting section sets the on-time of each output transistor based on the current balance signal. A configuration (fifth configuration) may be adopted in which the difference between the plurality of target currents is reduced by adjustment.

Regarding the semiconductor device according to the fifth configuration, the plurality of target currents include first and second target currents, and the plurality of output transistors are first output transistors connected to a switch terminal through which the first target current flows. and a second output transistor connected to a switch terminal through which the second target current flows; the on-time of the first output transistor is corrected to decrease while the on-time of the second output transistor is corrected to increase, and when the first target current is smaller than the second target current, based on the current balance signal. A configuration (sixth configuration) may be adopted in which the on-time of the first output transistor is increased and the on-time of the second output transistor is decreased.

Another semiconductor device according to the present disclosure is a semiconductor device used in a step-down multiphase DC/DC converter that steps down an input voltage and generates an output voltage based on the plurality of switch voltages, the semiconductor device A plurality of output stage circuits that generate the plurality of switch voltages at a plurality of switch terminals by switching, and switching drive of the plurality of output stage circuits with a phase difference provided in the switching drive of the plurality of output stage circuits. a switching control unit, wherein an output transistor is provided between the input voltage application terminal and the corresponding switch terminal in each output stage circuit, so that the plurality of output stage circuits are provided with a plurality of output transistors. , the switching control unit includes an on-time setting unit that sets the on-time of each output transistor, a current detection unit that detects a plurality of target currents flowing through the plurality of switch terminals, and a current detection unit that detects a magnitude relationship of the plurality of target currents. a current balance signal generation unit that generates a current balance signal according to the current balance signal, and the on-time setting unit adjusts the on-time of each output transistor based on the current balance signal to adjust the current balance between the plurality of target currents. This is a configuration (seventh configuration) that reduces the difference in .

Regarding the semiconductor device according to the seventh configuration, the plurality of target currents include first and second target currents, and the plurality of output transistors are first output transistors connected to a switch terminal through which the first target current flows. and a second output transistor connected to a switch terminal through which the second target current flows; the on-time of the first output transistor is corrected to decrease while the on-time of the second output transistor is corrected to increase, and when the first target current is smaller than the second target current, based on the current balance signal. The on-time of the first output transistor may be corrected to increase while the on-time of the second output transistor is corrected to decrease (eighth configuration).

A step-down multi-phase DC/DC converter according to the present disclosure is provided between the semiconductor device according to any one of the first to eighth configurations, an output terminal to which the output voltage is applied, and the plurality of switch terminals. A step-down multi-phase DC/DC converter, comprising: a plurality of coils; and an output capacitor provided between the output terminal and ground; This is a configuration (ninth configuration) in which the output voltage is generated at the output terminal by rectification and smoothing using a capacitor.

According to the present disclosure, it is possible to provide a semiconductor device and a step-down multiphase DC/DC converter that contribute to improved characteristics.

FIG. 1 is an overall configuration diagram of a DC/DC converter according to a first embodiment of the present disclosure. 2 is a waveform diagram of several currents, voltages, and signals associated with the DC/DC converter of FIG. 1; FIG. FIG. 2 is a diagram showing a configuration example of a pulse wave generation section in FIG. 1. FIG. 2 is a diagram for explaining the function of the PLL circuit in FIG. 1. FIG. 2 is a diagram for explaining the function of the PLL circuit in FIG. 1. FIG. 3 is a waveform diagram of several currents, voltages, and signals in a current unbalanced state according to the first embodiment of the present disclosure; FIG. FIG. 2 is a diagram for explaining the function of a current balance signal generation section in FIG. 1. FIG. FIG. 2 is an overall configuration diagram of a DC/DC converter according to a second embodiment of the present disclosure. FIG. 7 is an external perspective view of a semiconductor device according to a third embodiment of the present disclosure. FIG. 7 is a schematic partial configuration diagram of a step-down three-phase DC/DC converter according to a fifth embodiment of the present disclosure. 11 is a waveform diagram of several signals in the step-down three-phase DC/DC converter of FIG. 10. FIG. FIG. 1 is a block diagram of a semiconductor device according to one aspect of the present disclosure. FIG. 2 is a configuration diagram of a step-down DC/DC converter employing a multi-phase drive method according to a reference configuration.

Examples of embodiments of the present disclosure will be specifically described below with reference to the drawings. In each referenced figure, the same parts are given the same reference numerals, and overlapping explanations regarding the same parts will be omitted in principle. In this specification, for the purpose of simplifying the description, by writing symbols or codes that refer to information, signals, physical quantities, elements, parts, etc., information, signals, physical quantities, elements, parts, etc. that correspond to the symbols or codes are indicated. Names such as names may be omitted or abbreviated. For example, the current balance signal generation section referred to by "210" (see FIG. 1), which will be described later, may be referred to as the current balance signal generation section 210, or may be abbreviated as the generation section 210. , they all refer to the same thing.

First, some terms used in the description of the embodiments of the present disclosure will be explained. The ground refers to a reference conductive portion having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductive part is formed of a conductor such as metal. The potential of 0V is sometimes referred to as a ground potential. In embodiments of the present disclosure, voltages shown without particular reference represent potentials as seen from ground.

Level refers to the level of potential, with a high level having a higher potential than a low level for any signal or voltage of interest. For any signal or voltage of interest, a signal or voltage at a high level means that the signal or voltage level is at a high level, and a signal or voltage at a low level means that a signal or voltage level is at a high level. It means that it is at a low level. The level of a signal may be expressed as a signal level, and the level of a voltage may be expressed as a voltage level. Regarding any signal of interest, when the signal is at a high level, the inverted signal of the signal takes a low level, and when the signal is at a low level, the inverted signal of the signal takes a high level.

In any signal or voltage of interest, switching from a low level to a high level is called an up edge, and the timing of switching from a low level to a high level is called an up edge timing. Similarly, in any given signal or voltage of interest, switching from a high level to a low level is called a down edge, and the timing of switching from a high level to a low level is called a down edge timing.

Regarding any transistor configured as a FET (field effect transistor) including a MOSFET, an on state refers to a state in which the drain and source of the transistor are electrically connected, and an off state refers to a state in which the drain and source of the transistor are electrically connected. Refers to the state where there is no conduction between the two (blocked state). The same applies to transistors that are not classified as FETs. The MOSFET is understood to be an enhancement type MOSFET unless otherwise specified. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor."

Hereinafter, the on state and off state of any transistor may be simply expressed as on and off. For any transistor, switching from an off state to an on state is expressed as turn-on, and switching from an on state to an off state is expressed as turn-off. The timing at which turn-on occurs is referred to as turn-on timing, and the timing at which turn-off occurs is referred to as turn-off timing. Regarding any transistor, a period in which the transistor is in an on state is sometimes referred to as an on period, and a period in which the transistor is in an off state is sometimes referred to as an off period.

Regarding any signal having a signal level of high level or low level, a section where the level of the signal is high level is called a high level section, and a section where the level of the signal is low level is called a low level section. The same applies to any voltage that takes a high or low voltage level.

<<Introduction explanation>>
In a step-down DC/DC converter, the input voltage is switched in an output stage circuit consisting of a series circuit of an output transistor and a synchronous rectifier transistor, and the rectangular voltage obtained by switching is output by rectifying and smoothing it with a coil and a capacitor. Get voltage. This type of step-down DC/DC converter is often required to have high load response performance and miniaturization, and depending on the application, the degree of the requirement is very large.

A constant on-time control method is known as a control method suitable for high load response performance. In the constant on-time control method, when the output transistor is switched and driven, the on-time of the output transistor is kept constant, and the output voltage is stabilized by adjusting the off-time of the output transistor.

On the other hand, in applications where a large current needs to flow through the coil, when there is only one coil, it is necessary to increase the size of the coil due to ratings, heat generation, etc. As the size of the coil increases, the size of the step-down DC/DC converter and the size of the device incorporating the step-down DC/DC converter also increase (that is, it becomes difficult to miniaturize). There is a multi-phase drive method as a drive method that contributes to miniaturization.

In a step-down DC/DC converter that adopts a multi-phase drive method, as shown in FIG. 13, output stage circuits 910 including output transistors 911 are prepared for multiple channels, and the multiple output stage circuits 910 are out of phase. is driven by switching. In the configuration of FIG. 13, since the output stage circuits 910 are provided for two phases, the two output stage circuits 910 are switched and driven with a phase difference of 180°, and the connection between the first and second coils 920 is An output voltage Vo is generated at the node. Since the output current (load current) is shared between the two coils 920 and flows, the magnitude of the current flowing per coil is reduced. Therefore, the size of the coil can be reduced. It is also effective in reducing output ripple.

However, in the configuration of FIG. 13, a so-called current mode control method is adopted, and the load response performance is lower than that of the constant on-time control method. Therefore, conventionally, in applications requiring high load response performance, a step-down DC/DC converter employing a constant on-time control method has generally been selected. Note that, as in the configuration of FIG. 13, control that switches the output transistor (transistor 911 in FIG. 13) using a fixed clock is sometimes referred to as linear control, and control that switches the output transistor using a constant on-time control method is called linear control. This is sometimes called nonlinear control.

If it were possible to combine the constant on-time control method or a similar method with the multi-phase drive method, it would be extremely beneficial to achieve high load response performance and miniaturization at the same time.

However, good characteristics cannot be obtained with a simple parallel configuration in which a plurality of DC/DC converters using a constant on-time control method are provided and they are simply driven in parallel. In a simple parallel configuration, each DC/DC converter turns on/off its own output transistor independently depending on the output voltage, so it is assumed that multiple output transistors will turn on at the same time (i.e., multiple phase drive is not realized). Achieving multi-phase drive requires a technique for ensuring an appropriate phase difference for switching drive of the output stage circuit (hereinafter referred to as a phase difference ensuring technique for convenience).

Furthermore, when performing multi-phase drive, if the magnitude of the current flowing through multiple coils varies (for example, in the configuration shown in FIG. 13, one of the currents flowing through two coils 920 may be large and the other small (in certain situations), the efficiency of the DC/DC converter decreases. For this reason, a technique (hereinafter referred to as a current balancing technique) that makes the magnitude of the current flowing through a plurality of coils uniform is also desired.

<<First embodiment>>
A first embodiment of the present disclosure will be described. FIG. 1 shows the overall configuration of a DC/DC converter 10 according to a first embodiment of the present disclosure. The DC/DC converter 10 is a step-down multi-phase DC/DC converter that realizes both the above-described phase difference securing technology and current balancing technology, and generates an output voltage V _OUT by stepping down the input voltage V _IN .

The input voltage V _IN is a positive DC voltage, and has a voltage value within the range of 4.0V to 18.0V, for example. The output voltage V _OUT is lower than the input voltage V _IN and has a stabilized positive DC voltage value except for the transient state of the DC/DC converter 10. The target value of the output voltage V _OUT (the value of the target voltage V _TG to be described later) has a voltage value within the range of 0.6V to 3.4V, for example.

The DC/DC converter 10 includes an error voltage generation section 110, pulse wave generation sections 120A and 120B, a PWM comparator 130, a phase control logic 140, TON setting sections 150A and 150B, a PLL circuit 160, and an output stage drive. 170A and 170B, output stage circuits 180A and 180B, current sensors 190A and 190B, protection circuits 200A and 200B, current balance signal generation section 210, coils L1 and L2, and output capacitor C _OUT . . Further, the DC/DC converter 10 includes input terminals 251A and 251B, switch terminals 252A and 252B, ground terminals 253A and 253B, and an output terminal 254, as well as each node described below. Note that a single input terminal may be used as the input terminals 251A and 251B, and a single ground terminal may be used as the ground terminals 253A and 253B.

The DC/DC converter 10 includes output stage circuits 180A and 180B for two phases, and performs multi-phase switching by switching and driving the output stage circuits 180A and 180B with a 180° phase difference (or a phase difference close to 180°). Realizes phase drive. One phase in a two-phase multiphase drive is referred to as a first phase, and the other phase is referred to as a second phase. Blocks 150A, 170A, 180A, 190A and 200A are the TON setting section, output stage drive section, output stage circuit, current sensor and protection circuit in the first phase, and blocks 150B, 170B, 180B, 190B and 200B are the TON setting section, output stage drive section, output stage circuit, current sensor and protection circuit in the first phase. These are a TON setting section, an output stage drive section, an output stage circuit, a current sensor, and a protection circuit in two phases.

The characteristic operation of the DC/DC converter 10 will be briefly explained. In the DC/DC converter 10, in order to ensure a phase difference of 180° (or a phase difference close to 180°), the PWM comparator 130 generates a signal COMP indicating an on-timing sequence, and divides multiple on-timings in the on-timing sequence. By alternately assigning signals COMP1 and COMP2, a signal COMP1 indicating the on-timing of the first phase output transistor (181A) and a signal COMP2 indicating the on-timing of the second phase output transistor (181B) are generated ( (See Figure 2).

Then, the ON time of the output transistors 181A and 181B is set (adjusted) using the PLL circuit 160 so that each switching frequency of the output stage circuits 180A and 180B matches or approximates a predetermined reference frequency f _CLK . When the DC/DC converter 10 is in a stable state, the PLL circuit 160 is in a locked state, and the switching frequencies of the output stage circuits 180A and 180B (the frequencies of the drive control signals DRV1 and DRV2) are substantially fixed at the reference frequency f _CLK . , the on-time of the output transistors (181A, 181B) of each phase is substantially fixed at a time suitable for the load current (corresponding to the output current _IOUT ) at that time. In other words, on-time control similar to the constant on-time control method is realized. Furthermore, at this time, the first phase coil current (I _L1 ) and the second phase coil current (I _L2 ) are uniformly adjusted by the function of the current balance signal generation unit 210 .

The configuration and operation of each part of the DC/DC converter 10 will be explained in detail. FIG. 2 is a waveform diagram of several currents, voltages, and signals related to the DC/DC converter 10, and will be referred to as appropriate in the following description.

First, the output stage circuits 180A and 180B and their peripheral circuits will be explained. The output stage circuit 180A is a half bridge circuit consisting of transistors 181A and 182A. Transistors 181A and 182A are configured as N-channel MOSFETs. The drain of transistor 181A is connected to input terminal 251A, and the source of transistor 182A is connected to ground terminal 253A. The source of transistor 181A and the drain of transistor 182A are commonly connected to switch terminal 252A. The switch terminal 252A is connected to one end of the coil L1, and the other end of the coil L1 is connected to the output terminal 254. Output stage circuit 180B is a half bridge circuit consisting of transistors 181B and 182B. Transistors 181B and 182B are configured as N-channel MOSFETs. The drain of transistor 181B is connected to input terminal 251B, and the source of transistor 182B is connected to ground terminal 253B. The source of transistor 181B and the drain of transistor 182B are commonly connected to switch terminal 252B. Switch terminal 252B is connected to one end of coil L2, and the other end of coil L2 is connected to output terminal 254. The input terminals 251A and 251B are connected to the application terminal of the input voltage V _IN (the terminal to which the input voltage V _IN is applied), and receive the input voltage V _IN . Ground terminals 253A and 253B are connected to ground. An output capacitor C _OUT is provided between the output terminal 254 and ground, and an output voltage V _OUT is applied to the output terminal 254 .

A load LD is connected in parallel to the output capacitor C _OUT , and the load LD is driven based on the output voltage V _OUT . The current supplied from the output terminal 254 to the load LD is called an output current or a load current, and is represented by the symbol "I _OUT ".

In the first phase, transistor 181A functions as an output transistor and transistor 182A functions as a synchronous rectifier transistor. Therefore, the transistors 181A and 182A are sometimes referred to as an output transistor 181A and a synchronous rectification transistor 182A, respectively. Further, the voltage applied to the switch terminal 252A is referred to as a switch voltage V _LX1 . Note that it is assumed here that the on-resistances of the transistors 181A and 182A are sufficiently small.

The state of the output stage circuit 180A is one of an output high state, an output low state, and a Hi-Z state. In the output high state of the output stage circuit 180A, the transistor 181A is on and the transistor 182A is off, and substantially the same voltage as the input voltage V _IN appears as the switch voltage V _LX1 . In the output low state of the output stage circuit 180A, the transistor 181A is off and the transistor 182A is on, and substantially the ground voltage (ie, 0V voltage) appears as the switch voltage V _LX1 . When the output stage circuit 180A is in the Hi-Z state, both transistors 181A and 182A are turned off.

By alternately turning on and off the transistors 181A and 182A in the output stage circuit 180A, the input voltage V _IN is switched, and the switch voltage V _LX1 becomes a rectangular wave voltage (see FIG. 2). The switching frequency of the output stage circuit 180A (in other words, the switching frequency of the output transistor 181A) is represented by the symbol "f _SW1 ". The switching frequency f _SW1 is equal to the frequency of the switch voltage V _LX1 and the frequency of the drive control signal DRV1 described below. When the output stage circuit 180A is in the output high state, power based on the input voltage V _IN is supplied from the application end of the input voltage V _IN to the output terminal 254 through the output transistor 181A. Therefore, in each switching cycle of the output stage circuit 180A, the time during which the output stage circuit 180A is in the output high state (that is, the time during which the output transistor 181A is in the on state) is the first phase on time or simply the on time. It is called "T ON1" and is represented by the symbol "T _ON1 ".

In the second phase, transistor 181B functions as an output transistor and transistor 182B functions as a synchronous rectifier transistor. Therefore, the transistors 181B and 182B are sometimes referred to as an output transistor 181B and a synchronous rectification transistor 182B, respectively. Further, the voltage applied to the switch terminal 252B is referred to as a switch voltage V _LX2 . Note that it is assumed here that the on-resistances of the transistors 181B and 182B are sufficiently small.

The state of the output stage circuit 180B is one of an output high state, an output low state, and a Hi-Z state. In the output high state of the output stage circuit 180B, the transistor 181B is on and the transistor 182B is off, and substantially the same voltage as the input voltage V _IN appears as the switch voltage V _LX2 . In the output low state of the output stage circuit 180B, the transistor 181B is off and the transistor 182B is on, and substantially the ground voltage (ie, 0V voltage) appears as the switch voltage V _LX2 . When the output stage circuit 180B is in the Hi-Z state, both transistors 181B and 182B are turned off.

By alternately turning on and off transistors 181B and 182B in the output stage circuit 180B, the input voltage V _IN is switched, and the switch voltage V _LX2 becomes a rectangular wave voltage (see FIG. 2). The switching frequency of the output stage circuit 180B (in other words, the switching frequency of the output transistor 181B) is represented by the symbol "f _SW2 ". The switching frequency f _SW2 is equal to the frequency of the switch voltage V _LX2 and the frequency of the drive control signal DRV2, which will be described later. When the output stage circuit 180B is in the output high state, power based on the input voltage V _IN is supplied from the application end of the input voltage V _IN to the output terminal 254 through the output transistor 181B. Therefore, in each switching cycle of the output stage circuit 180B, the time during which the output stage circuit 180B is in the output high state (that is, the time during which the output transistor 181B is in the on state) is the on time of the second phase or simply the on time. It is called "T ON2" and is represented by the symbol "T _ON2 ".

A rectifying and smoothing circuit is configured by the coil L1, the coil L2, and the output capacitor _COUT . The output voltage V _OUT is generated by rectifying and smoothing the rectangular waveform switch voltages V _LX1 and V _LX2 appearing at the switch terminals 252A and 252B by a rectifying and smoothing circuit. Note that the current flowing through the coil L1 and the current flowing through the coil L2 are referred to as a coil current I _L1 and a coil current I _L2 , respectively. It is assumed that the polarity of the coil current I _L1 flowing from the switch terminal 252A to the output terminal 254 is positive, and that the polarity of the coil current I _L2 flowing from the switch terminal 252B to the output terminal 254 is positive.

The configuration and operation of other circuits including the preceding stage circuits of the output stage circuits 180A and 180B will be explained. The error voltage generation section 110 includes an error amplifier 111, resistors 112 and 113 that are voltage dividing resistors, a resistor 114 that is a feedback resistor, and a node 115. Node 115 corresponds to a feedback input terminal, and a feedback voltage V _FB is applied to node 115. Feedback voltage V _FB is a voltage proportional to output voltage V _OUT . Here, it is assumed that the output voltage V _OUT itself is the feedback voltage V _FB , but a divided voltage of the output voltage V _OUT or the like may be the feedback voltage V _FB . Node 115 is connected to one end of resistor 112, and the other end of resistor 112 is connected to the inverting input terminal of error amplifier 111 and to ground via resistor 113. A predetermined reference voltage V _REF is applied to the non-inverting input terminal of the error amplifier 111. The reference voltage V _REF has a predetermined positive DC voltage value. The output terminal of the error amplifier 111 is connected to the inverting input terminal of the error amplifier 111 via a resistor 114. Therefore, the error amplifier 111 and the resistors 112 to 114 constitute an inverting amplifier. An error voltage V ERR corresponding to the difference between a voltage proportional to the feedback voltage V _FB (voltage applied to the inverting input terminal of the error amplifier 111 ₎ and the reference voltage V _REF is output from the output terminal of the error amplifier 111.

The pulse wave generation section 120A includes resistors 121A and 122A, a capacitor 123A, nodes 124A and 125A, and a ripple injection section 126A. Node 124A is connected to node 115 and thus also has a feedback voltage V _FB applied thereto. One end of each of the resistor 121A and the capacitor 123A is commonly connected to a node 124A, and each other end of the resistor 121A and the capacitor 123A is commonly connected to a node 125A. Node 125A is connected to ground via resistor 122A.

The function of resistors 121A and 122A produces a divided voltage of feedback voltage V _FB at node 125A. The ripple injection section 126A is connected to the node 124A and the node 125A, and injects a ripple to the voltage (divided voltage of the feedback voltage V _FB ) generated at the node 125A due to the function of the resistors 121A and 122A, thereby causing a ripple current to the node 125A. Generate voltage. The pulsating voltage generated at node 125A is referred to as feedback pulsating voltage V _FBIN1 . The feedback pulsating current voltage V _FBIN1 is a voltage that fluctuates in conjunction with the switch voltage V _LX1 . In other words, the feedback pulsating current voltage V _FBIN1 increases monotonically in the high level section of the switch voltage V _LX1 (i.e., the on section of the output transistor 181A), and increases in the low level section of the switch voltage V _LX1 (i.e., the off section of the output transistor 181A). Monotonically decreasing. Therefore, the feedback pulsating current voltage V _FBIN1 has a waveform similar to that of the coil current I _L1 (see FIG. 2). The ripple by the ripple injection section 126A can be generated based on the drive control signal DRV1 and the switch voltage _VLX1 , which will be described later.

Pulse wave generation section 120B includes resistors 121B and 122B, capacitor 123B, and nodes 124B and 125B, as well as ripple injection section 126B. Node 124B is connected to node 115 and thus also has a feedback voltage V _FB applied thereto. One end of each of the resistor 121B and the capacitor 123B is commonly connected to a node 124B, and each other end of the resistor 121B and the capacitor 123B is commonly connected to a node 125B. Node 125B is connected to ground via resistor 122B.

The function of resistors 121B and 122B generates a divided voltage of feedback voltage V _FB at node 125B. The ripple injection section 126B is connected to the node 124B and the node 125B, and injects a ripple to the voltage (divided voltage of the feedback voltage V _FB ) generated at the node 125B due to the function of the resistors 121B and 122B, thereby causing a ripple current to the node 125B. Generate voltage. The pulsating voltage generated at node 125B is referred to as feedback pulsating voltage V _FBIN2 . The feedback pulsating current voltage V _FBIN2 is a voltage that fluctuates in conjunction with the switch voltage V _LX2 . In other words, the feedback pulsating current voltage V _FBIN2 monotonically increases during the high level section of the switch voltage V _LX2 (i.e., the ON section of the output transistor 181B), and increases monotonically during the low level section of the switch voltage V _LX2 (that is, the OFF section of the output transistor 181B). Monotonically decreasing. Therefore, the feedback pulsating current voltage V _FBIN2 has a waveform similar to that of the coil current I _L2 (see FIG. 2). The ripple by the ripple injection section 126B can be generated based on the drive control signal DRV2 and the switch voltage _VLX2 , which will be described later.

Note that the feedback voltage V caused by the resistors 121A and 122A in the pulse wave generation section 120A is the voltage division ratio of the feedback voltage V _FB (that is, the ratio of the resistance values of the resistances 121A and 122A), and the feedback voltage V caused by the resistances 121B and 122B in the pulse wave generation section 120B. The voltage division ratio of _FB (that is, the ratio of the resistance values of the resistors 121B and 122B) is the same. Therefore, the value of the DC component of the feedback pulsating current voltage V _FBIN1 and the value of the DC component of the feedback pulsating current voltage V _FBIN2 are the same.

PWM comparator 130 has first and second non-inverting input terminals, an inverting input terminal, and an output terminal. In the PWM comparator 130, the feedback ripple current voltages V _FBIN1 and V _FBIN2 are input to the first and second non-inverting input terminals, respectively, and the error voltage V _ERR is input to the inverting input terminal. The PWM comparator 130 includes first and second differential amplifiers, and outputs a first differential signal corresponding to the difference (V _FBIN1 - V _ERR ) between the feedback pulsating voltage V _FBIN1 and the error voltage V _ERR to the first differential amplifier. The second differential signal is generated by the amplifier, and a second differential signal corresponding to the difference (V _FBIN2 - V _ERR ) between the feedback pulsating current voltage V _FBIN2 and the error voltage V _ERR is generated by the second differential amplifier. Then, the PWM comparator 130 compares the average voltage of the feedback pulsating current voltages V _FBIN1 and V _FBIN2 with the error voltage V _ERR based on the sum of the above two differences (V _FBIN1 + V _FBIN2 -2· _VERR ). The result is output as a signal COMP.

The average voltage of the feedback pulsating voltages V _FBIN1 and V _FBIN2 is represented by the symbol "V _{FBIN_AVE} ". The average voltage V _{FBIN_AVE} is expressed as "V _{FBIN_AVE} = (V _FBIN1 +V _FBIN2 )/2". As shown in FIG. 2, the PWM comparator 130 maintains the signal COMP at a low level during the period where "V _{FBIN_AVE} > _VERR " is established, and switches from "V _{FBIN_AVE} > _VERR " to "V _{FBIN_AVE} < _VERR ". At each time of switching, the signal COMP is set to high level for a predetermined minute period starting from the switching timing, and then returned to low level (that is, one shot pulse is generated). Note that FIG. 2 also shows the waveform of the average current I _{L_AVE} of the coil currents I _L1 and I _L2 , and from the correspondence between the feedback ripple voltages V _FBIN1 and V _FBIN2 and the coil currents I _L1 and I _L2 , the average The voltage V _{FBIN_AVE} will have a waveform similar to the average current _{IL_AVE} .

Each up edge timing of the signal COMP represents the on timing of either one of the output transistors 181A and 181B. In other words, each rising edge timing of the signal COMP is the timing when the output transistor 181A should be turned on (i.e., the timing when the state of the output stage circuit 180A should be switched to the output high state) or the timing when the output transistor 181B should be turned on (i.e., the timing when the state of the output stage circuit 180A should be switched to the output high state). This represents the timing at which the state of the output stage circuit 180B should be switched to the output high state. Since the rising edge of the signal COMP occurs every time it switches from "V _{FBIN_AVE} > _VERR " to "V _{FBIN_AVE} < _VERR ", the on-timing sequence is defined by the signal COMP. The on-timing sequence consists of a plurality of on-timings arranged in chronological order.

The phase control logic 140 generates and outputs signals COMP1 and COMP2 from the signal COMP. More specifically, the phase control logic 140 generates the signals COMP1 and COMP2 by alternately distributing a plurality of pulses indicating a plurality of on-timings included in the signal COMP to the signals COMP1 and COMP2. To explain more clearly, the following operations are performed. That is, the phase control logic 140 basically keeps the levels of the signals COMP1 and COMP2 at a low level, and when an odd-numbered up edge occurs in the signal COMP, it also applies an up edge to the signal COMP1 in synchronization with the up edge of the signal COMP. The signal COMP1 is set to high level for a predetermined minute time and then returned to low level. When an even-numbered up edge occurs in the signal COMP, an up edge is also generated in the signal COMP2 in synchronization with the up edge of the signal COMP, and the signal COMP2 is set to a high level for a predetermined minute time and then returned to a low level.

The TON setting unit 150A generates a drive control signal DRV1 that specifies the state of the output stage circuit 180A based on the signal COMP1. The TON setting section 150A has a function of setting the on time _TON1 , and uses the drive control signal DRV1 to set the turn-on timing of the output transistor 181A (in other words, the timing of switching the output stage circuit 180A from the output low state to the output high state). and the on time of the output transistor 181A, that is, the on time _TON1 , are defined. At this time, the TON setting section 150A generates the drive control signal DRV1 by referring to the signal S _PLL input from the PLL circuit 160 and the current balance signal S _CB1 input from the current balance signal generation section 210 (for details, see (described later).

The drive control signal DRV1 is a binary signal that takes a signal level of low level or high level, and the on period and off period of the output transistor 181A are specified by the drive control signal DRV1. Here, the high level section of the drive control signal DRV1 is associated with the on section of the output transistor 181A (the section where the output stage circuit 180A should be in the output high state), and the low level section of the drive control signal DRV1 is associated with the on section of the output transistor 181A. (the period in which the output stage circuit 180A should be in the output low state). The up edge timing of the signal COMP1 corresponds to the turn-on timing of the output transistor 181A, and the output transistor 181A is turned off after the on-time _TON1 has elapsed since the turn-on of the output transistor 181A. It can also be said that the on period and off period of the output transistor 181A are set based on the setting contents of _TON1 .

The TON setting unit 150B generates a drive control signal DRV2 that specifies the state of the output stage circuit 180B based on the signal COMP2. The TON setting unit 150B has a function of setting an on-time _TON2 , and uses the drive control signal DRV2 to set the turn-on timing of the output transistor 181B (in other words, the timing of switching from the output low state to the output high state of the output stage circuit 180B). and the on time of the output transistor 181B, that is, the on time _TON2 , are defined. At this time, the drive control signal DRV2 is generated with reference to the signal _SPLL input from the PLL circuit 160 and the current balance signal _SCB2 input from the current balance signal generation section 210 (details will be described later).

The drive control signal DRV2 is a binary signal that takes a signal level of low level or high level, and the on period and off period of the output transistor 181B are specified by the drive control signal DRV2. Here, the high level section of the drive control signal DRV2 is associated with the on section of the output transistor 181B (the section where the output stage circuit 180B should be in the output high state), and the low level section of the drive control signal DRV2 is associated with the on section of the output transistor 181B. (the period in which the output stage circuit 180B should be in the output low state). The up edge timing of the signal COMP2 corresponds to the turn-on timing of the output transistor 181B, and the output transistor 181B is turned off after the on-time _TON2 has elapsed since the turn-on of the output transistor 181B. It can also be said that the on period and off period of the output transistor 181B are set based on the setting contents of _TON2 .

PLL circuit 160 is a phase locked circuit. A reference clock signal CLK, which is a rectangular wave signal having a predetermined reference frequency f _CLK , and a drive control signal DRV1 output from the TON setting section 150A are input to the PLL circuit 160. The PLL circuit 160 sets the signal S _PLL according to the phase difference between the reference clock signal CLK and the drive control signal DRV1 (that is, the difference between the phase of the reference clock signal CLK and the phase of the drive control signal DRV1) to the TON setting sections 150A and 150B. Output to.

The output stage drive section 170A performs switching drive of the output stage circuit 180A based on the drive control signal DRV1. The switching drive of the output stage circuit 180A includes an operation of alternately switching the state of the output stage circuit 180A between an output low state and an output high state. That is, the output stage driver 170A is connected to each gate of the transistors 181A and 182A, the switch terminal 252A, and the ground, so that the output stage circuit 180A is in the output low state during the low level section of the drive control signal DRV1, and Each gate voltage (more specifically, the gate-source voltage) of the transistors 181A and 182A is controlled so that the output stage circuit 180A has an output high state during the high level section of the drive control signal DRV1 (however, the protection circuit 200A (assuming the protection action is non-execution). Note that a bootstrap circuit (not shown) generates a voltage necessary for switching the output transistor 181A from the input voltage V _IN .

The output stage driver 170B performs switching drive of the output stage circuit 180B based on the drive control signal DRV2. The switching drive of the output stage circuit 180B includes an operation of alternately switching the state of the output stage circuit 180B between an output low state and an output high state. That is, the output stage driver 170B is connected to each gate of the transistors 181B and 182B, the switch terminal 252B, and the ground, so that the output stage circuit 180B is in the output low state during the low level section of the drive control signal DRV2, and Each gate voltage (more specifically, the gate-source voltage) of the transistors 181B and 182B is controlled so that the output stage circuit 180B has an output high state during the high level section of the drive control signal DRV2 (however, the protection circuit 200B (assuming the protection action is non-execution). Note that a bootstrap circuit (not shown) generates a voltage necessary for switching the output transistor 181B from the input voltage V _IN .

The current sensor 190A detects the first target current (specifically, detects the current value of the first target current). The first target current is the current flowing through the switch terminal 252A. The current sensor 190A may detect the first target current by detecting the current flowing between the source and drain of the output transistor 181A or the current flowing between the source and drain of the synchronous rectification transistor 182A. If a short-circuit abnormality in which the transistors 181A and 182A are turned on at the same time is ignored, the current flowing through the switch terminal 252A passes through the coil L1, so the first target current is also the coil current I _L1 . The protection circuit 200A performs a predetermined protection operation (overcurrent protection operation and negative current protection operation) by controlling the output stage drive unit 170A as necessary based on the detection result of the current sensor 190A.

The current sensor 190B detects the second target current (specifically, detects the current value of the second target current). The second target current is the current flowing through the switch terminal 252B. The current sensor 190B may detect the second target current by detecting the current flowing between the source and drain of the output transistor 181B or the current flowing between the source and drain of the synchronous rectification transistor 182B. If a short-circuit abnormality in which transistors 181B and 182B are turned on at the same time is ignored, the current flowing through switch terminal 252B passes through coil L2, so the second target current is also coil current I _L2 . The protection circuit 200B performs a predetermined protection operation (overcurrent protection operation and negative current protection operation) by controlling the output stage drive unit 170B as necessary based on the detection result of the current sensor 190B.

The current balance signal generation unit 210 compares the detection results of the current sensors 190A and 190B to generate current balance signals S _CB1 and S _CB2 for adjusting (correcting) the on-times T _ON1 and T _ON2 as necessary. The generated current balance signals S _CB1 and S _CB2 are output to TON setting units 150A and 150B, respectively.

FIG. 3(a) shows a circuit configuration of the pulse wave generation unit 120A including one configuration example of the ripple injection unit 126A, and FIG. 3(b) shows a circuit configuration of the pulse wave generation unit 120B including one configuration example of the ripple injection unit 126B. Show the configuration.

The ripple injection section 126A in FIG. 3A includes a buffer circuit 126A_1, a resistor 126A_2, and capacitors 126A_3 and 126A_4. The drive control signal DRV1 is input to the input terminal of the buffer circuit 126A_1. Therefore, the output signal of the buffer circuit 126A_1 also becomes high level during the high level period of the drive control signal DRV1, and the output signal of the buffer circuit 126A_1 also becomes low level during the low level period of the drive control signal DRV1. However, since the buffer circuit 126A_1 operates with the voltage proportional to the input voltage V _IN (here V _IN /4) as the positive power supply voltage and the ground as the negative power supply voltage, the output signal of the buffer circuit 126A_1 , the high level has substantially the positive side power supply voltage (V _IN /4 here) of the buffer circuit 126A_1, and the low level has a voltage of substantially 0V. The output signal of the buffer circuit 126A_1 is applied to one end of the resistor 126A_2, and the other end of the resistor 126A_2 is connected to the node 124A via the capacitor 126A_3 and to the node 125A via the capacitor 126A_4.

Since the switch voltage VLX1 is controlled to be at high level and low level in the high level section and low level section of the drive control signal DRV1, the switch voltage _VLX1 is controlled to be at high level and low level in the high level section and low level section of the drive control signal _DRV1 . A feedback pulsating current voltage V _FBIN1 is obtained which varies in conjunction with the switch voltage V _LX1 . Regarding the feedback pulsating current voltage V _FBIN1 , fluctuating based on the feedback voltage V _FB means that the feedback pulsating current voltage V _FBIN1 fluctuates around a voltage proportional to the feedback voltage V _FB (here, a partial voltage of the voltage V _FB ). refers to

The configuration shown in FIG. 3(a) is only an example, and the circuit configurations of the ripple injection section 126A and the pulse wave generation section 120A can be changed in various ways as long as the feedback pulsating voltage V _FBIN1 having the same characteristics as described above can be obtained. It is. The buffer circuit 126A_1 is deleted from the circuit of FIG. 3(a), and the switch voltage V _LX1 itself or the divided voltage of the switch voltage V _LX1 is applied to one end of the resistor 126A_2 that is not connected to the capacitors 126A_3 and 126A_4. You may also enter

The ripple injection section 126B in FIG. 3(b) includes a buffer circuit 126B_1, a resistor 126B_2, and capacitors 126B_3 and 126B_4. The drive control signal DRV2 is input to the input terminal of the buffer circuit 126B_1. Therefore, the output signal of the buffer circuit 126B_1 also becomes a high level during the high level period of the drive control signal DRV2, and the output signal of the buffer circuit 126B_1 also becomes a low level during the low level period of the drive control signal DRV2. However, since the buffer circuit 126B_1 operates with the voltage proportional to the input voltage V _IN (here V _IN /4) as the positive power supply voltage and the ground as the negative power supply voltage, the output signal of the buffer circuit 126B_1 , the high level has substantially the positive side power supply voltage (V _IN /4 here) of the buffer circuit 126B_1, and the low level has a voltage of substantially 0V. The output signal of the buffer circuit 126B_1 is applied to one end of the resistor 126B_2, and the other end of the resistor 126B_2 is connected to the node 124B via the capacitor 126B_3 and to the node 125B via the capacitor 126B_4.

Since the switch voltage _VLX2 is controlled to be at high level and low level in the high level section and low level section of the drive control signal DRV2, the configuration shown in _FIG. A feedback pulsating current voltage V _FBIN2 is obtained which varies in conjunction with the switch voltage V _LX2 . Regarding the feedback pulsating current voltage V _FBIN2 , fluctuating based on the feedback voltage V _FB means that the feedback pulsating current voltage V _FBIN2 fluctuates around a voltage proportional to the feedback voltage V _FB (here, a partial voltage of the voltage V _FB ). refers to

The configuration shown in FIG. 3(b) is only an example, and the circuit configurations of the ripple injection section 126B and the pulse wave generation section 120B can be changed in various ways as long as the feedback pulsating voltage V _FBIN2 having the same characteristics as described above can be obtained. It is. The buffer circuit 126B_1 is deleted from the circuit of FIG. 3(b), and the switch voltage V _LX2 itself or the divided voltage of the switch voltage V _LX2 is applied to one end of the resistor 126B_2 that is not connected to the capacitors 126B_3 and 126B_4. You may also enter

As described above, in the DC/DC converter 10, the potential difference between the non-inverting input terminal and the inverting _input terminal of the error amplifier 111 is zeroed by the basic feedback loop that extends from the error voltage generation section 110 to the section that generates the output voltage V OUT. Feedback control is performed to maintain the output voltage V _{TG at a predetermined target voltage V TG (} that is, it matches or approaches the target voltage V _TG ) through adjustment of the error voltage V _ERR . The target voltage V _TG is determined by the ratio of the resistance values of the resistors 112 and 113 and the reference voltage V _REF .

An explanation will be added regarding the generation operation of the drive control signals DRV1 and DRV2. First, for convenience of explanation, we will ignore the existence of the current balance signals S _CB1 and S _CB2 , and will explain the method of generating the drive control signal DRV1 based on the signals COMP1 and _SPLL and the method of generating the drive control signal DRV2 based on the signals COMP2 and S _PLL . Explain how to generate it. The PLL circuit 160 generates _{the signal SPLL} so that the phase difference between the reference clock signal CLK and the drive control signal DRV1 (the difference between the phase of the reference clock signal CLK and the phase of the drive control signal DRV1) is zero. The reference clock signal CLK, like the drive control signals DRV1 and DRV2, is a rectangular wave signal having a low or high signal level. A state in which the phase difference between the reference clock signal CLK and the drive control signal DRV1 is zero means that the reference clock signal CLK and the drive control signal DRV1 have the same frequency, but the up edge timing of the reference clock signal CLK and the drive control signal This refers to a state in which the up-edge timing of DRV1 matches, and maintaining this state is expressed as PLL lock. Except for transient states, in principle, the signals COMP1 and COMP2 have the same frequency and the phase difference between the signals COMP1 and COMP2 is maintained at 180°. Therefore, when the PLL is locked, the drive control signal DRV1 and DRV2 (that is, the switching frequency f _SW1 of the output stage circuit 180A and the switching frequency f _SW2 of the output stage circuit 180B) match the reference frequency f _CLK that is the frequency of the reference clock signal CLK.

Referring to FIG. 4, a state in which the drive control signal DRV1 is ahead in phase with respect to the reference clock signal CLK corresponds to a state in which the frequencies of the drive control signals DRV1 and DRV2 are higher than the reference frequency f _CLK . At this time, the PLL circuit 160 outputs a signal S _PLL for increasing the on-times T _ON1 and T _ON2 by the same amount of time to the TON setting sections 150A and 150B, and the TON setting sections 150A and 150B turn on according to the signal S _PLL . Increase times T _ON1 and T _ON2 by the same amount of time. The amount of this increase is preferably proportional to the magnitude of the phase difference between the reference clock signal CLK and the drive control signal DRV1. It is assumed that the initial values of the on-times T _ON1 and T _ON2 are a common reference on-time T _ONREF . As the on-times T _ON1 and T _ON2 increase, under the assumption that the error voltage V _ERR is constant, the switching from "V _{FBIN_AVE} > V _ERR " to "V _{FBIN_AVE} < V _ERR " occurs through an increase in the average voltage V _{FBIN_AVE} . Since the interval between occurrences of the signal COMP becomes longer, the frequency of the signal COMP decreases. That is, the frequencies of the drive control signals DRV1 and DRV2 decrease toward the reference frequency _{f_CLK} .

Referring to FIG. 5, a state where the drive control signal DRV1 is delayed in phase with respect to the reference clock signal CLK corresponds to a state where the frequencies of the drive control signals DRV1 and DRV2 are lower than the reference frequency f _CLK . At this time, the PLL circuit 160 outputs a signal _SPLL for reducing the on-times T _ON1 and T _ON2 by the same amount of time to the TON setting sections 150A and 150B, and the TON setting sections 150A and 150B turn on according to the signal S _PLL . Decrease times T _ON1 and T _ON2 by the same amount of time. The amount of this decrease is preferably proportional to the magnitude of the phase difference between the reference clock signal CLK and the drive control signal DRV1. It is assumed that the initial values of the on-times T _ON1 and T _ON2 are a common reference on-time T _ONREF . When the on-times T _ON1 and T _ON2 decrease, under the assumption that the error voltage V _ERR is constant, the switching from "V _{FBIN_AVE} > V _ERR " to "V _{FBIN_AVE} < V _ERR " occurs through a decrease in the average voltage V _{FBIN_AVE} . Since the interval between occurrences of is shortened, the frequency of signal COMP increases. In other words, the frequencies of the drive control signals DRV1 and DRV2 increase toward the reference frequency _{f_CLK} .

By performing the above-described control by the PLL circuit 160, the frequencies of the drive control signals DRV1 and DRV2 (i.e., switching frequencies f _SW1 and f _SW2 ) are matched with or close to the reference frequency f _CLK , and the PLL is locked in a steady state. is achieved. That is, the frequencies of the drive control signals DRV1 and DRV2 (ie, switching frequencies f _SW1 and f _SW2 ) match the reference frequency f _CLK .

Next, the function of the current balance signal generation section 210 will be explained. Although the feedback pulsating current voltages V _FBIN1 and V _FBIN2 have waveforms similar to the coil currents I _L1 and I _L2 , they are not physical quantities representing the coil currents I _L1 and I _L2 themselves, but are separately determined by the current balance between the coil currents I _L1 and I _L2 . It is necessary to take That is, if the current balance signal generation section 210 were not provided, the coil currents I _L1 and I _L2 may be stabilized in a non-uniform state as shown in FIG. 6 . In the state shown in FIG. 6, the situation is stable as "I _L1 > I _L2 ". In this case, if on-time T _ON1 is corrected to decrease while on-time T _ON2 is corrected to increase, it is expected that "I _L1 = I _L2 " will be achieved, and by achieving "I _L1 = I _L2 ", the result shown in FIG. 6 will be achieved. The state changes to the state shown in FIG. In addition, "I _L1 > I _L2 " here specifically means that the maximum value, average value, or minimum value of the coil current I _L1 is higher than the maximum value, average value, or minimum value of the coil current I _L2 , respectively. "I _L1 = I _L2 " means a situation in which the maximum value, average value, or minimum value of the coil current I _L1 is the maximum value, average value, or minimum value of the coil current I _L2 , respectively. It means a situation that matches the value.

In order to achieve “I _L1 =I _L2 ”, the DC/DC converter 10 is provided with a current balance signal generation section 210.

The current balance signal generation unit 210 receives the detection result of the first target current by the current sensor 190A and the detection result of the second target current by the current sensor 190B. It is now assumed that there is no short-circuit abnormality in which transistors 181A and 182A are turned on at the same time. Then, the first target current detected by the current sensor 190A is the coil current _IL1 flowing through the switch terminal 252A, and the second target current detected by the current sensor 190B is the coil current _IL2 flowing through the switch terminal 252B.

The current balance signal generation unit 210 generates a detection result of the first target current (coil current I _L1 ) provided from the current sensor 190A and a detection result of the second target current (coil current I _L2 ) provided from the current sensor 190B. Based on this, current balance signals S _CB1 and S _CB2 are generated for equalizing the magnitude of the first target current and the magnitude of the second target current. When the first target current is larger than the second target current, the TON setting units 150A and 150B decrease the on time T _ON1 and increase the on time T _ON2 based on the current balance signals S _CB1 and S _CB2 . However, when the first target current is smaller than the second target current, the on-time T _ON1 is increased and the on-time T _ON2 is decreased based on the current balance signals S _CB1 and S _CB2 . The fact that the first target current is larger than the second target current specifically means that the evaluation value of the first target current is larger than the evaluation value of the second target current, and the first target current is larger than the second target current. Specifically, being smaller than means that the evaluation value of the first target current is smaller than the evaluation value of the second target current. The evaluation value of the first and second target currents may be the average value of the first and second target currents, the maximum value of the first and second target currents, or the minimum value of the first and second target currents. But it's okay.

An example of operation will be described in which the average value of the first and second target currents is used as the evaluation value of the first and second target currents.
The current sensor 190A detects the current flowing between the drain and the source of the synchronous rectifier transistor 182A as a first target current in the period in which the output stage circuit 180A is in the output low state (hereinafter referred to as the first low period), and detects the current flowing between the drain and source of the synchronous rectification transistor 182A. First coil current information indicating the detection result is output to the generation unit 210. The average value of the first target current during the first low section in each switching cycle of the output stage circuit 180A is specified by the first coil current information. The average value of the first target current represents the average value I _{L1_AVE} of the coil current I _L1 during the first low section (see FIG. 7). The average value _{IL1_AVE} is derived every switching period of the output stage circuit 180A.
The current sensor 190B detects the current flowing between the drain and the source of the synchronous rectification transistor 182B as a second target current during the period in which the output stage circuit 180B is in the output low state (hereinafter referred to as the second low period), and detects the current flowing between the drain and source of the synchronous rectification transistor 182B. Second coil current information indicating the detection result is output to the generation unit 210. The second coil current information specifies the average value of the second target current during the second low section in each switching period of the output stage circuit 180B. The average value of the second target current represents the average value _{IL2_AVE} of the coil current I _L2 during the second low section (see FIG. 7). The average value _{IL2_AVE} is derived every switching period of the output stage circuit 180B.

The current balance signal generation unit 210 sets the average value I _{L1_AVE} as a first evaluation value and the average value I _{L2_AVE} as a second evaluation value, and compares the first and second evaluation values. Since the first and second evaluation values are updated sequentially, the generation unit 210 repeatedly performs the operation of comparing the latest set of first and second evaluation values.

In a first unbalance situation where the first evaluation value is larger than the second evaluation value, the current balance signal generation unit 210 generates a current balance signal _SCB1 that instructs correction to decrease the on time _TON1 , while reducing the on time TON1. Generates a current balance signal _SCB2 that instructs _ON2 increase correction. In the first unbalanced situation, the amount of correction to decrease the on-time T _ON1 and the amount of correction to increase the on-time T _ON2 may be determined according to the magnitude of the difference between the first and second evaluation values. However, it may be a predetermined fixed amount.
In the first unbalanced situation, the TON setting unit 150A decreases the on-time T _ON1 determined based on the signal S _PLL according to the current balance signal S _CB1 , and sends a drive control signal DRV1 specifying the on-time T _ON1 after the decrease correction. (Therefore, the length of the high level section of the drive control signal DRV1 is set as the on time _TON1 after reduction correction).
In the first unbalanced situation, the TON setting unit 150B increases the on-time T _ON2 determined based on the signal S _PLL according to the current balance signal S _CB2 , and sends a drive control signal DRV2 specifying the on-time T _ON2 after the increase correction. (Therefore, the length of the high level section of the drive control signal DRV2 is set as the on time _TON2 after the increase correction).

In a second unbalance situation where the first evaluation value is smaller than the second evaluation value, the current balance signal generation unit 210 generates a current balance signal _SCB1 that instructs an increase correction of the on time _TON1 , while increasing the on time TON1. Generates a current balance signal _SCB2 that instructs reduction correction of _ON2 . In the second unbalanced situation, the amount of correction to increase the on-time T _ON1 and the amount of correction to decrease the on-time T _ON2 may be determined according to the magnitude of the difference between the first and second evaluation values. However, it may be a predetermined fixed amount.
In the second unbalanced situation, the TON setting unit 150A increases the on-time T _ON1 determined based on the signal S _PLL according to the current balance signal S _CB1 , and sends a drive control signal DRV1 specifying the on-time T _ON1 after the increase correction. (Therefore, the length of the high level section of the drive control signal DRV1 is set as the on time _TON1 after the increase correction).
In the second unbalanced situation, the TON setting unit 150B reduces the on-time T _ON2 determined based on the signal S _PLL according to the current balance signal S _CB2 , and sends a drive control signal DRV2 specifying the on-time T _ON2 after the reduction correction. (Therefore, the length of the high level section of the drive control signal DRV2 is set as the on time _TON2 after reduction correction).

As described above, if it is detected that the first evaluation value corresponding to the coil current I _L1 is larger than the second evaluation value corresponding to the coil current I _L2 , then the on-time T _ON1 is corrected to decrease. The difference between the first and second evaluation values is reduced by increasing the on-time T _ON2 . On the other hand, if it is detected that the first evaluation value is smaller than the second evaluation value, then the on-time T _ON1 is corrected to increase and the on-time T _ON2 is corrected to decrease, so that the first and The difference between the second evaluation values is reduced. By repeating such correction (adjustment), the difference between the first and second evaluation values becomes zero or is maintained near zero. That is, the difference between the first target current (coil current _IL1 ) and the second target current (coil current _IL2 ) is reduced. Specifically, the difference between the average value of the coil current I _L1 and the average value of the coil current I _L2 is reduced, and as a result, the maximum value or minimum value of the coil current I _L1 and the maximum value or minimum value of the coil current I _L2 are reduced. The difference between the two is also reduced.

Note that the current sensor 190A detects the current flowing between the drain and source of the output transistor 181A as a first target current in a period in which the output stage circuit 180A is in an output high state (hereinafter referred to as a first high period), First coil current information indicating the detection result may be output to the generation unit 210. Then, the current sensor 190B detects the current flowing between the drain and the source of the output transistor 181B as a second target current in a period in which the output stage circuit 180B is in the output high state (hereinafter referred to as a second high period), Second coil current information indicating the detection result may be output to the generation unit 210. In this case, the first coil current information specifies the average value of the first target current during the first high section in each switching period of the output stage circuit 180A, and the second coil current information specifies the average value of the first target current in each switching period of the output stage circuit 180B. An average value of the second target current during the second high interval is determined. The generation unit 210 then sets the average value of the first target current during the first high interval as the first evaluation value, and sets the average value of the second target current during the second high interval as the second evaluation value. Can be done.

As described above, instead of the average value of each target current, the local maximum value or minimum value of each target current may be used as the evaluation value. That is, the current balance signal generation unit 210 may use the local maximum values of the first and second target currents in each switching cycle as the first and second evaluation values, and compare them. The minimum values of the first and second target currents in the switching period may be used as the first and second evaluation values to compare them.

For convenience of explanation, the function of the PLL circuit 160 and the function of the current balance signal generation section 210 have been explained separately, but in reality, in the DC/DC converter 10, in addition to the above-mentioned basic feedback loop including the error voltage generation section 110, Thus, a PLL feedback loop including the PLL circuit 160 and TON setting sections 150A and 150B, and a current balance feedback loop including the current balance signal generation section 210 and TON setting sections 150A and 150B are formed, and these feedback loops are connected in parallel. A feedback operation for making the output voltage _VOUT match or approximate the target voltage _VTG , a feedback operation for making the switching frequencies _fSW1 and _fSW2 match or approximate the reference frequency _fCLK , and a coil A feedback operation for equalizing the currents I _L1 and I _L2 is performed simultaneously.

When the magnitude of the load LD (that is, the load current I _OUT ) rapidly decreases starting from a certain stable state, the output voltage V _OUT transiently deviates somewhat from the target voltage V _TG . In a transient state, the switching frequencies f _SW1 and f _SW2 may deviate somewhat from the reference frequency f _CLK , and variations may occur between the coil currents I _L1 and I _L2 , but due to the functions of each feedback operation described above, the necessary time elapses. After that, “V _OUT =V _TG ”, “f _SW1 = f _SW2 = f _CLK ” and “I _L1 = I _L2 ” are realized again in a form suitable for the conditions after the load change.

Although the PLL is not locked during the process in which the output voltage _VOUT rises from 0V to the target voltage _VTG when the DC/DC converter 10 is started, the pulses in the signal COMP are alternately changed to the signals COMP1 and COMP2 in this process. By the above-mentioned method of distributing the power to the first and second phases, a switching phase difference between the first and second phases is ensured. Then, in the process of increasing the output voltage V _OUT , the switching frequencies f _SW1 and f _SW2 approach the reference frequency f _CLK , and the coil currents I _L1 and I _L2 are equalized.

The DC/DC converter 10 may operate in any of a plurality of operation modes, and the plurality of operation modes may include a PFM mode and a PWM mode. In the PWM mode, the operation described above in this embodiment is performed, and the output stage circuits 180A and 180B are switching driven using pulse width modulation. On the other hand, in the PFM mode, the output stage circuits 180A and 180B are switched and driven using pulse frequency modulation. Although a detailed explanation of the operation in the PFM mode will be omitted, even immediately after the operation mode of the DC/DC converter 10 is switched from the PFM mode to the PWM mode, the pulses in the signal COMP are alternately distributed to the signals COMP1 and COMP2. The above method ensures a switching phase difference between the first and second phases.

According to the DC/DC converter 10 according to this embodiment, it is possible to perform on-time control similar to the constant on-time control method while ensuring a 180° phase difference in the switching drive of the output stage circuits 180A and 180B. As a result, high load response performance can be achieved. In addition, the power supply efficiency can be optimized (maximized) by performing control to equalize the coil currents I _L1 and I _L2 .

Note that here, we focused on the on-times T _ON1 and T _ON2 as objects of setting, adjustment, or correction, but the setting and increase/decrease of the on-time T _ON1 are also the settings and increases/decrements of the on-duty D _ON1 , and the on-time T _ON2 The setting and increase/decrease of is also the setting and increase/decrease of on-duty D _ON2 . Therefore, the TON setting unit 150A may be considered to be responsible for setting and increasing/decreasing the on-duty D _ON1 , and the TON setting unit 150B may be considered to be responsible for setting and increasing/decreasing the on-duty D _ON2 (other optional items described later). The same applies to the embodiments of ). The on-duty _DON1 refers to the proportion of the on-time _TON1 in each cycle of the switching drive of the output stage circuit 180A (the proportion of the on-time _TON1 in the reciprocal of the switching frequency _fSW1 ), and the on-duty D _ON2 refers to the proportion occupied by the on time T _ON2 in each cycle of the switching drive of the output stage circuit 180B (the proportion occupied by the on time T _ON2 in the reciprocal of the switching frequency f _SW2 ).

<<Second embodiment>>
A second embodiment of the present disclosure will be described. The second embodiment and the third to sixth embodiments described later are embodiments based on the first embodiment, and unless there is a contradiction, matters not specifically stated in the second to sixth embodiments are based on the first embodiment. The description of the embodiment may also be applied to the second to sixth embodiments. When interpreting the description of the second embodiment, the description of the second embodiment may take precedence regarding matters that are inconsistent between the first and second embodiments (the same applies to the third to sixth embodiments described later). . Any plurality of embodiments among the first to sixth embodiments may be combined as long as there is no contradiction.

A part of the configuration of the DC/DC converter 10 in FIG. 1 can be used to form a step-down single-phase DC/DC converter having multiple channels. FIG. 8 is an overall configuration diagram of the DC/DC converter 20 according to the second embodiment. The DC/DC converter 20 is a step-down single-phase DC/DC converter having two channels. The two channels consist of a first channel and a second channel. The DC/DC converter 20 generates an output voltage V OUT1 by stepping down the input voltage V _IN1 in the first channel, and generates _{an output voltage V OUT2 by stepping down the input voltage V IN2 in the} second channel.

The input voltages V _IN1 and V _IN2 are positive DC voltages, and have voltage values within the range of 4.0V to 18.0V, for example. It does not matter whether the input voltages V _IN1 and V _IN2 match or do not match. The output voltages V _OUT1 and V _OUT2 are lower than the input voltages V _IN1 and V _IN2, respectively, and have stabilized positive DC voltage values except for the transient state of the DC/DC converter 20. The target values of the output voltages V _OUT1 and V _OUT2 (values of target voltages V _{TG1 and} V _TG2 to be described later) have a voltage value within the range of 0.6V to 3.4V, for example. It does not matter whether the target values of the output voltages V _OUT1 and V _OUT2 match or do not match.

The DC/DC converter 20 includes a first channel DC/DC converter and a second channel DC/DC converter.

The first channel DC/DC converter will be explained. The first channel DC/DC converter includes an error voltage generation section 110A, a pulse wave generation section 120A, a PWM comparator 130A, a TON setting section 150A, a PLL circuit 160A, an output stage drive section 170A, and an output stage circuit. 180A, a current sensor 190A, a protection circuit 200A, a coil L1, an output capacitor _COUT1 , an input terminal 251A, a switch terminal 252A, a ground terminal 253A, and an output terminal 254A.

The configuration of the output stage circuit 180A is as described in the first embodiment. However, in the DC/DC converter 20, the input terminal 251A is connected to the application terminal of the input voltage V _IN1 (the terminal to which the input voltage V _IN1 is applied) and receives the input voltage V _IN1 , and the switch terminal 252A is connected to the output terminal via the coil L1. By providing an output capacitor C _OUT1 connected to the terminal 254A and between the output terminal 254A and ground, an output voltage V _OUT1 is applied to the output terminal 254A.

By alternately turning on and off transistors 181A and 182A in output stage circuit 180A, input voltage V _IN1 is switched, and a rectangular waveform switch voltage V _LX1 is generated at switch terminal 252A. A rectifying and smoothing circuit is configured by the coil L1 output capacitor C _OUT1 , and the rectangular waveform switch voltage V _LX1 is rectified and smoothed by the rectifying and smoothing circuit to generate an output voltage V _OUT1 .

Error voltage generation section 110A in FIG. 8 has the same configuration as error voltage generation section 110 in FIG. 1. The error amplifier 111, resistors 112, 113, 114, and node 115 in the error voltage generator 110 in FIG. It is called. Node 115A corresponds to a feedback input terminal, and feedback voltage V _FB1 is applied to node 115A. Feedback voltage V _FB1 is a voltage proportional to output voltage V _OUT1 . Here, it is assumed that the output voltage V _OUT1 itself is the feedback voltage V _FB1 , but a divided voltage of the output voltage V _OUT1 or the like may be the feedback voltage V _FB1 . Node 115A is connected to one end of resistor 112A, and the other end of resistor 112A is connected to the inverting input terminal of error amplifier 111A and to ground via resistor 113A. A predetermined reference voltage V _REF1 is applied to the non-inverting input terminal of the error amplifier 111A. The reference voltage V _REF1 has a predetermined positive DC voltage value. The output terminal of the error amplifier 111A is connected to the inverting input terminal of the error amplifier 111A via a resistor 114A. Therefore, an inverting amplifier is configured by the error amplifier 111A and the resistors 112A to 114A. An error voltage V _ERR1 corresponding to the difference between a voltage proportional to the feedback voltage V FB1 (voltage applied to the inverting input terminal of the error amplifier 111A ₎ and the reference voltage V _REF1 is output from the output terminal of the error amplifier 111A.

Pulse wave generating section 120A in FIG. 8 is the same as pulse wave generating section 120A in FIG. 1, and feedback pulsating current voltage V _FBIN1 is generated at node 125A. However, in the pulse wave generation unit 120A of FIG. 8, the feedback voltage applied to the node 124A is the feedback voltage V _FB1 based on the output voltage V _OUT1 . That is, the pulse wave generation unit 120A generates the feedback pulsating current voltage V _FBIN1 based on the feedback voltage V _FB1 . The characteristics of the feedback pulsating current voltage V _FBIN1 are as described in the first embodiment, and have a waveform similar to the waveform of the coil current I _L1 . Note that when the configuration shown in FIG. 3A is adopted for the pulse wave generation unit 120A in FIG. 8, the positive power supply voltage of the buffer circuit 126A_1 is set to "V _IN1 /4".

The PWM comparator 130A generates and outputs a signal COMP1 by comparing the error voltage V _ERR1 and the feedback ripple voltage V _FBIN1 . Specifically, the PWM comparator 130A maintains the signal COMP1 at a low level in the section where "V _FBIN1 > _VERR1 " is established, and when it switches from "V _FBIN1 > _VERR1 " to "V _FBIN1 < _VERR1 ". , the signal COMP1 is set to high level for a predetermined minute period starting from the switching timing, and then returned to low level.

The TON setting unit 150A generates a drive control signal DRV1 that specifies the state of the output stage circuit 180A based on the signal COMP1 supplied from the PWM comparator 130A. In the DC/DC converter 20 of FIG. 8, a PLL circuit 160A is used as the PLL circuit 160 (see FIG. 1), and the drive control signal DRV1 is generated regardless of the current balance signal _SCB1 (see FIG. 1). In the first place, the current balance signal _SCB1 does not exist). Except for these points, the operation of the TON setting section 150A is as described in the first embodiment.

The PLL circuit 160A in FIG. 8 is the same as the PLL circuit 160 in FIG. ) is output to the TON setting section 150A, and the frequency of the drive control signal DRV1 is made to match or approximate the reference frequency f _CLK (the frequency of the reference clock signal CLK) in cooperation with the TON setting section _150A . The configuration and operation of the output stage drive unit 170A, current sensor 190A, and protection circuit 200A are as described in the first embodiment.

The second channel DC/DC converter will be explained. The second channel DC/DC converter includes an error voltage generation section 110B, a pulse wave generation section 120B, a PWM comparator 130B, a TON setting section 150B, a PLL circuit 160B, an output stage drive section 170B, and an output stage circuit. 180B, a current sensor 190B, a protection circuit 200B, a coil L2, an output capacitor _COUT2 , an input terminal 251B, a switch terminal 252B, a ground terminal 253B, and an output terminal 254B.

In the DC/DC converter 20 of FIG. 8, the configuration and operation of the second channel DC/DC converter are the same as the configuration and operation of the first channel DC/DC converter. The above-mentioned matters also apply to the second channel DC/DC converter. However, in this application, the codes or symbols 110A to 115A, 120A to 126A, 126A_1 to 126A_4, 130A, 150A, 160A, 170A, 180A to 182A, 190A described in relation to the first channel DC/DC converter , 200A, 251A to 254A, L1, C _OUT1 , V _FB1 , V _REF1 , V _ERR1 , V _LX1 , V _FBIN1 , COMP1, DRV1, S _PLL1 , V _IN1 , V _OUT1 , I _L1 are the DC/ In the DC converter, the symbols or symbols 110B to 115B, 120B to 126B, 126B_1 to 126B_4, 130B, 150B, 160B, 170B, 180B to 182B, 190B, 200B, 251B to 254B, L2, C _OUT2 , V _FB2 , V It can be read as _REF2 , _VERR2 , V _LX2 , V _FBIN2 , COMP2, DRV2, S _PLL2 , V _IN2 , V _OUT2 , and _IL2 . Further, it is assumed that a clock signal CLKB is input to the PLL circuit 160B as a reference clock signal. Clock signal CLKB is an inverted signal of reference clock signal CLK.

In the first channel DC/DC converter included in the DC/DC converter 20, the non-inverting input terminal and the inverting input terminal of the error amplifier 111A are connected by a feedback loop extending from the error voltage generating section 110A to the section that generates the output voltage V _OUT1 . Feedback control is performed to maintain the potential difference between the terminals at zero, and through adjustment of the error voltage V _ERR1 , the output voltage V _OUT1 is stabilized at a predetermined target voltage V _TG1 (that is, it matches the target voltage V _TG1) . or approach). The target voltage V _TG1 is determined by the ratio of the resistance values of the resistors 112A and 113A and the reference voltage V _REF1 . Furthermore, the function of the PLL circuit 160A allows the frequency of the drive control signal DRV1 (therefore, the switching frequency f _SW1 of the output stage circuit 180A) to match or approximate the reference frequency f _CLK .

Independently from this, in the second channel DC/DC converter included in the DC/DC _converter 20, the error amplifier 111B is Feedback control is performed to maintain the potential difference between the non-inverting input terminal and the inverting input terminal at zero, and the output voltage V _OUT2 is stabilized at a predetermined target voltage V _TG2 through adjustment of the error voltage V _ERR2 ( That is, the target voltage V TG2 coincides with or approaches the target voltage V _TG2 ). The target voltage V _TG2 is determined by the ratio of the resistance values of the resistors 112B and 113B and the reference voltage V _REF2 . Furthermore, the function of the PLL circuit 160B causes the frequency of the drive control signal DRV2 (and thus the switching frequency f _SW2 of the output stage circuit 180B) to match or approximate the reference frequency f _CLK .

Although it is not clear from FIG. 8, the output terminals 254A and 254B may be connected to each other.

<<Third Embodiment>>
A third embodiment of the present disclosure will be described. A part or all of the DC/DC converter 10 in FIG. 1 and a part or all of the DC/DC converter 20 in FIG. 8 are formed by a semiconductor integrated circuit on a semiconductor substrate, and the semiconductor integrated circuit is made of resin. A semiconductor device may be configured by encapsulating it in a housing (package). FIG. 9 is an external perspective view of a semiconductor device 500 according to the third embodiment.

The semiconductor device 500 includes the above-described semiconductor integrated circuit and a casing housing the semiconductor integrated circuit as main components, and a plurality of external terminals are provided to the casing so as to be exposed from the casing. Although FIG. 9 takes as an example a case where the semiconductor device 500 has a casing (package) called QFN (Dual Flatpack No-leaded), the casing of the semiconductor device 500 may be of any type. The number of external terminals of semiconductor device 500 is also arbitrary.

Among the blocks constituting the DC/DC converter 10 in FIG. Each block referred to in 1 is formed by a semiconductor integrated circuit of a semiconductor device 500, and when realizing the DC/DC converter 10 of _FIG . Connect externally.

Among the blocks constituting the DC/DC converter 20 in FIG. Each block referenced in 200B is formed by the semiconductor integrated circuit of the semiconductor device 500, and when realizing the DC/DC converter 20 of FIG. Connect _OUT1 and C _OUT2 externally.

That is, the semiconductor integrated circuit of the semiconductor device 500 is provided with a circuit that can configure either the DC/DC converters 10 or 20, and the same semiconductor core (semiconductor chip on which the semiconductor integrated circuit is formed) can perform DC/DC converters. /DC converters 10 and 20 can be configured. When configuring the DC/DC converter 10 of FIG. 1, the error voltage generation section 110B, PWM comparator 130B, and PLL circuit 160B of FIG. 8 are not operated (although they are provided in the semiconductor integrated circuit). The DC/DC converter 10 may be configured by realizing the connection state of each circuit shown in FIG. 1 without operating the circuits significantly). On the other hand, when configuring the DC/DC converter 20 of FIG. 8, the phase control logic 140 and current balance signal generation section 210 of FIG. 8), the DC/DC converter 20 may be configured by realizing the connection state of each circuit shown in FIG.

At the manufacturing stage of the semiconductor device 500, a dedicated semiconductor device 500 for configuring the DC/DC converter 10 (hereinafter referred to as a multi-phase dedicated semiconductor device 500) and a dedicated semiconductor device 500 for configuring the DC/DC converter 20 are manufactured. A semiconductor device 500 (hereinafter referred to as a single-phase dedicated semiconductor device 500) may be configured (manufactured) separately.

The plurality of external terminals provided in the multi-phase dedicated semiconductor device 500 include input terminals 251A and 251B, switch terminals 252A and 252B, and ground terminals 253A and 253B in FIG. 1, and further include a feedback input terminal. In the multi-phase dedicated semiconductor device 500, the feedback input terminal is connected to nodes 115, 124A, and 124B in FIG. 1 as an external terminal to receive the feedback voltage V _FB .

The plurality of external terminals provided in the single-phase dedicated semiconductor device 500 include input terminals 251A and 251B, switch terminals 252A and 252B, and ground terminals 253A and 253B in FIG. 8, and further include a feedback input terminal. In the single-phase dedicated semiconductor device 500, first and second feedback input terminals are provided as feedback input terminals, and the first feedback input terminal is connected to nodes 115A and 124A in _{FIG. 8 as an external terminal to receive the feedback voltage V FB1} . The second feedback input terminal is connected to nodes 115B and 124B in FIG. 8 as an external terminal to receive the feedback voltage V _FB2 .

A multi-phase/single-phase switching type semiconductor device 500 may be configured (manufactured). The multi-phase/single-phase switching type semiconductor device 500 operates in a multi-phase mode or a single-phase mode based on a setting signal supplied from outside the semiconductor device 500 (for example, based on the level of a voltage applied to a certain external terminal). Operate selectively. In the multi-phase/single-phase switching type semiconductor device 500, either the circuit configuration of FIG. 1 or the circuit configuration of FIG. 8 can be selectively formed using a switching function of a multiplexer or a switch (not shown). Based on the setting signal, the circuit configuration shown in FIG. 1 may be formed within the semiconductor device 500 in the multi-phase mode, while the circuit configuration shown in FIG. 8 may be formed within the semiconductor device 500 in the single-phase mode.

Multi-phase/single-phase switching type semiconductor device 500 includes input terminals 251A and 251B, switch terminals 252A and 252B, and ground terminals 253A and 253B in FIG. 8, and further includes first and second feedback input terminals.
When the DC/DC converter 10 of FIG. 1 is configured using a multi-phase/single-phase switching type semiconductor device 500, the semiconductor device 500 is operated in a multi-phase mode and feedback is sent to the first feedback input terminal. Give voltage V _FB . When operating in multiphase mode, nodes 115, 124A, and 124B of FIG. 1 are connected to a first feedback input terminal within semiconductor device 500.
When the DC/DC converter 20 of FIG. 8 is configured using a multi-phase/single-phase switching type semiconductor device 500, the semiconductor device 500 is operated in a single-phase mode, and the first and second feedback inputs are Feedback voltages V _FB1 and V _FB2 are applied to the terminals, respectively. When operating in single phase mode, nodes 115A and 124A of FIG. 8 are connected to a first feedback input terminal, and nodes 115B and 124B of FIG. 8 are connected to a second feedback input terminal within semiconductor device 500.

Note that after the DC/DC converter 10 or 20 using the multi-phase/single-phase switching type semiconductor device 500 is activated, the operation mode may be switched between the multi-phase mode and the single-phase mode. In this case, even if there is a switch from single-phase mode to multi-phase mode, the switching phase difference between the first and second phases is ensured by the method described in the first embodiment.

Further, in the semiconductor device 500, the resistors 112 and 113 or the resistors 112A and 113A may be provided outside the semiconductor device 500 and connected externally to the semiconductor device 500, or the output stage circuits 180A and 180B may be connected to the semiconductor device 500. It may be provided outside the semiconductor device 500 and externally connected to the semiconductor device 500.

<<Fourth embodiment>>
A fourth embodiment of the present disclosure will be described. The DC/DC converter 10 can be used as a power supply device for any electronic device. In particular, for example, the DC/DC converter 10 is suitable for applications where high load response performance is required due to large load fluctuations, and where miniaturization is also strongly required. The DC/DC converter 10 described in this embodiment may be configured using a semiconductor device 500.

As an example, the DC/DC converter 10 can be used as a power supply device for an SSD (Solid State Drive). An SSD is a recording device that uses a semiconductor memory as a recording medium, and includes a semiconductor memory and a memory controller that controls reading and writing of data to the semiconductor memory as main components. The power consumption of memory controllers varies. That is, when the memory controller is used as the load of the power supply device (corresponding to the load LD in FIG. 1), the load fluctuation is large. By using the output voltage V _OUT of the DC/DC converter 10 as the power supply voltage for such a memory controller, high load response performance can be provided.

Further, by employing a multi-phase drive method, small coils can be used as the coils L1 and L2 (see FIG. 1), so it is possible to reduce the overall size of the SSD. The miniaturization of SSDs requires the use of low-profile components (components with low height). A low-profile coil tends to have a large DCR (direct current resistance). If a single-phase drive is performed using only one low-profile coil and a large current (a large current required by a memory controller: 12 A, for example) is passed through the single coil, heat generation increases and the power supply efficiency decreases significantly. If a multi-phase drive system is adopted as in the DC/DC converter 10, the load current is shared among a plurality of coils, so low-profile components can be used without problems.

When using an SSD as a storage device for a server device in a data center, etc., power efficiency is extremely important from the perspective of constant operation (24-hour operation), but it is possible to achieve high power efficiency by introducing the above-mentioned current balance technology. can. Of course, the DC/DC converter 10 can also be used for an SSD installed in a personal computer or the like.

<<Fifth embodiment>>
A fifth embodiment of the present disclosure will be described. In the first embodiment, the DC/DC converter 10 having a circuit for two phases has been described as an example of a step-down multi-phase DC/DC converter. A converter may also be configured. Here, n is an arbitrary integer of 2 or more.

Considering the case where n=3, a step-down three-phase DC/DC converter that is a step-down multi-phase DC/DC converter including circuits for three phases will be described. FIG. 10 schematically shows a partial configuration of a step-down three-phase DC/DC converter. The step-down three-phase DC/DC converter includes each component of the DC/DC converter 10 shown in FIG. 1, as well as a third phase pulse wave generation section, TON setting section, output stage drive section, output stage circuit, As a current sensor, a protection circuit, and a coil, a pulse wave generation section 120C, a TON setting section 150C, an output stage drive section 170C, an output stage circuit 180C, a current sensor 190C, a protection circuit 200C, and a coil L3 are provided (however, the current sensor 190C and protection circuit (Circuit 200C is not shown). The configuration and operation of each circuit in the third phase is the same as that of each circuit in the first or second phase. The configuration and operation of the 3-phase DC/DC converter will be explained.

The output stage circuit 180C has the same configuration as the output stage circuit 180A, and includes an output transistor 181C and a synchronous rectification transistor 182C corresponding to the output transistor 181A and the synchronous rectification transistor 182A. The output stage circuit 180C switches the input voltage V _IN to generate a rectangular waveform switch voltage V _LX3 at the switch terminal 252C corresponding to the connection node between the output transistor 181C and the synchronous rectification transistor 182C. A coil L3 is provided between the switch terminal 252C and the output terminal 254. Note that, similar to the DC/DC converter 10, in a step-down three-phase DC/DC converter, a coil L1 is provided between the switch terminal 252A where the switch voltage V _LX1 is generated and the output terminal 254, and the switch where the switch voltage V _LX2 is generated. A coil L2 is provided between the terminal 252B and the output terminal 254.

The pulse wave generation section 120C has the same configuration as the pulse wave generation section 120A, and generates a feedback pulsation voltage V _FBIN3 that fluctuates in conjunction with the switch voltage V _LX3 based on the feedback voltage V _FB .

In the step-down 3-phase DC/DC converter, the PWM comparator 130 uses the average voltage of the feedback ripple current voltages V _FBIN1 , V _FBIN2 and V _FBIN3 as the voltage V _{FBIN_AVE} instead of the average voltage of the feedback ripple current voltages V _FBIN1 and V _FBIN2 . The signal COMP is generated by the operation described in the first embodiment. Each up edge timing in this signal COMP represents the on timing of the output transistor 181A, 181B, or 181C.

In the step-down three-phase DC/DC converter, as shown in FIG. 11, the phase control logic 140 sequentially and cyclically converts a plurality of pulses indicating a plurality of on-timings included in the signal COMP into signals COMP1 and COMP2 one by one. and COMP3 to generate signals COMP1 to COMP3. To explain more clearly, the following operations are performed. That is, in the step-down three-phase DC/DC converter, the phase control logic 140 basically keeps the levels of the signals COMP1 to COMP3 at a low level, and when the (3×i+1)th up edge occurs in the signal COMP, the signal An up edge is also generated in the signal COMP1 in synchronization with the up edge of COMP, and the signal COMP1 is set to high level for a predetermined minute time and then returned to low level, and the (3×i+2)th up edge is generated in the signal COMP. When this occurs, an up edge is also generated in the signal COMP2 in synchronization with the up edge of the signal COMP, and the signal COMP2 is set to a high level for a predetermined minute period and then returned to a low level, and the signal COMP2 is set to the (3×i)th time. When an up edge occurs, an up edge is also generated in the signal COMP3 in synchronization with the up edge of the signal COMP, and the signal COMP3 is set to a high level for a predetermined minute time and then returned to a low level (here, i is an integer).

TON setting units 150A, 150B, and 150C generate drive control signals DRV1, DRV2, and DRV3 based on signals COMP1, COMP2, and COMP3, respectively. The method of generating the drive control signal DRV3 based on the signal COMP3 is the same as the method of generating the drive control signal DRV1 based on the signal COMP1.

The operation of PLL circuit 160 is as described above. However, in the step-down 3-phase DC/DC converter shown in FIG. 10, the output signal S _PLL of the PLL circuit 160 is supplied not only to the TON setting sections 150A and 150B but also to the TON setting section 150C, so that the drive control signals DRV1, The frequencies of DRV2 and DRV3 (and thus the switching frequencies of output transistors 181A, 181B and 181C) are brought to match or approach the reference frequency _{f_CLK} .

Output stage drive units 170A, 170B and 170C perform switching drive of output stage circuits 180A, 180B and 180C based on drive control signals DRV1, DRV2 and DRV3. Similar to the output stage drive units 170A and 170B, the output stage drive unit 170C sets the output stage circuit 180C to a high output state during the high level section of the drive control signal DRV3, and outputs the output stage circuit 180C to the high level state during the low level section of the drive control signal DRV3. 180C is set to output low state.

As a result, since "360°/n=360°/3=120°", the output stage circuits 180A to 180C are switched and driven with a phase difference of 120° (or a phase difference close to 120°). Thus, an ideal three-phase drive can be realized while using a control method similar to the constant-on-time control method.

The current balance signal generation unit 210 generates current balance signals S _CB1 , S _CB2 and S _CB3 based on the first, second and third target currents detected by the current sensors 190A, 190B and 190C (in FIG. 10 (Each current sensor is not shown). The first, second, and third target currents are currents flowing through the switch terminals 252A, 252B, and 252C, respectively, and correspond to coil currents I _L1 , I _L2 , and I _L3 . Note that the coil current _IL3 represents the current flowing through the coil L3. The TON setting units 150A, 150B, and 150C set the on-times _TON1 , _TON2 , and _TON3 (high-level sections of the drive control signals DRV1, _DRV2 , and _DRV3 ) as necessary based on the current balance signals _SCB1 , SCB2, and SCB3. By correcting the length), the difference between the first to third target currents is reduced. The method of this reduction is the same as that described in the first embodiment (the first embodiment shows the method of reduction in the case of "n=2"). Note that the on time _TON3 represents the time during which the output stage circuit 180C is in the output high state (that is, the time during which the output transistor 181C is in the on state) in each switching cycle of the output stage circuit 180C.

<<Sixth embodiment>>
A sixth embodiment of the present disclosure will be described. In the sixth embodiment, modification techniques and application techniques applicable to the first to fifth embodiments will be described.

In the DC/DC converter shown in each of the embodiments described above (for example, the DC/DC converter 10 in FIG. 1), a synchronous rectification method is adopted in the output stage circuit, but a diode rectification method is adopted. Also good. That is, each synchronous rectifier transistor may be replaced with a rectifier diode. When this replacement is performed, the output transistor is naturally the only transistor whose on/off is controlled in each output stage circuit.

Although a DC/DC converter to which both phase difference securing technology and current balance technology are applied has been described, in the step-down multi-phase DC/DC converter according to the present disclosure, only the phase difference securing technology may be implemented. Alternatively, only current balancing technology may be implemented.

For any signal or voltage, the relationship between high and low levels may be reversed as described above, without detracting from the spirit of the above.

The type of channel of the FET (field effect transistor) shown in each embodiment is merely an example, and an N-channel FET may be changed to a P-channel FET, or a P-channel FET may be changed to an N-channel FET. The configuration of the circuit containing the FET can be modified to change the type of FET. For example, a modification is possible in which the output transistors 181A and 181B in FIG. 1 are replaced with P-channel MOSFETs.

Any of the transistors mentioned above may be any type of transistor as long as no inconvenience occurs. For example, any transistors mentioned above as MOSFETs can be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, unless inconveniences arise. Any transistor has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

<<Consideration of the invention>>
Configuration examples of the present disclosure embodied in each of the above-described embodiments will be described. FIG. 12 shows a block diagram of a semiconductor device W according to one aspect of the present disclosure.

A semiconductor device W according to one aspect of the present disclosure (for example, corresponding to the semiconductor device 500 in FIG. 9) is a semiconductor device used in a step-down multiphase DC/DC converter that steps down an input voltage to generate an output voltage. _and ( _n is an integer of 2 or more), a switching control section that drives the switching of the first to nth output stage circuits with a phase difference provided in the switching drive of the first to nth output stage circuits, and In the type multi-phase DC/DC converter, the output voltage is generated by rectifying and smoothing the first to nth switch voltages, and the semiconductor device generates a feedback voltage (for example, V _FB ) according to the output voltage. an error voltage generating section that generates an error voltage (for example, _VERR ) according to the difference between a voltage proportional to the feedback voltage and a predetermined reference voltage; a feedback pulsating current voltage generation unit that generates first to nth feedback pulsating current voltages (for example, V _FBIN1 , V _FBIN2 ) that vary in conjunction with the first to nth switch voltages; an on-timing sequence generating section that generates an on-timing sequence consisting of a plurality of on-timings based on the feedback pulsating current voltage, and the switching control section generates the first to nth output stage circuits based on the on-timing sequence. A phase difference is provided in the switching drive of the first to n-th output stage circuits by sequentially driving the switching.

Hereinafter, the correspondence between the structure of the semiconductor device W and the structure of FIG. 1 will be explained as appropriate (the correspondence with the structure of FIG. 10 can be considered in the same way). The first to nth output stage circuits in the semiconductor device W correspond to the output stage circuits 180A and 180B in FIG. The switching control section in the semiconductor device W corresponds to a block including each portion referenced by reference numerals 140, 150A, 150B, 160, 170A, 170B, 190A, 190B, 200A, 200B, and 210 in FIG. A feedback input terminal in semiconductor device W corresponds to node 115 (124A, 124B) in FIG. The error voltage generation section in the semiconductor device W corresponds to the error voltage generation section 110 in FIG. In FIG. 1, the feedback pulsating current voltage generating section in the semiconductor device W is formed by pulse wave generating sections 120A and 120B. The on-timing sequence generation section in the semiconductor device W corresponds to the PWM comparator 130 in FIG. Since the on-timing sequence is defined by the output signal COMP of the PWM comparator 130, it can be understood that the on-timing sequence is generated by the PWM comparator 130.

In the semiconductor device W described above, for example, the first to nth output stage circuits are provided at the first to nth output stages provided between the input voltage application terminal and the first to nth switch terminals, respectively. The switching control section includes transistors (for example, 181A, 181B), and the switching control section includes an on-time setting section that sets the on-time (for example, T _ON1 , T _ON2 ) of each output transistor, and the setting contents and the on-timing sequence It is preferable to drive the first to nth output stage circuits by switching based on the following.

The on-time setting section in the semiconductor device W is formed by TON setting sections 150A and 150B in FIG. The PLL circuit 160 in FIG. 1 may be considered to be included in the components of the on-time setting section, or may be considered to be provided in the switching control section separately from the on-time setting section.

For example, in the above-described semiconductor device W, the on-timing sequence generating section is configured such that the level relationship between the error voltage and the average voltage (for example, V _{FBIN_AVE} ) of the first to n-th feedback pulsating voltages is from a first relationship to a first relationship. 2, the on-timing sequence is generated by setting the on-timing every time the on-timing changes, and the switching control section generates the on-timing sequence by setting the on-timings every time the on-timing changes. It is preferable to repeatedly turn on the n-output transistors one by one.

In the configuration of FIG. 1, a change from the first relationship to the second relationship corresponds to a change from "V _{FBIN_AVE} > _VERR " to "V _{FBIN_AVE} < _VERR ", but from "V _{FBIN_AVE} < _VERR " to "V The circuit configuration and operation of FIG. 1 may be modified so that the change to _{``FBIN_AVE} > _VERR '' corresponds to the change from the first relationship to the second relationship. In the configuration of FIG. 1, since "n=2", one output transistor 181A and one output transistor 181B is included in the on-timing sequence and at two consecutive on-timings (that is, at two consecutive up-edge timings in the signal COMP). After that, the output transistors 181A and 181B are sequentially turned on one by one again at the next two consecutive on timings. The following similar operations are repeated. The same applies to the case of “n≧3”.

For example, in the semiconductor device W described above, the on-time setting section specifies the on-period and off-period of the first to n-th output transistors based on the on-time settings of each output transistor and the on-timing sequence. The switching control unit generates first to nth drive control signals (for example, DRV1, DRV2) to turn on/off the first to nth output transistors according to the first to nth drive control signals. The on-time setting unit uses a PLL circuit to adjust the frequencies of the first to nth drive control signals corresponding to the switching frequencies of the first to nth output transistors to match a predetermined reference frequency. Alternatively, the on-time of each output transistor may be set to be close to each other.

In FIG. 1, the switching drive section in the semiconductor device W is formed by output stage drive sections 170A and 170B.

Further, for example, in the above semiconductor device W, the switching control section includes a current detection section that detects the first to nth target currents flowing through the first to nth switch terminals, and a current detection section that detects the first to nth target currents flowing through the first to nth switch terminals, and a current balance signal generation unit that generates a current balance signal (for example, S _CB1 , S _CB2 ) according to the magnitude relationship of the first to nth target currents, and the on-time setting unit The difference between the first to nth target currents may be reduced by adjusting the on-time of each output transistor based on .

The current detection section in the semiconductor device W is formed by current sensors 190A and 190B in FIG. The current balance signal generation section in the semiconductor device W corresponds to the current balance signal generation section 210 in FIG.

The embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values shown in the above-mentioned explanatory text are merely examples, and it goes without saying that they can be changed to various numerical values.

10 DC/DC converter 110 Error voltage generation section 120 Pulse wave generation section 130 PWM comparator 140 Phase control logic 150A, 150B TON setting section 160 PLL circuit 170A, 170B Output stage drive section 180A, 180B Output stage circuit 181A, 181B Output transistor 182A , 182B Synchronous rectification transistors 190A, 190B Current sensors 200A, 200B Protection circuit 210 Current balance signal generation section L1, L2 Coil C _OUT output capacitor

Claims (7)

A semiconductor device used in a step-down multiphase DC/DC converter that steps down an input voltage and generates an output voltage based on a plurality of switch voltages, the semiconductor device comprising:
a plurality of output stage circuits that generate the plurality of switch voltages at the plurality of switch terminals by switching the input voltage;
an error voltage generation unit that generates an error voltage according to a difference between a voltage proportional to a feedback voltage according to the output voltage and a predetermined reference voltage;
a feedback pulsating voltage generation unit that generates a plurality of feedback pulsating voltages that vary in conjunction with the plurality of switch voltages based on the feedback voltage;
an on-timing sequence generation unit that generates an on-timing sequence consisting of a plurality of on-timings based on the error voltage and the plurality of feedback pulsating voltages;
A semiconductor device comprising: a switching control unit that sequentially switches and drives the plurality of output stage circuits based on the on-timing sequence to provide a phase difference to the switching drive of the plurality of output stage circuits. In each output stage circuit, an output transistor is provided between the input voltage application terminal and the corresponding switch terminal, so that the plurality of output stage circuits are provided with a plurality of output transistors,
2. The semiconductor according to claim 1, wherein the switching control section includes an on-time setting section that sets an on-time of each output transistor, and drives the plurality of output stage circuits in switching based on the setting contents and the on-timing sequence. Device. The on-timing sequence generation unit sets the on-timing every time a level relationship between the error voltage and an average voltage of the plurality of feedback pulsating voltages changes from a first relationship to a second relationship. generate a column,
3. The semiconductor device according to claim 2, wherein the switching control section repeatedly performs an operation of sequentially turning on the plurality of output transistors one by one at a plurality of consecutive on-timings included in the on-timing sequence. The on-time setting section generates a plurality of drive control signals that specify on-periods and off-periods of the plurality of output transistors based on the setting contents of the on-time of each output transistor and the on-timing sequence,
The switching control section includes a switching drive section that turns on/off the plurality of output transistors according to the plurality of drive control signals,
The on-time setting section uses a PLL circuit to set the on-time of each output transistor so that the frequencies of the plurality of drive control signals corresponding to the switching frequencies of the plurality of output transistors match or approach a predetermined reference frequency. The semiconductor device according to claim 2 or 3. The switching control unit includes a current detection unit that detects a plurality of target currents flowing through the plurality of switch terminals, and generates a current balance signal according to a magnitude relationship of the plurality of target currents based on a detection result of the current detection unit. a current balance signal generation unit,
5. The semiconductor device according to claim 2, wherein the on-time setting section reduces the difference between the plurality of target currents by adjusting the on-time of each output transistor based on the current balance signal. The plurality of target currents include first and second target currents, and the plurality of output transistors include a first output transistor connected to a switch terminal through which the first target current flows and a switch terminal through which the second target current flows. a second output transistor connected;
The on-time setting section includes:
When the first target current is larger than the second target current, the on-time of the first output transistor is corrected to decrease while the on-time of the second output transistor is corrected to be increased based on the current balance signal;
When the first target current is smaller than the second target current, the on-time of the first output transistor is corrected to increase while the on-time of the second output transistor is corrected to decrease based on the current balance signal. The semiconductor device according to item 5. A semiconductor device according to any one of claims 1 to 6 ,
a plurality of coils provided between an output terminal to which the output voltage is applied and the plurality of switch terminals;
A step-down multiphase DC/DC converter, comprising: an output capacitor provided between the output terminal and ground;
A step-down multiphase DC/DC converter that generates the output voltage at the output terminal by rectifying and smoothing the plurality of switch voltages using the plurality of coils and the output capacitor.

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