CN119582617A

CN119582617A - Multiphase power supply and its control circuit

Info

Publication number: CN119582617A
Application number: CN202411876386.2A
Authority: CN
Inventors: 臧鹏
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2024-12-18
Filing date: 2024-12-18
Publication date: 2025-03-07

Abstract

The present application discloses a multi-phase power supply and its control circuit, including: a feedback control circuit for generating a phase-cutting signal according to a feedback signal of an output voltage and a reference voltage signal; a switch control circuit for generating a plurality of frequency-dividing signals according to the phase-cutting signal, and controlling the main power tube of a corresponding power stage circuit to be turned on according to the logic states of the plurality of frequency-dividing signals; and a conduction time control circuit for generating a shutdown trigger signal when the conduction time of the main power tube of the triggered power stage circuit reaches a set time, and the switch control circuit controls the main power tube of the triggered power stage circuit to be turned off according to the shutdown trigger signal and the plurality of frequency-dividing signals. The multi-phase power supply of the present application can realize phase-shifting control between a plurality of power stage circuits by using only one control loop, and has a simple circuit structure, which is conducive to simplifying circuit design and reducing circuit cost.

Description

Multiphase power supply and control circuit thereof

Technical Field

The invention relates to the technical field of switching power supplies, in particular to a multiphase power supply and a control circuit thereof.

Background

The exponential growth in internet of things (IoT) cloud service scale has driven significant advances in data centers, networks, and telecommunication devices, while the ever-increasing data and information presents new challenges to the processing efficiency of servers in the data centers, and therefore how to efficiently power and dissipate heat for these devices while minimizing power consumption is an important topic in the current power technology field.

Multiphase power supplies are techniques that implement regulation control of the power supply by connecting multiple power stage circuits in parallel and distributing the switching modulation process to the different phases. The PWM (pulse width modulation ) signals between phases in a multiphase power supply may be the same or staggered by a certain phase so that the frequency of fluctuation seen by the output and input is the product of the switching frequency and the number of phases in each phase, thereby reducing the need for filter capacitors and current surge to the input, and accelerating the response to load changes.

Fig. 1 shows a schematic circuit diagram of a multiphase power supply according to the prior art. As shown in fig. 1, a conventional multiphase power supply 100 is comprised of a multiphase power supply controller 110, a plurality of parallel power stage circuits 101-104 (4-phase multiphase power supply is illustrated in fig. 1 as an example), and a feedback control circuit 120. Each power stage circuit comprises a driver, switching tubes T1 and T2, an inductor Lx and an output capacitor Cout, the switching tubes T1 and T2 are connected between an input voltage Vin and ground, a first end of the inductor Lx is connected to an intermediate node of the switching tubes T1 and T2, a second end is connected to a first end of the output capacitor Cout, and a second end of the output capacitor Cout is grounded. The drivers in the power stage circuits 101-104 each receive the PWM signals PWM1-PWM4 from the multiphase power controller 110, and control the corresponding transistors to turn on and off according to the received PWM signals, charge the output capacitor Cout of the current phase to generate the current phase output voltages Vo1-Vo4, and combine the output voltages Vo1-Vo4 into an output voltage Vout to drive the load.

The multiphase power supply controller 110 comprises a plurality of PWM controllers 111-114, each PWM controller 111-114 determining the working order of the multiphase power stage circuits 101-104 based on the feedback signal FB of the feedback control circuit 120, respectively, to provide the pulse width modulated signals PWM1-PWM4. The existing multiphase power supply controller needs PWM controllers with the same number as the power level circuits, so that the problems of complex structure, large circuit scale and high circuit cost of the controller exist, and the problem of matching degree among the PWM controllers also exists, thereby influencing the accuracy of current balance of each phase of the multiphase power supply.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a multiphase power supply and a control circuit thereof, which can reduce the circuit scale and cost of a controller and improve the problem of current balance of each phase.

According to one aspect of the invention, a control circuit of a multiphase power supply is provided, the multiphase power supply comprises a plurality of parallel power stage circuits, the control circuit comprises a feedback control circuit, a switch control circuit and a conduction time control circuit, the feedback control circuit is used for generating phase-cut signals according to feedback signals of output voltages and reference voltage signals, the switch control circuit is used for controlling working time sequences of the power stage circuits according to the phase-cut signals, the switch control circuit is used for generating a plurality of frequency division signals according to the phase-cut signals and controlling the conduction of main power tubes of the corresponding power stage circuits according to logic states of the frequency division signals, and the conduction time control circuit is used for generating a turn-off trigger signal when the conduction time of the main power tubes of the triggered power stage circuits reaches a set time, and the switch control circuit is used for controlling the turn-off of the main power tubes of the triggered power stage circuits according to the turn-off trigger signal and the frequency division signals.

Optionally, the switch control circuit comprises a frequency division module, a conduction control module, a synchronous detection module and a turn-off control module, wherein the frequency division module is used for performing frequency division operation on the phase-cut signals to obtain a plurality of frequency division signals, the conduction control module is used for performing logic operation on the plurality of frequency division signals to obtain a plurality of conduction control signals, the plurality of conduction control signals are respectively used for controlling conduction of main power tubes of corresponding power level circuits, the synchronous detection module is used for generating synchronous signals of the plurality of frequency division signals when the turn-off trigger signals are detected, and the turn-off control module is used for performing logic operation on the plurality of synchronous signals to obtain a plurality of turn-off control signals, and the plurality of turn-off control signals are respectively used for controlling turn-off of the main power tubes of the corresponding power level circuits.

Optionally, the frequency dividing module comprises a plurality of cascaded first D flip-flops, wherein the data end and the negative output end of each of the plurality of first D flip-flops are connected, the negative output end is used for outputting each of the plurality of frequency dividing signals, the clock end of the first D flip-flop in the plurality of first D flip-flops is used for receiving the phase-cut signal, and the clock ends of the other first D flip-flops are connected with the negative output end of the previous first D flip-flop.

Optionally, the synchronous detection module comprises a plurality of second D triggers, the second D triggers correspond to the first D triggers, a data end of each second D trigger is used for receiving a corresponding frequency division signal, a clock end is used for receiving the turn-off trigger signal, and an output end is used for providing a corresponding synchronous signal.

Optionally, the turn-on control module includes a plurality of first logic units, an input end of each first logic unit is used for receiving the plurality of frequency division signals, an output end of each first logic unit is used for generating a turn-on control signal of a corresponding power stage circuit, and the turn-off control module includes a plurality of second logic units, an input end of each second logic unit is used for receiving a plurality of synchronous signals, and each second logic unit is used for generating a turn-off control signal of the corresponding power stage circuit.

Optionally, the first logic unit and the second logic unit include at least one of an and gate, a not gate, or a nor gate.

Optionally, when the number of the plurality of power stage circuits is odd, the plurality of first D flip-flops further includes a reset terminal, and the conduction control module further includes a third logic unit, where the third logic unit is configured to provide an effective reset signal to the reset terminal of the plurality of first D flip-flops to reset the plurality of first D flip-flops when the plurality of frequency division signals are in a preset logic state.

Optionally, the feedback control circuit comprises a first error amplifier for generating an error signal according to the feedback signal and the reference voltage signal, an integrator for performing integral operation on a difference between the feedback signal and the reference voltage signal to generate an integral signal, a slope compensation module for generating a slope compensation signal according to a switch node voltage of the triggered power stage circuit, an adder for obtaining a superposition signal of the error signal, the integral signal and the slope compensation signal, and a first comparator for comparing the superposition signal with a first reference voltage to generate the phase-cut signal.

Optionally, the slope compensation module comprises a first switch array, a filtering unit and a second error amplifier, wherein the first switch array is connected with the switch node voltage of the power stage circuits, the second end of the first switch array is connected with the first node and used for providing the switch node voltage of the triggered power stage circuits in the power stage circuits to the first node, the filtering unit is used for filtering the voltage at the first node to generate a first ripple signal and a second ripple signal, and the second error amplifier is used for generating the slope compensation signal according to the first ripple signal and the second ripple signal.

The filtering unit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a fourth resistor, a second capacitor and a second capacitor, wherein the first resistor and the second resistor are connected in series between the first node and the ground, the first end of the third resistor is connected with the second node between the first resistor and the second resistor, the first end of the first capacitor is connected with the third node, the second end of the first resistor is connected with the ground, the first end of the fourth resistor is connected with the fourth node, the second end of the second capacitor is connected with the ground, the positive input end of the second error amplifier is connected with the third node to receive the first ripple signal, and the negative input end of the second error amplifier is connected with the fourth node to receive the second ripple signal.

Optionally, the on-time control circuit sets the set time according to an input voltage and an output voltage of the multiphase power supply.

Optionally, the on-time control circuit comprises a fifth resistor, a third capacitor, a second comparator and a third switch, wherein the first end of the fifth resistor is connected with the input voltage, the first end of the third capacitor is connected with the second end of the fifth resistor, the second end of the third capacitor is connected with the ground, the positive input end of the second comparator is connected with a middle node of the fifth resistor and the third capacitor, the negative input end of the second comparator is connected with the output voltage, the second comparator is used for generating the turn-off trigger signal when the voltage of the third capacitor rises to the output voltage, the first end of the third capacitor is connected with the first end of the third capacitor, the second end of the third capacitor is connected with the first reference voltage, the third end of the third capacitor is connected with the second reference voltage, the third switch is used for floating when the main power tube of the triggered power stage circuit is turned on, so that the input voltage charges the third capacitor, and the voltage of the third capacitor is reset to the first reference voltage or the second reference voltage when the main power tube of the triggered power stage circuit is turned off.

Optionally, the first reference voltage is a ground potential, the second reference voltage is obtained through a switch node voltage of a currently triggered power stage circuit, and the third switch is further configured to reset the voltage of the third capacitor to the second reference voltage when the multiphase power supply operates in a continuous conduction mode, and reset the voltage of the third capacitor to the first reference voltage when the multiphase power supply operates in an intermittent conduction mode.

According to another aspect of the present invention there is provided a multiphase power supply comprising a plurality of parallel power stage circuits, and a control circuit as described above.

In summary, in the multiphase power supply based on the COT control architecture provided by the embodiment of the present invention, the phase-dislocation control between the multiple power stage circuits can be achieved by only using one control loop, and there is no need to set an independent compensation network and current sampling circuit in each power stage circuit, so that the circuit structure is simple, and the circuit design is simplified and the circuit cost is reduced. In addition, the invention controls the conduction time of a plurality of power stage circuits by using one conduction time control circuit, can ensure the consistent direct current quantity of each phase of inductance current, and is beneficial to improving the stability and reliability of the system.

Furthermore, the control circuit of the multiphase power supply provided by the embodiment of the invention introduces the current sampling information of the power stage circuits into the feedback control circuit and/or the conduction time control circuit, and adaptively adjusts the triggering time and/or the charging time of each power stage circuit according to the current sampling information, so that the current balance among a plurality of power stage circuits is realized, and the stability and the performance of the system are improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic circuit diagram of a multiphase power supply according to the prior art.

Fig. 2 shows a schematic circuit diagram of a multiphase power supply according to an embodiment of the invention.

Fig. 3 shows a schematic circuit diagram of a driver in a respective power stage circuit according to an embodiment of the invention.

Fig. 4 shows a schematic block diagram of a switch control circuit according to an embodiment of the present invention.

Fig. 5 shows a schematic circuit diagram of a switch control circuit according to a first embodiment of the present invention.

Fig. 6 shows a schematic waveform diagram of a switch control circuit according to a first embodiment of the present invention.

Fig. 7 shows a schematic circuit diagram of a switch control circuit according to a second embodiment of the present invention.

Fig. 8 shows a schematic waveform diagram of a switch control circuit according to a second embodiment of the present invention.

Fig. 9 shows a schematic circuit diagram of a feedback control circuit according to an embodiment of the invention.

Fig. 10 shows a schematic circuit diagram of a slope compensation module according to an embodiment of the invention.

Fig. 11 shows a schematic waveform diagram of a slope compensation module according to an embodiment of the invention.

Fig. 12 shows a schematic circuit diagram of a conduction time control circuit according to an embodiment of the present invention.

Fig. 13 shows a schematic waveform diagram of an on-time control circuit according to an embodiment of the invention.

Fig. 14 shows a waveform diagram of 2 power stage circuits in a multiphase power source to achieve current sharing according to an embodiment of the invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.

It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

In the present application, the switching transistor is a transistor that operates in a switching mode to provide a current path, and includes one selected from a bipolar transistor or a field effect transistor. The first end and the second end of the switching tube are respectively a high potential end and a low potential end on a current path, and the control end is used for receiving a driving signal to control the switching tube to be turned on and off.

The invention may be embodied in various forms, some examples of which are described below.

Fig. 2 shows a schematic circuit diagram of a multiphase power supply according to an embodiment of the invention. The multiphase power supply comprises N power stage circuits and a control circuit which are arranged in parallel, wherein N is an integer larger than 1, the N power stage circuits share the same control loop, and the control circuit is used for controlling the working time sequence and the charging time of the N power stage circuits so as to jointly provide an output voltage Vout.

Specifically, referring to fig. 2, the multiphase power supply 200 includes N power stage circuits 201-20N (N is the number of phases of the multiphase power supply set, and N is an integer greater than 1) arranged in parallel, and each power stage circuit is exemplified as a buck converter.

Taking the power stage circuits 201 as an example, each power stage circuit includes a driver DRV, a switching tube T1 (also referred to as a high-side switching tube), a switching tube T2 (also referred to as a low-side switching tube), and an inductor Lx. The drains of the high-side switching tube T1 and the low-side switching tube T2 are connected to each other, the common end of the two forms a switching node SW, the source of the low-side switching tube T2 is connected to the ground, and the source of the high-side switching tube T1 is connected to the input voltage Vin. The first end of the inductor Lx is connected to the switching node Lx, and the second end of the inductor Lx is connected to the output voltage Vout. The driver DRV in each power stage circuit 201-20N receives a control signal from the control circuit, and controls the on and off of the corresponding switching tube according to the received control signal. It should be appreciated that in this embodiment, the high-side switching transistor T1 is a main power transistor, the low-side switching transistor T2 is a synchronous rectifying transistor, and the switching transistors T1 and T2 may be any type of field effect transistor, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and may be any other type of field effect and/or other type of transistor within the scope of the teachings of the present invention, as known to those skilled in the art.

It should be appreciated that although each power stage circuit may be understood with reference to the structure of power stage circuit 201 in fig. 2. And in this embodiment, each phase inductance corresponding to each of the N power stage circuits 201-20N may be separate or may be coupled to each other (e.g., a first phase inductance and a second phase inductance are coupled; a third phase inductance and a fourth phase inductance are coupled, and so on). Meanwhile, although the power stage circuit 201 is described as having a Buck topology (Buck), the aspects of the present invention may be employed for any type of topology design, such as Boost (Boost), flyback (Flyback), buck-Boost (Buck-Boost), cuk, sepic, zeta, etc.

The multiphase power supply 200 further comprises an output capacitor Cout, which is arranged between the output terminal of the multiphase power supply 200 and ground to generate an output voltage Vout across it.

Specifically, the control circuit includes a feedback control circuit 210, a switch control circuit 220, and a conduction time control circuit 230. The feedback control circuit 210 is configured to generate a phase-cut signal LOOP according to the feedback signal FB of the output voltage Vout and the reference voltage signal VREF. Illustratively, the multiphase power supply is controlled using any existing constant on-time Control (COT) scheme under which the feedback control circuit 210 is implemented in a variety of ways. For example, in one embodiment, the reference voltage signal VREF is directly compared with the feedback signal FB to generate the phase-cut signal LOOP. In another embodiment, the error between the reference voltage signal VREF and the feedback signal FB is compensated to obtain a feedback compensation signal, and the feedback compensation signal is compared with a current feedback signal representing a trend of variation of the sum of the inductor currents of each phase, so as to generate the phase-cut signal LOOP, where the current feedback signal may be a current sampling signal obtained by sampling and representing the inductor currents of each phase, or may be a current ripple signal simulating the variation of the inductor currents of each phase, that is, any control manner and variations of COT in the prior art may be applied thereto. In addition, other control modes of the power converter in the prior art, such as adaptive on-time control (compared with COT, the on-time Ton is not fixed, but is adjusted according to the input voltage and/or the output voltage), are also suitable for the present scheme, that is, the control mode is not limited by the present invention.

The switch control circuit 220 is configured to control the operation timings of the N power stage circuits 201-20N according to the phase-cut signal LOOP. The switch control circuit 220 is configured to generate M frequency division signals (not shown in the figure) according to the phase-cut signal LOOP, where M is an integer greater than 0, and sequentially trigger the N power stage circuits 201-20N according to the logic states of the M frequency division signals, and generate corresponding on control signals SETi (i=1, 2,3. The conduction control signal SET is used for controlling conduction of the main power tube T1 of the corresponding power stage circuit. In one exemplary embodiment, the period of the M divided signals is incremented by a binary weight from low to high, and each divided signal corresponds to each bit of a multi-bit binary number. It should be noted that the present invention is not limited thereto, and in other embodiments, M divided signals may be in one-to-one correspondence with N power stage circuits, and each divided signal is used to control a corresponding power stage circuit.

The on-time control circuit 230 is configured to start timing when the main power tube T1 of the triggered power stage circuit is turned on, and generate an off trigger signal SHOT when the on-time of the main power tube T1 reaches a set time, and the switch control circuit 220 determines the position of the triggered power stage circuit according to the off trigger signal SHOT and the M frequency division signals, and generates a corresponding off control signal rsti (i=1, 2,3. The turn-off control signal RST is used for controlling the turn-off of the main power tube T1 of the triggered power stage circuit and controlling the turn-on of the corresponding synchronous power tube T2.

Further, referring to fig. 3, the driver DRV in each power stage circuit of the embodiment of the present invention is configured to receive the corresponding on control signal SET and off control signal RST, and generate driving signals HG and LG according to logic processing of the on control signal SET and the off control signal RST, respectively, where the driving signal HG is provided to a control terminal of a high-side switching tube T1 of the corresponding power circuit and is used to control an on state of the switching tube T1, and the driving signal LG is provided to a control terminal of a low-side switching tube T2 to control an on state of the switching tube T2. Further, each driver includes an RS flip-flop 2011 AND an AND gate unit AND0. The SET terminal of the RS flip-flop 2011 is configured to receive a corresponding on control signal SET (e.g., the on control signal SET 1), the reset terminal of the RS flip-flop 2011 is configured to receive a corresponding off control signal RST (e.g., the off control signal RST 1), the positive output terminal of the RS flip-flop 2011 is configured to provide the driving signal HG (e.g., the driving signal HG1 of the switching tube T1 in the power stage circuit 201), the negative output terminal of the RS flip-flop 2011 is connected to the first input terminal of the AND gate unit AND0, the second input terminal of the AND gate unit AND0 is configured to receive an inverted signal of the zero-crossing detection signal ZC, AND the output terminal of the AND gate unit AND0 is configured to provide the driving signal LG (e.g., the driving signal LG1 of the switching tube T2 in the power stage circuit 201). Illustratively, the multiphase power supply 200 according to the embodiment of the present invention may further include a zero-crossing detection circuit, where the zero-crossing detection circuit is configured to detect the inductor current when each power stage circuit is triggered, and generate the zero-crossing detection signal ZC when the inductor current crosses zero.

Taking the power stage circuit 201 as an example, when the on control signal SET1 is active (e.g., the on control signal SET1 is at a high level), the RS flip-flop 2011 generates an active (e.g., a high level) driving signal HG to control the switch T1 and the switch T2 in the power stage circuit 201 to be turned on and off, and the input voltage Vin charges the inductor Lx in the power stage circuit 201. When the off control signal RST1 is valid (e.g., the off control signal RST1 is at a high level), the RS flip-flop 2011 generates an inactive (e.g., a low level) driving signal HG to control the switching tube T1 in the power stage circuit 201 to be turned off, AND meanwhile, since the negative output terminal of the RS flip-flop 2011 is at a high level, the AND gate unit AND0 outputs an active (e.g., a high level) driving signal LG1, so the switching tube T2 in the power stage circuit 201 is turned on AND the inductor Lx in the power stage circuit 201 starts to discharge. When the inductance current drops to zero, the zero-crossing detection signal ZC is active (e.g., high level), AND the AND gate unit AND0 outputs an inactive (e.g., low level) driving signal LG1, turning off the switching transistor T2 in the power stage circuit 201.

Fig. 4 shows a schematic block diagram of the switch control circuit 220 according to an embodiment of the present invention. As shown in fig. 4, the switch control circuit 220 of the embodiment of the present invention includes a frequency dividing module 221, a turn-on control module 222, a synchronization detecting module 223, and a turn-off control module 224. The frequency dividing module 221 is configured to perform a frequency dividing operation on the divided signal LOOP to generate M frequency divided signals. The conduction control module 222 is configured to detect logic states of the M frequency-divided signals, and generate a plurality of conduction control signals according to detection results. The synchronization detection module 223 is configured to generate M synchronization signals synchronized with the M frequency-divided signals after detecting the valid shutdown trigger signal SHOT. The turn-off control module 224 is configured to perform a logic operation on the M synchronization signals, generate a plurality of turn-off control signals according to the operation result, where the plurality of turn-off control signals are respectively used to control turn-off of the main power tube of the corresponding power stage circuit, and then turn on the corresponding synchronous rectifier tube.

Taking a 4-phase power supply as an example, the frequency dividing module 221 performs frequency dividing by 2 and frequency dividing by 4 operations on the divided signal LOOP to generate two divided signals Q1 and Q2. The conduction control module 222 is configured to perform a logic operation on the frequency-divided signals Q1 and Q2 to obtain a plurality of conduction control signals SET1-SET4, where the plurality of conduction control signals SET1-SET4 are respectively used to control conduction of the main power transistors of the corresponding power stage circuits 201-204. The synchronization detection module 223 is configured to generate a plurality of synchronization signals Div1 and Div2 synchronized with the frequency-divided signals Q1 and Q2 when the off trigger signal SHOT is detected. The turn-off control module 224 generates a plurality of turn-off control signals RST1-RST4 according to the logic operation results of the plurality of synchronous signals Div1 and Div2, where the plurality of turn-off control signals RST1-RST4 are respectively used to control turn-off of the main power transistors of the corresponding power stage circuits 201-204 and control turn-on of the corresponding synchronous rectifying tubes.

Fig. 5 shows a schematic circuit diagram of the switch control circuit 220-1 according to the first embodiment of the present invention. In an exemplary embodiment, the number of power stage circuits in the multiphase power supply 200 is even, and in fig. 7, the power stage circuits of the multiphase power supply 200 are illustrated as including 4. It should be understood that the multiphase power supply of the present invention may include more or fewer power stage circuits.

As shown in fig. 5, the frequency dividing module 221-1 of the present embodiment includes 2D flip-flops dff1_1 and dff1_2 in cascade, the data terminals and the negative output terminals of the D flip-flops dff1_1 and dff1_2 are connected together, the negative output terminal of the D flip-flop dff1_1 is used for outputting the frequency dividing signal Q1, the negative output terminal of the D flip-flop dff1_2 is used for outputting the frequency dividing signal Q2, the clock terminal of the D flip-flop dff1_1 is used for receiving the phase-cut signal LOOP, and the clock terminal of the D flip-flop dff1_2 is connected with the negative output terminal of the previous D flip-flop (i.e., the output terminal of the D flip-flop dff1_1). It should be understood that the number of cascaded D flip-flops in the frequency dividing module 221-1 of the present invention may be set according to the number of power stage circuits in the multi-phase power supply 200, for example, when the number of power stage circuits in the multi-phase power supply 200 is 2, the number of D flip-flops in the frequency dividing module 221-1 is 1, when the number of power stage circuits in the multi-phase power supply 200 is 8, the number of D flip-flops in the frequency dividing module 221-1 is 3, and so on.

The turn-on control module 222-1 includes N first logic units, each having an input for receiving M frequency-divided signals (e.g., frequency-divided signals Q1 and Q2) from the frequency-dividing module 221-1, and an output for generating a turn-on control signal SET of a corresponding power stage circuit. Illustratively, each first logic cell includes at least one of an and gate, a not gate, or a nor gate. By way of example, the divided signals Q1 and Q2 each have two logic states of "0" (e.g., a logic low level) and "1" (e.g., a logic high level), so that the divided signals Q1 and Q2 constitute 4 logic states, i.e., (Q1, Q2) have 4 states of (1, 1), (0, 1), (1, 0) and (0, 0). Assuming that the 1 st power stage circuit 201 is triggered when the divided signals Q1 and Q2 are (1, 1), the 2 nd power stage circuit 202 is triggered when the divided signals Q1 and Q2 are (0, 1), and so on, the turn-on control module 222-1 of fig. 5 can be obtained.

As shown in fig. 5, the conduction control block 222-1 of the present embodiment includes AND gates AND1-AND3 AND NOR gates NOR1. The input terminal of the AND gate AND1 is used for receiving the frequency division signals Q1 AND Q2, the output terminal is used for outputting the conduction control signal SET1, one input terminal of the AND gate AND2 is used for receiving the inverse signal of the frequency division signal Q1, the other input terminal is used for receiving the frequency division signal Q2, the output terminal is used for providing the conduction control signal SET2, one input terminal of the AND gate AND3 is used for receiving the frequency division signal Q1, the other input terminal is used for receiving the inverse signal of the frequency division signal Q2, the output terminal is used for providing the conduction control signal SET3, the input terminal of the NOR gate NOR1 is used for receiving the frequency division signals Q1 AND Q2, AND the output terminal is used for providing the conduction control signal SET4.

Further, the synchronization detection module 223-1 includes D flip-flops dff2_1 and dff2_2 corresponding to the 2D flip-flops dff1_1 and dff1_2 in the frequency division module 221-1. The data terminal of the D flip-flop dff2_1 is configured to receive the corresponding frequency-divided signal Q1, the clock terminal is configured to receive the off trigger signal SHOT, and the output terminal is configured to provide the synchronization signal Div1 of the frequency-divided signal Q1. The data terminal of the D trigger DFF2_2 is used for receiving the corresponding frequency division signal Q2, the clock terminal is used for receiving the turn-off trigger signal SHOT, and the output terminal is used for providing the synchronous signal Div2 of the frequency division signal Q2.

Further, the off control block includes AND gates AND4-AND6 AND NOR gate NOR2. The AND gate AND4 has an input for receiving the synchronization signals Div1 AND Div2, an output for outputting the off control signal RST1, one input for receiving the inverse of the synchronization signal Div1, another input for receiving the synchronization signal Div2, an output for providing the off control signal RST2, one input for receiving the synchronization signal Div1, another input for receiving the inverse of the synchronization signal Div2, an output for providing the off control signal RST3, an input of the NOR gate NOR1 for receiving the synchronization signals Div1 AND Div2, AND an output for providing the off control signal RST4.

Fig. 6 shows a schematic waveform diagram of a switching control circuit according to a first embodiment of the present invention, and the operation principle of the 4-phase power supply of the present embodiment is explained below with reference to fig. 5 and 6. As shown in fig. 6, when the 1 st rising edge of the phase-cut signal LOOP arrives, the two-divided signal Q1 of the phase-cut signal LOOP is obtained by the D flip-flop dff1_1, the four-divided signal Q2 of the phase-cut signal LOOP is obtained by the D flip-flop dff1_2, AND when the divided signals Q1 AND Q2 are both "1", the AND gate AND1 outputs the high-level conduction control signal SET1, AND the AND gates AND2-AND3 AND the NOR gate NOR1 outputs are both low-level, so that the 1 st power stage circuit 201 is triggered, AND then the main power transistor T1 of the 1 st power stage circuit 201 is turned on. After the main power transistor T1 of the 1 st power stage circuit 201 is turned on, the on-time control circuit 230 starts timing, and after the timing reaches the set time, the on-time control circuit 230 generates an effective pulse of the off trigger signal SHOT, and then obtains the synchronization signal Div1 of the frequency-divided signal Q1 through the D flip-flop dff2_1, and obtains the synchronization signal Div2 of the frequency-divided signal Q2 through the D flip-flop dff2_2. As shown in fig. 6, waveforms of the synchronization signals Div1 and Div2 are the same as those of the divided signals Q1 and Q2, respectively, and the synchronization signals Div1 and Div2 are delayed with respect to the divided signals Q1 and Q2 by a time, for example, equal to a set time in the on-time control circuit 230. Therefore, when the pulse of the 1 st shutdown trigger signal SHOT arrives, the synchronization signals Div1 AND Div2 are both "1", so that the AND gate AND4 outputs the shutdown control signal RST1 of high level, AND the outputs of the AND gates AND5-AND6 AND the NOR gate NOR2 are both of low level, so that the main power transistor T1 of the 1 st power stage circuit is turned off AND then the corresponding synchronous rectifier transistor T2 thereof is turned on. When the 2 nd rising edge of the phase-cut signal LOOP arrives, the frequency-dividing signal Q1 is turned to "0", AND the frequency-dividing signal Q2 remains "1", so that the AND gate AND2 outputs the high-level conduction control signal SET2 to turn on the main power transistor T1 of the 2 nd power stage circuit. Similarly, when the on time of the main power tube of the 2 nd power stage circuit reaches the set time, the on time control circuit 230 generates an effective pulse of the off trigger signal SHOT, AND the synchronization detection module 223-1 obtains that the synchronization signal Div1 is "0" AND the synchronization signal Div2 is "1", so that the AND gate AND5 outputs the high-level off control signal RST2 to turn off the main power tube T1 of the 2 nd power stage circuit, then turns on the corresponding synchronous rectifying tube, AND so on, thereby achieving the phase-error control of the plurality of power stage circuits in the 4-phase power supply.

Fig. 7 shows a schematic circuit diagram of a switch control circuit according to a second embodiment of the present invention, and fig. 8 shows a schematic waveform diagram of the switch control circuit according to the second embodiment of the present invention. In another exemplary embodiment, the number of power stage circuits in the multiphase power supply 200 is an odd number, and in fig. 4, the power stage circuits of the multiphase power supply 200 are illustrated as including 3. It should be appreciated that the multiphase power supply of the present invention may include more power stage circuits.

As shown in fig. 7, the main difference between the present embodiment AND the first embodiment is that the D flip-flops dff1_1 AND dff1_2 in the frequency dividing module 221-2 further have Reset terminals, AND the on control module 222-2 further includes a logic gate unit (e.g., NOR gate NOR 3) for generating the Reset signal Reset in addition to the AND gates AND1-AND3 for generating the on control signals SET1-SET3, the input terminal of the or gate NOR3 is used for receiving the frequency dividing signals Q1 AND Q2, the or gate NOR3 is used for providing the valid Reset signal Reset to the Reset terminals of the D flip-flops dff1_1 AND dff1_2 when the frequency dividing signals Q1 AND Q2 reach the preset logic state (e.g., the frequency dividing signals Q1 AND Q2 are both "0"), so that the negative output terminals of the D flip-flops dff1_1 AND dff1_2 are Reset to "1", AND the multi-phase power supply 200 can start to operate again from the 1 st power stage circuit after the 3 rd power stage circuit has ended. Otherwise, the structure and principle of the synchronous detection module 223-2 and the off control module 224-2 of the present embodiment are the same as those of the first embodiment, and will not be described again here.

Specifically, as shown in fig. 8, when the 3 rd power stage circuit finishes operating, when the 4 th rising edge of the phase-cut signal arrives, the divided signals Q1 AND Q2 are both "0", AND the NOR gate NOR3 generates the Reset signal Reset of high level, so that the D flip-flops dff1_1 AND dff1_2 are Reset, AND the divided signals Q1 AND Q2 are both inverted to "1", so that the AND gate AND1 generates the effective conduction control signal SET1, so that the main power transistor of the 1 st power stage circuit is turned on.

In summary, in the multiphase power supply 200 based on the COT control architecture provided in the embodiment of the present invention, the phase-misplacement control between the multiple power stage circuits can be achieved by only adopting one control loop, and there is no need to set an independent compensation network and current sampling circuit in each power stage circuit, so that the circuit structure is simple, and the circuit design is simplified and the circuit cost is reduced. In addition, the invention controls the conduction time of a plurality of power stage circuits by using one conduction time control circuit, can ensure the consistent direct current quantity of each phase of inductance current, and is beneficial to improving the stability and reliability of the system.

In further embodiments, the multiphase power supply of the present invention further includes introducing current sampling information in the feedback control circuit 210 and the on-time control circuit 230 to achieve current sharing among multiple power stage circuits.

Specifically, fig. 9 shows a schematic circuit diagram of a feedback control circuit according to an embodiment of the present invention, and fig. 10 and 11 show schematic circuit diagrams and waveform diagrams of a slope compensation module according to an embodiment of the present invention, respectively.

As shown in fig. 9, the feedback control circuit 210 of the present embodiment includes an error amplifier 211, an integrator 212, a slope compensation module 213, an adder 214, and a comparator 215. The positive input terminal of the error amplifier 211 is configured to receive the feedback signal FB of the output voltage Vout, the negative input terminal is configured to receive the reference voltage signal VREF, and the output terminal is configured to provide the error signal Verr therebetween. The integrator 212 is configured to integrate the difference between the feedback signal FB and the reference voltage signal VREF to generate an integrated signal Vc to eliminate a static error of the output voltage Vout. The RAMP compensation module 213 is configured to generate a RAMP compensation signal RAMP according to the triggered switch node voltage of the power stage circuit. The adder 214 is used to obtain the superimposed signal Vcom of the error signal Verr, the integrated signal Vc, and the RAMP compensation signal RAMP. The comparator 215 is configured to compare the superimposed signal Vcom with a first reference voltage Vg1 (e.g., a reference ground potential) to generate the phase-cut signal LOOP.

As shown in fig. 10, the slope compensation module 213 includes a filter unit 2131 composed of resistors R1 to R4 and capacitors C1 and C2, an error amplifier 2132, and a first switch array 2133 composed of a plurality of switches S11 to S1N. Wherein a first terminal of the first switch array 2133 is connected to the switch node voltages Vsw1-VswN of the plurality of power stage circuits and a second terminal is connected to the node A1 for providing the switch node voltage of the triggered power stage circuit of the plurality of power stage circuits to the node A1. The filtering unit 2131 is used to filter the voltage at node A1 to generate ripple signals CSP and CSN. The error amplifier 2132 is used to generate the RAMP compensation signal RAMP from the ripple signals CSP and CSN.

Further, in the filter unit 2131, the resistors R1 and R2 are connected in series between the node A1 and the reference ground, one end of the resistor R3 is connected to the node A2 between the resistors R1 and R2, the other end of the resistor R3 is connected to the node A3, one end of the resistor R4 is connected to the node A3, the other end of the resistor R4 is connected to the node A4, one end of the capacitor C1 is connected to the node A3, the other end of the capacitor C1 is connected to the reference ground, one end of the capacitor C2 is connected to the node A4, and the other end of the capacitor C2 is connected to the reference ground. Wherein node A3 is connected to the positive input of error amplifier 2132 to provide the ripple signal CSP thereto, and node A4 is connected to the negative input of error amplifier 2132 to provide the ripple signal CSN thereto.

Fig. 11 shows a schematic waveform diagram of a slope compensation module according to an embodiment of the invention. In the following embodiments, a 2-phase power supply is taken as an example, where IL1 and IL2 in fig. 11 are inductance current waveforms of the 1 st power stage circuit and the 2 nd power stage circuit, respectively, CSP is a waveform of the ripple signal CSP, and Vsw1 and Vsw2 are switching node voltage waveforms of the 1 st power stage circuit and the 2 nd power stage circuit, respectively. As shown in fig. 11, in the feedback control circuit 210 of the present embodiment, when the system is in a steady state, the output voltages of the error amplifier 211 and the integrator 212 are constant, so that each effective pulse of the phase-cut signal LOOP is determined by the injected RAMP compensation signal RAMP, and the effective pulse-generating point of the phase-cut signal LOOP is exemplified at a position where the RAMP compensation signal RAMP reaches a minimum value, and the waveform of the RAMP compensation signal RAMP coincides with the waveform of the ripple signal CSP, so that the embodiment of the present invention realizes the respective phase current balance of the multiphase power supply by controlling the waveform of the ripple signal CSP.

Further, as shown in fig. 10, when the main power transistor of each power stage circuit is turned on, its corresponding switching node voltage Vsw is supplied to the node A1 through the first switching array 2133, and then the voltage of the node A1 is divided by the resistors R1 and R2 to obtain the voltage of the node A2, and the voltage of the node A2 charges the capacitors C1 and C2 through the resistor R3 and the resistor R4, respectively, so that the voltages of the ripple signals CSP and CSN increase. When the main power transistor of each power stage circuit is turned off and the synchronous rectifier is turned on, the voltage on the capacitor C1 is discharged to the ground through the resistors R3 and R2, and thus the voltage of the ripple signal CSP decreases. Since the discharge path of the capacitor C1 is the same regardless of which power stage circuit is turned on, the discharge time of the capacitor C1 is mainly determined by the voltage level when the capacitor C1 is charged. Assuming that the current imbalance of the 1 st and 2 nd power stage circuits in the multiphase power supply 200, for example, the 1 st power stage circuit has a larger current than the 2 nd power stage circuit, when the main power tube of the 1 st power stage circuit is turned on, the switch S11 is closed, the switch node voltage Vsw1 charges the capacitor C1 through the voltage dividing resistor, and then the switch node voltageWhereinIs the inductor current of the 1 st power stage circuit,On-resistance of main power tube of 1 st power stage circuit due to inductance currentThe capacitor C1 has a relatively large charging voltage, so that the voltage of the ripple signal CSP raised is relatively small under the same on time, so that the ripple signal CSP can be discharged to a minimum value after the main power tube of the 1 st power stage circuit is turned off for a short time, the effective pulse of the phase-cut signal LOOP arrives in advance, and finally the main power tube of the 2 nd power stage circuit can be turned on in advance. When the main power tube of the 2 nd power stage circuit is conducted, the voltage of the switch node is switched onWhereinThe inductor current for the 2 nd power stage circuit,The on-resistance of the main power tube of the 2 nd power stage circuit is generally uniform in magnitude. Because the inductance current is smaller, the charging voltage of the capacitor C1 is larger, under the same conduction time, the raised voltage of the ripple signal CSP is larger, so that after the main power tube of the 2 nd power stage circuit is turned off, the ripple signal CSP can be discharged to the minimum value after more time is needed, the effective pulse of the phase-cut signal LOOP arrives later, the conduction time of the main power tube of the 1 st power stage circuit is finally delayed, the inductance current of the 1 st power stage circuit is reduced until the inductance current of the 1 st power stage circuit is equal to the inductance current of the 2 nd power stage circuit, at the moment, the charging time of the ripple signal CSP when the different power stage circuits are triggered can be equal, the ripple point of the phase-cut signal LOOP can be stable, and then the current balance of the multiphase power supply is realized.

Fig. 12 shows a schematic circuit diagram of a conduction time control circuit according to an embodiment of the present invention. In a further embodiment, the on-time control circuit 230 sets the set time according to the input voltage Vin and the output voltage Vout of the multiphase power supply. As shown in fig. 12, the on-time control circuit 230 of the present embodiment includes a resistor R5, a capacitor C3, a switch S3, and a comparator 231. The first end of the resistor R5 is connected to the input voltage Vin, the second end of the resistor R5 is connected to the first end of the capacitor C3, and the second end of the capacitor C3 is connected to the reference ground. The positive input end of the comparator 231 is connected with the intermediate node of the resistor R5 and the capacitor C3, the negative input end is connected with the output voltage Vout, and the comparator 231 is used for generating the turn-off trigger signal SHOT when the voltage Vs on the capacitor C3 rises to the output voltage Vout. The switch S3 has a first terminal connected to the first terminal of the capacitor C3, a second terminal connected to a first reference voltage Vg1 (e.g., ground), and a third terminal connected to a second reference voltage Vg2. The switch S3 is configured to float when the main power tube of the triggered power stage circuit is turned on, so that the input voltage Vin charges the capacitor C3, and is configured to reset the voltage on the capacitor C3 to the first reference voltage Vg1 or the second reference voltage Vg2 when the main power tube of the triggered power stage circuit is turned off.

Further, the second reference voltage Vg2 is obtained through the switching node voltage of the power stage circuit which is currently triggered. Specifically, the on-time control circuit 230 further includes a second switch array 232 of switches S21-S2N. The first end of the second switch array 232 is connected to the switch node voltages Vsw1-VswN of the plurality of power stage circuits, and the second end is connected to the node A5, so as to provide the switch node voltage of the triggered power stage circuit of the plurality of power stage circuits to the node A5, and provide the second reference voltage Vg2 through the node A5.

The switch S3 is also used to reset the voltage on the capacitor C3 to the second reference voltage Vg2 when the multiphase power source is operating in a Continuous Conduction Mode (CCM), and to reset the voltage of the capacitor C3 to the first reference voltage Vgs1 when the multiphase power source is operating in a Discontinuous Conduction Mode (DCM).

Fig. 13 shows a schematic waveform diagram of an on-time control circuit according to an embodiment of the invention. Similarly, the following embodiment will be described with reference to a 2-phase power supply, in which IL1 and IL2 in fig. 13 are inductance current waveforms of the 1 st power stage circuit and the 2 nd power stage circuit, CSP is a waveform of a ripple signal CSP, vsw1 and Vsw2 are switching node voltage waveforms of the 1 st power stage circuit and the 2 nd power stage circuit, respectively, and Vs is a charging voltage of the capacitor C3. As shown in fig. 13, each time the main power transistor of one power stage circuit is turned on, the switch S3 floats, the input voltage Vin charges the capacitor C3 through the resistor R5, and the comparator 231 toggles to generate an active pulse of the off trigger signal SHOT whenever the voltage on the capacitor C3 rises from the initial value to the output voltage Vout, so the set time is equal to the time when the voltage on the capacitor C3 rises from the initial value to the output voltage Vout. When the multiphase power supply 200 is operated in the continuous conduction mode, the initial voltage of the capacitor C3 is equal to the second reference voltage Vg2, i.e. the initial voltage of the capacitor C3 is equal to the divided value of the switch node voltage of each power stage circuit, and when the synchronous rectifier of each power stage circuit is turned on, the switch node voltageWhereinAn inductor current of a power stage circuit isThe on-resistance of the synchronous rectifier of the power stage circuit can be obtained, so that the set time of the on-time control circuit 230 is equal to. Assuming that the current of the 1 st power stage circuit is larger than that of the 2 nd power stage circuit, when the synchronous rectifying tube of the 1 st power stage circuit is conducted, the switch S21 is closed, the voltage of the capacitor C3 is reset to the divided value of the switch node voltage Vsw1, and the initial voltage across the capacitor C3 is. When the effective pulse of the phase-cut signal LOOP arrives, the main power tube of the 2 nd power stage circuit is conducted, the switch S3 floats, so that the input voltage Vin charges the capacitor C3, the voltage at two ends of the capacitor C3 rises from the initial voltage, and the set conduction time of the main power tube of the 2 nd power stage circuit is larger because of larger inductance current, so that the charging time of the 2 nd power stage circuit is prolonged, and the current in the 2 nd power stage circuit is gradually increased. When the synchronous rectifier of the 2 nd power stage is turned on, the switch S22 is closed, the switch S3 is connected to the first terminal and the third terminal, and the capacitor C3 is reset to the divided value of the switching node voltage Vsw2, and the initial voltage across the capacitor C3 becomesSince the inductance current of the 2 nd power stage circuit is smaller, after the effective pulse of the next phase-cut signal LOOP arrives, the conduction time of the main power tube of the 1 st power stage circuit is reduced, so that the current of the 1 st power stage circuit is gradually reduced until the inductance current of the 1 st power stage circuit is equal to the inductance current of the 2 nd power stage circuit, and at the moment, the conduction time set by the conduction time control circuit 230 tends to be stable, and then the current balance of the multiphase power supply is realized.

Fig. 14 shows a waveform schematic diagram of implementing current sharing by 2 power stage circuits in a multiphase power supply according to an embodiment of the present invention, in fig. 14, iout represents an output current of the multiphase power supply 200, curve 401 represents an inductance current of the 1 st power stage circuit, curve 402 represents an inductance current of the 2 nd power stage circuit as shown in fig. 14, when a sudden change occurs in the system, the currents of two power stage circuits in the multiphase power supply are unequal, but the control circuit of the multiphase power supply provided by the embodiment of the present invention can automatically adjust the inductance currents of two phase power stage circuits, so as to implement automatic current balancing of multiple power stage circuits, which is beneficial to improving stability and performance of the circuit.

In the above description, well-known structural elements and steps have not been described in detail. Those of ordinary skill in the art will understand that the corresponding structural elements and steps may be implemented by various technical means. In addition, in order to form the same structural elements, those skilled in the art can also devise methods which are not exactly the same as the methods described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the following claims.

Claims

1. A control circuit for a multiphase power supply, the multiphase power supply comprising a plurality of power stage circuits connected in parallel, the control circuit comprising:

A feedback control circuit for generating a phase-cut signal according to the feedback signal of the output voltage and the reference voltage signal;

A switch control circuit for controlling the working time sequence of the plurality of power stage circuits according to the phase-cut signals, wherein the switch control circuit is used for generating a plurality of frequency division signals according to the phase-cut signals and controlling the conduction of the main power tube of the corresponding power stage circuit according to the logic states of the plurality of frequency division signals, and

And the on-time control circuit is used for generating an off trigger signal when the on time of the main power tube of the triggered power stage circuit reaches a set time, and the switch control circuit controls the main power tube of the triggered power stage circuit to be turned off according to the off trigger signal and the plurality of frequency division signals.

2. The control circuit of claim 1, wherein the switch control circuit comprises:

the frequency dividing module is used for carrying out frequency dividing operation on the tangential phase signals so as to obtain a plurality of frequency dividing signals;

The conduction control module is used for carrying out logic operation on the plurality of frequency division signals to obtain a plurality of conduction control signals, and the plurality of conduction control signals are respectively used for controlling the conduction of the main power tube of the corresponding power stage circuit;

A synchronization detection module for generating synchronization signals of the plurality of frequency division signals when the turn-off trigger signal is detected, and

The turn-off control module is used for carrying out logic operation on the plurality of synchronous signals to obtain a plurality of turn-off control signals, and the plurality of turn-off control signals are respectively used for controlling turn-off of the main power tube of the corresponding power stage circuit.

3. The control circuit of claim 2, wherein the frequency division module comprises:

And the clock ends of the first D flip-flops in the plurality of first D flip-flops are used for receiving the phase-cut signal, and the clock ends of the other first D flip-flops are connected with the negative output end of the previous first D flip-flop.

4. A control circuit according to claim 3, wherein the synchronization detection module comprises:

a plurality of second D flip-flops, the plurality of second D flip-flops corresponding to the plurality of first D flip-flops,

The data end of each second D trigger is used for receiving corresponding frequency division signals, the clock end is used for receiving the turn-off trigger signals, and the output end is used for providing corresponding synchronous signals.

5. The control circuit of claim 4, wherein the turn-on control module comprises a plurality of first logic cells, each having an input for receiving the plurality of divided signals, each having an output for generating a turn-on control signal for a respective power stage circuit,

The turn-off control module comprises a plurality of second logic units, wherein the input end of each second logic unit is used for receiving a plurality of synchronous signals, and each second logic unit is used for generating a turn-off control signal of a corresponding power stage circuit.

6. The control circuit of claim 5, wherein the first and second logic units comprise at least one of an and gate, a not gate, or a nor gate.

7. The control circuit of claim 5, wherein the plurality of first D flip-flops further comprises a reset terminal when the number of the plurality of power stage circuits is an odd number, the turn-on control module further comprises a third logic unit for providing an active reset signal to the reset terminal of the plurality of first D flip-flops to reset the plurality of first D flip-flops when the plurality of divided signals are in a preset logic state.

8. The control circuit of claim 1, wherein the feedback control circuit comprises:

a first error amplifier for generating an error signal based on the feedback signal and the reference voltage signal;

an integrator for integrating a difference between the feedback signal and the reference voltage signal to generate an integrated signal;

The slope compensation module is used for generating a slope compensation signal according to the voltage of the switch node of the triggered power stage circuit;

An adder for obtaining a superimposed signal of the error signal, the integrated signal and the slope compensation signal, and

A first comparator for comparing the superimposed signal with a first reference voltage to generate the phase-cut signal.

9. The control circuit of claim 8, wherein the slope compensation module comprises:

A first switch array, a first end of which is connected with the switch node voltage of the power stage circuits, and a second end of which is connected with a first node, and is used for providing the switch node voltage of the triggered power stage circuits in the power stage circuits to the first node;

A filtering unit for filtering the voltage at the first node to generate a first ripple signal and a second ripple signal, and

And the second error amplifier is used for generating the slope compensation signal according to the first ripple signal and the second ripple signal.

10. The control circuit of claim 9, wherein the filtering unit comprises:

the first resistor and the second resistor are connected in series between the first node and the ground;

A third resistor, the first end of which is connected with a second node between the first resistor and the second resistor;

The first end of the first capacitor and the second end of the third resistor are connected to the third node, and the second end of the first capacitor is connected to the ground;

A fourth resistor, the first end of which is connected with the third node;

a second capacitor having a first end connected to the fourth node and a second end connected to ground,

The positive input end of the second error amplifier is connected with the third node to receive the first ripple signal, and the negative input end of the second error amplifier is connected with the fourth node to receive the second ripple signal.

11. The control circuit of claim 1, wherein the on-time control circuit sets the set time according to an input voltage and an output voltage of the multiphase power supply.

12. The control circuit of claim 11, wherein the on-time control circuit comprises:

A fifth resistor, the first end of which is connected with the input voltage;

The first end of the third capacitor is connected with the second end of the fifth resistor, and the second end of the third capacitor is connected with the ground;

a second comparator having a positive input connected to the intermediate node of the fifth resistor and the third capacitor and a negative input connected to the output voltage, the second comparator generating the off trigger signal when the voltage of the third capacitor rises to the output voltage, and

A third switch, the first end of which is connected with the first end of the third capacitor, the second end of which is connected with the first reference voltage, the third end of which is connected with the second reference voltage,

The third switch is used for floating when the main power tube of the triggered power stage circuit is turned on so that the input voltage charges the third capacitor, and is used for resetting the voltage of the third capacitor to the first reference voltage or the second reference voltage when the main power tube of the triggered power stage circuit is turned off.

13. The control circuit of claim 12, wherein the first reference voltage is ground, the second reference voltage is derived from a switching node voltage of a currently triggered power stage circuit,

The third switch is further configured to reset the voltage of the third capacitor to the second reference voltage when the multiphase power supply is operating in a continuous conduction mode, and to reset the voltage of the third capacitor to the first reference voltage when the multiphase power supply is operating in an intermittent conduction mode.

14. A multiphase power supply comprising:

a plurality of parallel power stage circuits, and

The control circuit of any one of claims 1-13.