JP7440861B2 - Silicon carbide semiconductor device and its manufacturing method - Google Patents

Description

Application of Article 30, Paragraph 2 of the Patent Law Published on the web as a collection of lecture proceedings (9a-PB3-6) for the 66th Japan Society of Applied Physics Spring Academic Conference (https://confit.atlas.jp/guide/event/jsap2019s/ Subject/9a-PB3-6/advanced) Presented at the 66th Spring Academic Conference of the Japan Society of Applied Physics Published in the proceedings of the International Conference on Silicon Carbide and Related Materials 2019 I Advanced Power Presented at International Conference on Silicon Carbide and Related Materials 2019 Published in the proceedings of the 6th lecture of the Semiconductor Subcommittee. Presented at the 6th lecture of the Advanced Power Semiconductor Subcommittee.

The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing the same.

Semiconductor devices are used for various purposes. In recent years, there has been a demand for semiconductor devices that can operate in high-temperature environments of 200° C. or higher and environments with absorbed doses of several thousand Gy to tens of thousands of Gy. However, it is difficult to use conventional silicon (Si) semiconductors in such an environment, and new semiconductor materials are being considered. Among these, silicon carbide (SiC) semiconductors are expected to be a semiconductor material with excellent heat resistance and radiation resistance.

Ion implantation technology is essential to manufacturing semiconductor devices. In the case of silicon carbide semiconductors, there are problems unique to silicon carbide semiconductors, such as recovery of crystallinity after ion implantation is not as easy as in silicon semiconductors. For this reason, attempts have been made to optimize ion implantation for silicon carbide semiconductors. For example, Patent Document 1 considers reducing damage to the crystal lattice of silicon carbide by changing the plane orientation during ion implantation.

Japanese Patent Application Publication No. 2002-261041

Ion implantation into silicon carbide semiconductors has not only the problem of damage to the crystal, but also the problem of poor controllability of the implantation depth. An object of the present disclosure is to improve the controllability of the depth of ion implantation into a silicon carbide semiconductor, and to easily manufacture a high-performance silicon carbide semiconductor device.

One embodiment of the method for manufacturing a silicon carbide semiconductor device of the present disclosure includes a step of performing ion implantation into a 4H-SiC crystal layer to form an ion implantation layer, and the ion implantation is performed with respect to the {1-100} plane. ], an ion implantation angle tilted +10° or -10° from {1-210} plane, an ion implantation angle tilted +3° or -3° from [0001] with respect to {1-100} plane, or {1-100} plane and {1- The ion implantation is performed at an ion implantation angle tilted by +4° or −4° from [0001] with respect to the plane intermediate between the ion implantation and the [0001] plane.

One aspect of the method for manufacturing a silicon carbide semiconductor device includes forming a trench penetrating an ion implantation layer to use the ion implantation layer as a source region and a drain region separated from each other, and forming a gate insulating film in the trench. The method may further include a step of forming a gate electrode on the gate insulating film, and a step of forming ohmic electrodes in ohmic contact with the source region and the drain region, respectively.

One embodiment of the silicon carbide semiconductor device of the present disclosure includes a 4H-SiC crystal layer and at least one impurity implantation layer formed in the 4H-SiC crystal layer, and the impurity implantation layer has a depth 2.14 mm below the design depth. The impurity concentration at twice the depth is 1/20 or less of the highest impurity concentration in the design depth range.

One embodiment of the silicon carbide semiconductor device further includes a trench provided in the 4H-SiC crystal layer, a gate electrode provided in the trench via a gate insulating film, and an ohmic electrode in ohmic contact with the impurity injection layer, The impurity implantation layer may be provided on both sides of the trench.

According to the method for manufacturing a semiconductor device of the present disclosure, controllability of implantation depth is improved, and a high-performance silicon carbide semiconductor device can be easily manufactured.

1 is a cross-sectional view showing a trench MOSFET according to one embodiment. (a) to (h) are cross-sectional views showing a method for manufacturing a trench MOSFET according to an embodiment in order of steps. FIG. 2 is a cross-sectional view showing a vertical MOSFET according to one embodiment. FIG. 1 is a cross-sectional view showing an IGBT according to an embodiment. FIG. 2 is a cross-sectional view of a PN diode according to one embodiment. FIG. 1 is a cross-sectional view showing a Schottky barrier diode according to one embodiment. FIG. 7 is a cross-sectional view showing a modified example of a Schottky barrier diode having a junction barrier structure. FIG. 3 is a plan view showing the relationship between ion implantation angle and surface orientation. It is a graph showing the measurement results of backscattering yield by Rutherford scattering method. 3 is a graph showing changes in impurity concentration in the depth direction.

In terms of lattice plane symbols, negative exponents are represented by adding a "-" (bar) above the number in terms of crystallography, but in this disclosure, for convenience of writing the specification, the number is not shown. Sometimes expressed with a negative sign in front.

A method of manufacturing a silicon carbide (SiC) semiconductor device according to the present disclosure includes a step of implanting ions into a 4H-SiC crystal layer to form an ion implantation layer. In the process of forming an ion implantation layer, ion implantation is performed at an ion implantation angle tilted by +10° or -10° from [0001] with respect to the {1-100} plane, and from [0001] with respect to the {1-210} plane. At an ion implantation angle tilted by +3° or -3°, or by an ion implantation angle tilted by +4° or -4° from [0001] with respect to the intermediate plane between the {1-100} plane and the {1-210} plane. conduct. Note that this angle allows a deviation of approximately ±1°.

In the ion-implanted layer, it is preferable that impurities exist at a designed concentration in a region within a designed depth range, and the impurity concentration sharply attenuates outside the range. In order to form an ideal ion implantation layer, ion implantation conditions are determined by performing a simulation using parameters such as implantation ion concentration, implantation energy, and substrate material. However, the actual concentration profile of impurities in the depth direction may deviate greatly from the simulation results, and the characteristics of the semiconductor device may be greatly disturbed. The inventors of the present application have found that by performing ion implantation in an angular range that does not cause a sharp drop (dip) in the number of backscattered ions in the Rutherford backscattering method, it is possible to bring the concentration profile of impurities in the depth direction closer to the simulation results. I found out what I can do.

Specifically, in the case of a direction parallel to the {0-100} plane, there is a range in which a dip of approximately ±1° hardly occurs at +10° or −10° from [0001]. Therefore, by performing ion implantation at an ion implantation angle tilted +10° or -10° from [0001] with respect to the {1-100} plane, the controllability of the ion implantation depth is improved and the depth is adjusted to the design value. An ion-implanted layer having a near ideal concentration profile can be formed.

The range in which a similar dip hardly occurs is between +3° or -3° from [0001] in the direction parallel to the {1-210} plane, and between the {1-100} plane and the {1-210} plane. It also exists at +4° or −4° from [0001] in the direction parallel to the plane. For this reason, the ion implantation angle should be set at an angle of +3° or -3° from [0001] with respect to the {1-210} plane, or an intermediate plane between the {1-100} plane and the {1-210} plane. It is also possible to set the angle to +4° or −4° from [0001].

By setting the ion implantation angle to such a value, the impurity concentration at a position 2.14 times deeper than the designed implantation depth can be adjusted by +4° or -4° from [0001] with respect to the conventional {1-100} plane. The injection angle can be reduced to 1/6 or less compared to the case of an inclined injection angle. For example, when the designed implantation depth is 70 nm, the impurity concentration at a depth of 150 nm, which is 2.14 times deeper, can be reduced to 1/6 or less of the conventional level.

Further, the impurity concentration at a position 2.14 times deeper than the design value implantation depth can be preferably set to 1/20 or less, more preferably 1/50 or less of the highest impurity concentration within the design depth range. can. For example, when forming an ion implantation layer with a designed implantation depth of 70 nm, the impurity concentration at a depth of 150 nm is preferably 1/20 or less of the highest impurity concentration in the range from the surface to 70 nm, and more preferably. can be reduced to 1/50 or less.

The method for forming the ion-implanted layer of this embodiment has a large attenuation of the impurity concentration in the depth direction and can easily realize an ideal impurity profile. Transistors).

The trench MOSFET shown in FIG. 1 has a source region 112 and a drain region 111, which are ion-implanted layers formed by ion implantation into a substrate 101 made of 4H-SiC single crystal. A trench is provided between source region 112 and drain region 111. An insulating film 116 is formed on the substrate 101 and has an opening that exposes the source region 112, the drain region 111, and the trench.

A gate electrode 123 is formed in the trench with a gate insulating film 115, which is a dry oxide film, interposed therebetween. A silicide layer 125 is formed on the source region 112 and the drain region 111 so as to be in ohmic contact with each other, and a metal layer 126 is formed on the silicide layer 125. The silicide layer 125 and metal layer 126 formed on the source region 112 function as the source electrode 122, and the silicide layer 125 and metal layer 126 formed on the drain region 111 function as the drain electrode 121.

In the trench MOSFET, for example, as shown in FIG. 2, an insulating film 117 that serves as an implantation mask is formed on a substrate 101, and then ions are implanted to form an ion implantation layer 113 that becomes a source region 112 and a drain region 111. Ion implantation is performed at an ion implantation angle tilted by +10° or -10° from [0001] with respect to the {1-100} plane. Further, in order to reduce damage, high temperature ion implantation at, for example, 500° C. is preferable. Thereafter, a carbon cap layer 118 is formed and annealing is performed to activate impurities and restore crystallinity. Annealing can be performed, for example, at 1700° C. for 5 minutes.

Next, an insulating film 116 having an opening exposing the ion implantation layer 113 is formed, and then a trench is formed using the insulating film 116 as a mask to separate the ion implantation layer 113 into a source region 112 and a drain region 111. Thereafter, dry oxidation is performed at, for example, 1150° C. to form a gate insulating film 115 in the trench portion. After that, openings are formed in the insulating film 116 to expose the source region 112 and the drain region 111, and a silicide layer 125 is formed in the source region 112 and the drain region 111. Thereafter, an aluminum layer is formed and patterned to form a source electrode 122, a drain electrode 121, and a gate electrode 123.

The impurity profile in the depth direction of the ion-implanted layer 113 that becomes the source region 112 and drain region 111 in the trench MOSFET is very important. If the impurity is implanted deeper than the designed position, the source region 112 and drain region 111 will not be sufficiently separated even if a trench is formed, and leakage will occur below the gate electrode 123. The threshold voltage will rise above the design value. It is possible to lower the threshold voltage by making the trench deeper, but if the trench is made deeper than the designed value, parasitic capacitance increases and the operating speed decreases. Further, if the ion implantation layer 113 extends to a deeper position than the designed value, there is also a problem that the impurity concentration in the ion implantation layer 113 decreases.

By using the ion-implanted layer forming method of this embodiment, it is possible to prevent the ion-implanted layer 113 from spreading to a deeper position than the designed value, and to realize a concentration profile close to the designed value. Thereby, in the trench MOSFT, leakage is less likely to occur below the gate electrode 123, and threshold voltage deviation is less likely to occur. In addition, for the {1-210} plane, the ion implantation angle is +3° or -3° tilted from [0001], or for the intermediate plane between the {1-100} plane and the {1-210} plane, [ Ion implantation of the ion implantation layer 113 can also be performed at an ion implantation angle tilted by +4° or −4° from [0001].

The method for forming an ion-implanted layer of this embodiment can, in principle, bring the impurity profile close to an ideal type for both aluminum and boron, which are p-type impurities, and nitrogen and phosphorus, which are n-type impurities. Therefore, it is useful for forming both a p-type ion implantation layer and an n-type ion implantation layer. Further, even if atomic ions are implanted instead of molecular cluster ions, the impurity profile can be easily controlled, and the ion implantation can be performed with less damage to the silicon carbide crystal.

The method for forming an ion implantation layer of this embodiment can be used not only for manufacturing trench MOSFETs but also for manufacturing various semiconductor devices having ion implantation layers. For example, it can also be used to manufacture a vertical MOSFET as shown in FIG. In the vertical MOSFET shown in FIG. 3, an n ^- type drift layer 132 is formed by epitaxial growth on the surface of an n ⁺ type substrate 131 made of 4H-SiC. A p-type well 133 and an n ⁺ -type source region 134 are provided on the surface side of the drift layer 132 by ion implantation, and a source electrode 141 is formed on the source region 134 . A gate electrode 143 is formed across the source region 134 with a gate insulating film 135 interposed therebetween. A drain electrode 142, which is an ohmic electrode, is formed on the back surface of the substrate 131.

The method for forming an ion implantation layer of this embodiment can be used to form the p-type well 133 and the source region 134, which are ion implantation layers. In particular, by using the ion implantation method of this embodiment to form the source region 134, it is easy to control the source region 134 so that it does not become too deep.

The method for forming an ion implantation layer of this embodiment can also be used for manufacturing an insulated gate bipolar transistor (IGBT) as shown in FIG. 4. In the IGBT shown in FIG. 4, an n ^- type drift layer 152 is formed by epitaxial growth on the surface of a substrate 151 made of, for example, p ⁺ type 4H-SiC, and a p type well is formed on the surface side of the drift layer 152. 153 is formed by ion implantation. An n ⁺ -type emitter region 154 is formed in the p-type well 153 by ion implantation, and an emitter electrode 161 is formed on the emitter region 154 . A gate electrode 163 is formed across the emitter region 154 with a gate insulating film 155 interposed therebetween. A collector electrode 162 is formed on the back surface of the substrate 151.

The method for forming an ion implantation layer of this embodiment can be used to form the p-type well 153 and the emitter region 154, which are ion implantation layers. In particular, by using the ion implantation method of this embodiment to form the emitter region 154, it is easy to control the emitter region 154 so that it does not become too deep.

The method for forming an ion implantation layer of this embodiment can also be used to manufacture a PN diode as shown in FIG. In FIG. 5, an n ^- type epitaxial layer 172 is formed on a substrate 171 made of n ⁺ type 4H-SiC, and a p ⁺ type layer 173 is formed on top of the epitaxial layer 172 by ion implantation. There is. A silicon oxide film 175 having an opening exposing the p ⁺ type layer is formed on the epitaxial layer 172, and an anode electrode 178 is formed in the opening. A cathode electrode 179 is formed on the back surface of the substrate 171. By using the ion implantation method of this embodiment to form the p ⁺ type layer 173, it is possible to easily control the p ⁺ type layer 173 so that it does not become too deep.

The method for forming an ion implantation layer of this embodiment can also be used to manufacture a Schottky barrier diode as shown in FIG. In FIG. 6, an n ^- type epitaxial layer 182 is formed on a substrate 181 made of n ⁺ type 4H-SiC, and a p ⁺ type layer 183 is formed on top of the epitaxial layer 182 by ion implantation. There is. A silicon oxide film 185 having an opening exposing the p ⁺ type layer is formed on the epitaxial layer 182, and a Schottky electrode 188 is formed in the opening. An ohmic electrode 189 is formed on the back surface of the substrate 181. Instead of the p ⁺ type layer 183, a junction barrier structure 184 as shown in FIG. 7 can also be formed. By using the formation method of the ion implantation method of this embodiment, it is possible to easily control the p ⁺ type layer 183 or the junction barrier structure 184 so that it does not become too deep.

The method for forming an ion implantation layer of this embodiment can be used not only in these cases but also in any case where an ion implantation layer is formed in a 4H-SiC crystal layer. Note that the 4H-SiC crystal layer into which ions are implanted may be the substrate or an epitaxially grown layer formed on the substrate.

The method for forming an ion-implanted layer according to the present disclosure will be described in more detail using Examples. The following examples are illustrative and are not intended to limit the scope of rights.

<Channeling measurement using Rutherford backscattering method>
Helium was injected at an injection angle tilted from [0001], and channeling was measured by the Rutherford backscattering method. The scattering intensity was measured at an inclined angle along line 1, line 2, and line 3 in FIG. 8 with an injection acceleration voltage of 2 MeV.

As shown in Figure 9, in the case of line 1, which is parallel to the {1-100} plane, there is a dip in the vicinity of -4°, which is used in normal ion implantation, where the number of backscattered ions rapidly decreases. It will be done. At locations where dips are observed, channeling occurs during ion implantation, and there is a high possibility that impurities will spread to deep locations. On the other hand, no dip is observed in the range of -10±1°, and it is predicted that channeling will be less likely to occur, even considering the deviation of the injection angle.

In the case of line 2, which is the direction parallel to the {1-210} plane, the range is -3±1°, and the direction parallel to the plane between the {1-100} plane and the {1-210} plane. In the case of line 3, a rapid decrease in the number of backscattered ions is not observed in the range of -4±1°, so it is predicted that channeling can be made difficult to occur even in this range.

Furthermore, since the profile of the number of backscattered ions is symmetrical, it is predicted that channeling can be made similarly less likely to occur at +10° in line 1, +3° in line 2, and +4° in line 3.

<Measurement of impurity concentration profile>
Ions were implanted into a 4H-SiC single crystal substrate, and the impurity concentration in the depth direction was measured by secondary ion mass spectrometry (SIMS). Conditions for ion implantation were determined by simulation so that the designed implantation depth was 70 nm. The simulation for determining the conditions was performed using SRIM2008 as simulation software. The specific implantation conditions were multistage implantation using aluminum atoms as the ion species, implantation depth of 70 nm, and implantation concentration of 4×10 ²⁰ (atoms/cm ³ ). The implantation amount was 2.40×10 ¹⁵ /cm ² , the implantation amount was 7.00×10 ¹⁴ /cm ² at acceleration energy of 25 keV, and the implantation amount was 3.20×10 ¹³ /cm ² at acceleration energy of 12 keV. For SIMS measurements, a secondary ion mass spectrometer SIMS6650 manufactured by ULVAC Phi was used, and an O2 Duo Plasmatron ion gun was used as the primary ion gun.

As shown in FIG. 10, when ion implantation is performed at a tilt of -4° from [0001] with respect to the {1-100} plane, which corresponds to -4° of line 1, the impurity concentration decreases from a depth of about 80 nm. However, the deviation from the ideal profile obtained by simulation begins to increase, and the impurity concentration at a position of 150 nm, which is 2.14 times the design implantation depth, is approximately 6×10 ¹⁹ cm ⁻³ .

On the other hand, if ions are implanted at a tilt of -10° from [0001] to the {1-100} plane, which corresponds to -10° on line 1, the impurity concentration up to a depth of about 100 nm will be lower than the ideal level according to the simulation. profile is not significantly different. Although the deviation gradually increases at a position deeper than the designed implantation depth of 70 nm, the impurity concentration at 150 nm was about 1×10 ¹⁹ cm ⁻³ , which was about 1/6 of the case at −4°.

In addition, in the case of -10°, the maximum impurity concentration in the range up to the design implantation depth of 70nm is about 6×10 ²⁰ cm ^-3 , and the impurity concentration at 150nm, which is 2.14 times the design implantation depth, is about 6×10 20 cm -3. The concentration was 1/50 or less of the maximum value. On the other hand, in the case of −4°, the impurity concentration at 150 nm is about 1/10 of the maximum value, and sufficient attenuation of the impurity concentration does not occur.

<Comparison of threshold voltages>
When the p-type trench MOSFET shown in Figure 1 was fabricated, when ions were implanted at an angle of -10° from [0001] with respect to the {1-100} plane, the threshold voltage was -4V, and the normally-off state was I was able to make it happen. On the other hand, when ion implantation was performed at an angle of −4° from [0001] with respect to the {1-100} plane, the threshold voltage was +9V, and normally-off could not be realized. The threshold voltage was measured by setting the drain voltage to -100 mV, the source voltage to 0 V, and changing the gate voltage.

Note that the trench depth was 160 nm, the gate insulating film thickness was 20 nm, the gate length was 5 μm, and the gate width was 10 μm. The ion implantation layer was formed by multistage implantation using aluminum atoms as ion species, with a designed implantation depth of 70 nm and an implantation concentration of 4×10 ²⁰ atoms/cm ³ . The conditions for multi-stage implantation were: acceleration energy of 55 keV and implantation amount of 2.40×10 ¹⁵ /cm ² , acceleration energy of 25 keV and implantation amount of 7.00×10 ¹⁴ /cm ² , acceleration energy of 12 keV and implantation amount of 3.20×10 ¹³ / ^cm2 .

The method for manufacturing a silicon carbide semiconductor device of the present disclosure has high controllability of implantation depth, can easily manufacture a high-performance silicon carbide semiconductor device, and is useful in the field of semiconductor devices.

101 Substrate 111 Drain region 112 Source region 113 Ion implantation layer 115 Gate insulating film 116 Insulating film 117 Insulating film 118 Carbon cap layer 121 Drain electrode 122 Source electrode 123 Gate electrode 125 Silicide layer 126 Metal layer 131 Substrate 132 Drift layer 133 P-type well 134 Source region 135 Gate insulating film 141 Source electrode 142 Drain electrode 143 Gate electrode 151 Substrate 152 Drift layer 153 P-type well 154 Emitter region 155 Gate insulating film 161 Emitter electrode 162 Collector electrode 163 Gate electrode 171 Substrate 172 Epitaxial layer 173 P ⁺ type Layer 175 Silicon oxide film 178 Anode electrode 179 Cathode electrode 181 Substrate 182 Epitaxial layer 183 Mold layer 184 Junction barrier structure 185 Silicon oxide film 188 Schottky electrode 189 Ohmic electrode

Claims (2)

A step of performing ion implantation into a 4H-SiC crystal layer to form an ion implantation layer,
The ion implantation is performed at an ion implantation angle of +10° or -10° from [0001] with respect to the {1-100} plane, and an ion implantation angle of +3° or -3° from [0001] with respect to the {1-210} plane. The ion implantation angle of the silicon carbide semiconductor device is performed at an ion implantation angle that is tilted by +4° or −4° from [0001] with respect to the plane between the {1-100} plane and the {1-210} plane. Production method. forming a trench penetrating the ion implantation layer to make the ion implantation layer a source region and a drain region separated from each other;
forming a gate insulating film in the trench;
forming a gate electrode on the gate insulating film;
The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising the step of forming ohmic electrodes in ohmic contact with the source region and the drain region, respectively.

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