JP7318580B2 - SOI wafer manufacturing method - Google Patents

Description

The present invention relates to an SOI wafer and its manufacturing method.

As a method for manufacturing an SOI wafer, there is known a method of manufacturing a bonded SOI wafer by bonding two silicon single crystal wafers, a base wafer as a substrate and a bond wafer on which an SOI layer is formed, with a silicon oxide film interposed therebetween. It is As a process for manufacturing such a bonded wafer, for example, an oxide film is formed on the surface of at least one of the two wafers, and after the bonding surfaces are brought into close contact with each other without foreign matter interposed therebetween, approximately 200 wafers are bonded together. A method of heat-treating at a temperature of up to 1200° C. to increase bonding strength is known (see Patent Document 1).

The bonded wafer, whose bonding strength has been increased by performing such a heat treatment, can be subjected to subsequent grinding and polishing processes. An SOI layer can be formed in which devices are formed. However, when the surface after grinding is thinned by polishing, setting a large polishing allowance has the advantage of improving minute micro-roughness of the polished surface, but on the other hand, the film of the SOI layer over the entire wafer. Since there is a problem that thickness uniformity deteriorates, there is an upper limit to the polishing margin that can be set.

Therefore, as a method for improving the micro-roughness without degrading the film thickness uniformity, there is a high-temperature heat treatment at 1000° C. or higher in a non-oxidizing atmosphere, which is an effective means for improving the micro-roughness.

Recently, as a technique for manufacturing an ultra-thin SOI wafer having an SOI layer thickness of 0.1 μm or less with good film thickness uniformity, an ion implantation delamination method (also called Smart Cut (registered trademark) method) has been introduced. It is drawing attention (Patent Document 2).
In the ion implantation delamination method, for example, an oxide film is formed on at least one of two silicon wafers, and at least one of hydrogen ions and rare gas ions is implanted from the surface of the bond wafer to the inside of the bond wafer, for example, near the surface. After the microbubble layer (encapsulation layer) is formed, the bond wafer is brought into close contact with the base wafer via the oxide film on the ion-implanted surface side, and then heat treatment (peeling heat treatment) is applied to remove the microbubble layer from the cleaved surface (peeled surface). ), the bond wafer is separated into a thin film, and heat treatment (bonding heat treatment) is applied to firmly bond the two silicon wafers to form an SOI wafer.

The surface (exfoliated surface) of the SOI wafer manufactured in this way has a relatively good mirror finish, but in order to obtain an SOI wafer with a surface roughness equivalent to that of a normal mirror-polished wafer, it is further called touch polishing. Polishing is performed with a very small polishing stock removal of 100 nm or less.
As an alternative to or in combination with this touch polishing, high-temperature heat treatment is performed in a hydrogen or Ar atmosphere to reduce the surface roughness of the SOI layer (surface A technique for reducing roughness) and crystal defects is also known (Patent Document 3).

By using the ion implantation delamination method, it is relatively easy to obtain an SOI wafer with extremely high film thickness uniformity of the SOI layer, and in addition, one of the delaminated wafers can be reused, so there is an advantage that materials can be used effectively. There is also In addition, this method can be used to directly bond silicon wafers without an oxide film in the production of bonded wafers. It can also be used to manufacture an SOI wafer by injecting and bonding with an insulating base wafer such as quartz, silicon carbide, alumina, or diamond, which has a different coefficient of thermal expansion from that of a silicon wafer.

As a bond wafer and a base wafer in the production of such an SOI wafer, it is common to use a silicon single crystal wafer with a plane orientation of {100}. ), an SOI wafer having an SOI layer having a plane orientation of {110} is produced by using a wafer having a plane orientation of {110} as a bond wafer for the purpose of producing a device with enhanced carrier mobility in the channel direction. A method has also been proposed (Patent Document 4).

In the specification of the present application, the Miller indices are used to represent crystal planes and crystal orientations. For example, {100} is a generic term for crystal planes such as (100), (010), and (001), and <100> is a crystal orientation such as [100], [010], and [001]. It represents a generic term.

Japanese Patent Publication No. 5-46086 Japanese Patent No. 3048201 JP-A-11-307472 JP-A-2004-342858

In recent years, due to the diversification of device applications manufactured using SOI wafers, in addition to the conventionally used SOI wafers having an SOI layer with a plane orientation of {100} or {110}, depending on the device application, or compound An SOI wafer having an SOI layer with a plane orientation of {111} has been demanded as a substrate for epitaxially growing a semiconductor layer.

However, according to the inventor's research, when the plane orientation of the SOI layer of the SOI wafer is exactly {111}, that is, {111} just (general processing accuracy is about ±0.1 degrees), the SOI In the wafer manufacturing process, the flattening heat treatment applied mainly for the purpose of flattening the surface of the SOI layer causes remarkable unevenness reflecting the atomic step shape on the surface of the SOI layer, and sufficient flatness ( It was found that there is a problem that the surface roughness) cannot be obtained. Further, although it is possible to remove the atomic step shape on the surface of the SOI layer by polishing, the film thickness uniformity of the SOI layer deteriorates due to the sagging of the outer peripheral portion of the wafer caused by polishing.

Accordingly, the present invention has been devised in view of such problems, and provides an SOI wafer capable of effectively applying planarization heat treatment to the surface of the SOI layer even if the SOI wafer has a {111} SOI layer. As a result, it is an object of the present invention to provide an SOI wafer having a {111} SOI layer with good surface roughness (micro-roughness) in which unevenness reflecting the step shape is suppressed, and a method for manufacturing the same.

In order to achieve the above objects, the present invention provides an SOI wafer having an SOI layer, wherein the plane orientation of the SOI layer is angled off from {111}, and the angle of the off-angle is 2 degrees. An SOI wafer characterized by the above is provided.
In this way, the plane orientation of the SOI layer is off-angled from {111} and the off-angle angle is 2 degrees or more, so heat treatment in a non-oxidizing atmosphere (flattening heat treatment) is performed. Therefore, the micro-roughness is not deteriorated, but rather improved, and an SOI wafer having both high film thickness uniformity and good micro-roughness can be obtained.

Further, it is preferable that the angle of the off-angle is 5 degrees or less.
If the off-angle angle is 5 degrees or less, {111} characteristics (device characteristics) can be obtained more reliably and sufficiently.

Further, according to the present invention, there is provided a method for manufacturing an SOI wafer in which a base wafer and a bond wafer made of silicon single crystal are bonded together and the bond wafer is thinned to form an SOI layer, wherein the bond wafer has a plane orientation of Provided is a method for manufacturing an SOI wafer, characterized in that the SOI wafer is manufactured by using a wafer which is off-angled from {111} and the angle of the off-angle is 2 degrees or more.
Thus, in the method of manufacturing an SOI wafer by the bonding method, by using a bond wafer whose plane orientation is off-angled from {111} and whose off-angle angle is 2 degrees or more, high film thickness uniformity and SOI wafers with both good micro-roughness can be produced.

Further, it is preferable to heat-treat the manufactured SOI wafer at a temperature of 1000° C. or more and 1350° C. or less in a non-oxidizing atmosphere.
As described above, according to the present invention, even if heat treatment is performed in a non-oxidizing atmosphere, unevenness reflecting the shape of atomic steps does not occur on the surface of the SOI layer, and roughness is sufficiently improved and crystal defects are reduced. A well-structured SOI wafer can be manufactured.

In addition, as the bond wafer, at least one of hydrogen ions and rare gas ions is implanted from the surface to form an ion-implanted layer in the vicinity of the surface, and the bond wafer and the base wafer are bonded together. After that, the bond wafer can be thinned by peeling at the ion-implanted layer.
In this way, by using the so-called ion implantation delamination method, an ultra-thin SOI wafer having an SOI layer thickness of, for example, 0.1 μm or less, which has high film thickness uniformity and is capable of forming high-speed devices, can be obtained. It can be reliably manufactured.

Moreover, when bonding the bond wafer and the base wafer together, it is preferable to bond them together via an insulating film.
In this way, by bonding a bond wafer and a base wafer made of, for example, silicon via an insulating film, it is possible to manufacture an SOI wafer having good bonding strength because the base wafer and the bond wafer are made of the same material. .

Further, it is preferable to use a bond wafer having an off-angle angle of 5 degrees or less.
If the off-angle angle is 5 degrees or less, {111} characteristics (device characteristics) can be obtained more reliably and sufficiently.

As described above, with the SOI wafer of the present invention, not only the SOI layer surface micro-roughness but also the thickness uniformity of the SOI layer can be excellent. It is possible to provide an SOI wafer having an SOI layer with a plane orientation of {111} suitable for forming an epitaxial layer and a method for manufacturing the same.

It is a schematic diagram showing an example of the SOI wafer of the present invention. FIG. 4 is a diagram showing the results of micro-roughness measurement by AFM in Examples 1 and 2; 5 is a diagram showing the results of micro-roughness measurement by AFM of Comparative Example 1. FIG. (111) It is a figure which shows an example of the surface state after planarization heat processing of the polished wafer using a just crystal.

Conventionally, when manufacturing an SOI wafer having an SOI layer with a plane orientation of {111}, first, a silicon single crystal ingot with a crystal orientation of <111> is pulled up, and then the crystal orientation of the ingot is measured by an X-ray orientation measuring device ( Angular resolution of about 1 minute), the ingot is sliced so that the plane orientation is exactly {111}, and a bond wafer for forming an SOI layer is manufactured.

In this way, when bond wafers sliced so that the plane orientation is exactly {111} are manufactured at the mass production level, even if they are sliced so that the plane orientation is just, the actual degree is about ±0.1 degrees. Those with angular misalignment are usually included. On the other hand, there are cases where an angular deviation of about ±0.2 degrees is allowed as a required product wafer specification. In such a case, the angular deviation is within ±0.2 degrees. Since a wafer satisfies the required specifications, such a wafer is treated as having a plane orientation of {111} just.
However, there are no product specifications that allow angular deviations greater than 0.2 degrees as {111} just, so wafers with such angular deviations are intentionally tilted from {111}. It can be said that it is a wafer sliced by In this way, a wafer manufactured by intentionally tilting the slicing direction from a certain characteristic orientation is called an off-angled wafer, and the tilt angle is called an off-angle angle.

The present inventor prepared an SOI wafer having an SOI layer with a plane orientation of {111} just by an ion implantation delamination method, and used an inert gas (argon It was confirmed that when a high-temperature heat treatment was performed in a gas), the surface of the SOI layer showed a remarkable unevenness reflecting the shape of the atomic step, and the micro-roughness of the surface of the SOI wafer tended to worsen. As a result of further investigation, we found that the micro-roughness after this heat treatment is related to the off-angle of the bond wafer.

Here, an experiment on a bond wafer, which is the source of the SOI layer, will be shown.
FIG. 4 shows an example of the surface state of a polished wafer (PW) using (111) just crystal after planarization heat treatment. The conditions at this time and the measurement results by AFM (Atomic Force Microscope) are as follows.
・Wafer used: diameter 300 mm PW, (111) just ・Heat treatment conditions: RTA (hydrogen atmosphere (100% H ₂ ), 1200° C., 30 seconds)
・Surface roughness measurement: AFM (30 μm square)
·Measurement result:
(Before RTA) PV: 0.853 nm, RMS: 0.103 nm, Ra: 0.085 nm
(After RTA) PV: 0.901 nm, RMS: 0.111 nm, Ra: 0.091 nm

As described above, the high-temperature heat treatment causes step-shaped unevenness on the surface, thereby deteriorating the micro-roughness. Also in the high-temperature heat treatment of an SOI wafer using such a bond wafer of (111) just crystals, step-shaped irregularities are generated on the surface of the SOI layer, and the micro-roughness is deteriorated. As a result of further intensive research, the present inventors have found that micro-roughness can be improved even after heat treatment if the plane orientation is off-angled from {111} by an angle of 2 degrees or more, and have completed the present invention.

Hereinafter, the present invention will be described in detail as an example of embodiments with reference to the drawings, but the present invention is not limited to these.

FIG. 1 shows an example of the SOI wafer of the present invention. As shown in FIG. 1, an SOI wafer 1 has an SOI layer 4 on a base wafer 2, for example a silicon wafer, with an insulating film (eg, Si oxide film) 3 interposed therebetween. The plane orientation of this SOI layer 4 is off-angled from {111}, and the angle of this off-angle is 2 degrees or more. That is, it is not the product specification (off-angle angle: within ±0.1 degrees) that is normally allowed as {111} just.
In addition to the embodiment shown in FIG. 1, an SOI layer as described above may be formed on an insulating substrate (such as a quartz substrate) as a base wafer, instead of the one in which an insulating film is separately provided. .

With such a material, at least the effect of improving the surface roughness can be obtained by the high-temperature heat treatment described above, and the purpose of removing defects can also be achieved.

The upper limit of the off-angle angle is not particularly limited as long as generation of a step shape in the planarization heat treatment can be suppressed, but is preferably 15 degrees or less, more preferably 5 degrees or less.
In particular, when the angle is 5 degrees or less, {111} characteristics (device characteristics) can be obtained more reliably and sufficiently.

The above SOI wafer can be produced, for example, by the steps of the SOI wafer production method of the present invention described below. First, a silicon single crystal ingot having a <111> crystal orientation is grown using a <111> crystal orientation seed crystal by the Czochralski method (CZ method). Next, when slicing a bond wafer for forming an SOI layer from the grown silicon single crystal ingot, an off-angle is applied so that the off-angle angle is 2 degrees or more. In this case, the seed crystal used in advance may have a desired off-angle, and the grown CZ silicon single crystal ingot may be sliced perpendicular to the growth axis direction. By doing so, the yield of slicing from the ingot can be improved.

Next, thinning of the bond wafer by the ion implantation delamination method will be described.
First, at least one of hydrogen ions and rare gas ions is implanted at a desired acceleration energy and dose from the surface of a bond wafer having an off-angle produced by the CZ method. A microbubble layer (ion-implanted layer) is formed in the vicinity of the surface of the bond wafer by the ions thus implanted. This bond wafer is brought into close contact with the base wafer via a silicon oxide film or the like on the ion-implanted surface side. After that, when a heat treatment (peeling heat treatment) is applied at a relatively low temperature of about 500° C. or higher, the microbubble layer is peeled off due to the pressure of the microbubbles and the rearrangement of the crystals. Next, a heat treatment (bonding heat treatment) is performed at about 1000 to 1200° C. in an oxidizing atmosphere to increase the bonding strength between the wafers.

With such an ion implantation delamination method, an ultra-thin SOI wafer having an SOI layer thickness of, for example, 0.1 μm or less, which has an SOI layer with high film thickness uniformity and a plane orientation of {111}. can be manufactured more reliably.
The thinning of the bond wafer is not limited to the hydrogen ion implantation delamination method, and conventionally used methods such as grinding, polishing, and etching can be applied.

When bonding the bond wafer and the base wafer together as described above, it is preferable to bond them together via an insulating film. In this way, by bonding a bond wafer and a base wafer made of, for example, silicon via an insulating film, it is possible to manufacture an SOI wafer having good bonding strength because the base wafer and the bond wafer are made of the same material. . However, the present invention is not limited to this, and for example, the bond wafer may be directly attached to the insulating base wafer.

Next, the obtained SOI wafer is subjected to a high-temperature heat treatment of about 1000°C to 1350°C in a non-oxidizing atmosphere such as Ar or _H2 . It is possible to manufacture an SOI wafer which is excellent and has reduced crystal defects. In this case, in the present invention, since the plane orientation of the SOI layer is at least two degrees off-angled from {111}, the heat treatment in a non-oxidizing atmosphere results in a microscopic Roughness does not deteriorate, but rather improves.

The SOI wafer thus obtained is extremely thin as described above, has high film thickness uniformity, and has good micro-roughness. It is suitable for specific device applications and for forming epitaxial layers made of compound semiconductors.

EXAMPLES The present invention will be described in more detail below with reference to examples and comparative examples, but the present invention is not limited to the examples.

(Example 1)
A silicon single crystal ingot having a <111> crystal orientation is pulled up by the CZ method, and the ingot is sliced to obtain a bond with a diameter of 300 mm and an off-angled bond whose plane orientation is off-angled from (111) by 2 degrees. Wafers were produced as examples of the present invention.

An SOI wafer was produced by forming an oxide film on this bond wafer, implanting hydrogen ions to form an ion-implanted layer, bonding with a base wafer, and separating at the ion-implanted layer.
The SOI wafer fabrication conditions are as follows.
・Base wafer: (100) silicon single crystal wafer ・Buried oxide film: 300 nm formed on bond wafer surface, no base wafer ・Ion implantation conditions: Hydrogen ions, implantation energy of 60 keV, dose amount of 8×10 ¹⁶ atoms/cm ²
・Exfoliation heat treatment: 500° C. for 30 minutes in an Ar gas atmosphere ・Planarization heat treatment 1: RTA (100% H ₂ , 1200° C., 30 seconds)
- Bonding heat treatment: Oxidizing atmosphere, 1000°C, 1 hour - Flattening heat treatment 2: RTA (100% H ₂ , 1200°C, 30 seconds)

After the planarization heat treatment 2 was performed on the SOI wafer, the micro-roughness of the SOI layer surface was measured by AFM. This AFM micro-roughness measurement was performed on a 30 μm square range at the center of the SOI wafer. FIG. 2 shows the measurement results. Table 1 also shows the micro-roughness (PV, RMS, Ra) and the presence or absence of step-shaped unevenness in addition to the implementation conditions.

(Example 2)
An SOI wafer was produced in the same manner as in Example 1 except that the off-angle angle of the bond wafer was 4 degrees, and micro-roughness was measured by AFM. FIG. 2 shows the measurement results.

(Example 3)
An SOI wafer was manufactured in the same manner as in Example 1, except that the conditions of the planarization heat treatment were changed as follows, and micro-roughness was measured by AFM.
・Planarization heat treatment 1: None ・Planarization heat treatment 2: 100% Ar atmosphere, 1200°C, 1 hour

(Comparative Examples 1 and 2)
An SOI wafer was produced in the same manner as in Example 1 except that the bond wafer was (111) just (Comparative Example 1) and the off-angle angle was 1 degree (Comparative Example 2), and micro-roughness was measured by AFM. The measurement results of Comparative Example 1 are shown in FIG.

When the film thickness uniformity was measured, both Examples 1-3 and Comparative Example were good. However, step-shaped unevenness did not occur at all in Example 1-3. confirmed to have occurred. As for surface roughness, as shown in Table 1, Example 1-3, which is the present invention and the off-angle angle of the bond wafer is 2 degrees or more, has substantially better values than Comparative Examples 1 and 2. rice field.

In addition, this invention is not limited to the said embodiment. The above embodiment is an example, and any device that has substantially the same configuration as the technical idea described in the claims of the present invention and produces similar effects is the present invention. It is included in the technical scope of the invention.

DESCRIPTION OF SYMBOLS 1... SOI wafer, 2... Base wafer, 3... Insulating film, 4... SOI layer.

Claims (3)

A method for manufacturing an SOI wafer by bonding a base wafer and a bond wafer made of silicon single crystal together and thinning the bond wafer to form an SOI layer, comprising:
manufacturing the SOI wafer using a bond wafer having a plane orientation oriented off-angle from {111} and having an off-angle angle of 2 degrees or more and 5 degrees or less ;
A method for manufacturing an SOI wafer, wherein the manufactured SOI wafer is further heat-treated at a temperature of 1000° C. or higher and 1350° C. or lower in a non-oxidizing atmosphere . using a bond wafer in which at least one of hydrogen ions and rare gas ions is implanted from the surface to form an ion-implanted layer in the vicinity of the surface;
2. The method for manufacturing an SOI wafer according to claim 1 , wherein after bonding the bond wafer and the base wafer, the bond wafer is thinned by delamination at the ion-implanted layer. 3. The method for manufacturing an SOI wafer according to claim 1, wherein when the bond wafer and the base wafer are bonded together, an insulating film is interposed therebetween.

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