JP7211949B2 - セラミックス回路基板 - Google Patents
セラミックス回路基板 Download PDFInfo
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- JP7211949B2 JP7211949B2 JP2019534494A JP2019534494A JP7211949B2 JP 7211949 B2 JP7211949 B2 JP 7211949B2 JP 2019534494 A JP2019534494 A JP 2019534494A JP 2019534494 A JP2019534494 A JP 2019534494A JP 7211949 B2 JP7211949 B2 JP 7211949B2
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
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- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
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- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
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Description
α2=Σαi・Ei・Vi/ΣEi・Vi
上記計算式中、αは熱膨張係数、Eはヤング率、Vは体積分率を示し、添え字iは複合材料における各材料成分を示す。
セラミックス基材として、窒化アルミニウム(AlN)基材(サイズ:50mm×60mm×0.635mmt)を用いた。Al-Cu-Mgクラッド箔をろう材として用い、セラミックス基材の両面に温度630℃にてAl板(厚み0.2mm)を接合し、エッチングによりAl回路を形成した。続いて、溶射法(コールドスプレー法)で厚み0.4mmのCu回路を積層し、温度300℃でアニール処理を行った後、無電解Niめっきを施し、セラミックス回路基板を作製した。
実施例1と同様のセラミックス基材の両面に溶射法(コールドスプレー法)で厚み0.2mmのAl回路を積層し、温度500℃でアニール処理を行った。続いて、溶射法(コールドスプレー法)で厚み0.4mmのCu回路を積層し、温度300℃でアニール処理を行った後、無電解Niめっきを施し、セラミックス回路基板を作製した。
セラミックス基材として、窒化珪素(Si3N4)基材(サイズ:50mm×60mm×0.32mmt)を用いた。Ag-Cu-TiH2ろう材を用い、セラミックス基材の両面に温度800℃にてCu板(厚み0.1mm)を接合し、続いて融点が300℃の降温半田でCu板(厚み0.9mm)を接合した。エッチングによりCu回路を形成した後、無電解Niめっきを施し、セラミックス回路基板を作製した。
実施例1と同様のセラミックス基材の両面に溶射法(コールドスプレー法)で厚み0.4mmのAl回路を形成し、温度500℃でアニール処理を行った後、無電解Niめっきを施し、セラミックス回路基板を作製した。
実施例1と同様のセラミックス基材の両面にアクリル系接着剤で厚み0.3mmのCu金属を接着した後、エッチングによりCu回路を形成し、無電解Niめっきを施してセラミックス回路基板を作製した。
Ag-Cu-TiH2ろう材を用い、実施例1と同様のセラミックス基材の両面に温度800℃にてCu板(厚み0.3mm)を接合し、エッチングによりCu回路を形成した後、無電解Niめっきを施し、セラミックス回路基板を作製した。
セラミックス基材として、窒化アルミニウム(AlN)基材(サイズ:50mm×60mm×1.0mmt)を用いた以外は、比較例1と同様の操作を行い、セラミックス回路基板を作製した。
セラミックス基材として、窒化珪素(Si3N4)基材(サイズ:50mm×60mm×0.635mmt)を用いた以外は、比較例1と同様の操作を行い、セラミックス回路基板を作製した。
セラミックス基材として、窒化珪素(Si3N4)基材(サイズ:50mm×60mm×0.32mmt)を用いた以外は、比較例1と同様の操作を行い、セラミックス回路基板を作製した。
Cu板(厚み1.0mm)を用いた以外は、比較例4と同様の操作を行い、セラミックス回路基板を作製した。
Al-Cu-Mgクラッド箔をろう材として用い、実施例1と同様のセラミックス基材の両面に温度630℃にてAl板(厚み0.4mm)を接合し、エッチングによりAl回路を形成した後、無電解Niめっきを施してセラミックス回路基板を作製した。
得られたセラミックス回路基板を、4mm×20mmのサイズに切り出し、線熱膨張係数の測定用試験片を作製した。得られた試験片に対して熱膨張計(セイコー電子工業株式会社製、商品名「TMA300」)を用いて5℃/分で降温することにより、温度25℃から150℃の線熱膨張係数を測定した。
下記計算式を用いて、線熱膨張係数の理論値を算出した。
α2=Σαi・Ei・Vi/ΣEi・Vi
上記計算式中、αは熱膨張係数、Eはヤング率、Vは体積分率を示し、添え字iは複合材料における各材料成分を示す。
なお、複合材料における各材料成分の熱膨張係数及びヤング率は、以下の表2に示す値を用いて算出した。
Al-SiC(65%)材をサイズが140×190×5mmとなるように加工した後、無電解Niめっきを施したベース板を用い、上記実施例及び比較例で得られたセラミックス回路基板とベース板を、共晶半田にて接合して測定用サンプルとした。
測定用サンプルにおけるベース板の放熱面の形状を3次元輪郭測定装置(株式会社東京精密製、商品名「コンターレコード1600D-22」)を用いて測定することで、長さ10cmに対するベース板の反り変化量を測定した。
Claims (7)
- セラミックス基材と、前記セラミックス基材の両面に設けられ、Al及び/又はCuを含む金属層と、を備え、
前記金属層が第一金属層及び第二金属層を有し、前記セラミックス基材、前記第一金属層及び前記第二金属層がこの順に積層されており、
前記第一金属層が、Cu又はAlで形成されており、
25℃~150℃における線熱膨張係数の測定値α1が5×10-6~9×10-6/Kであり、
25℃~150℃における線熱膨張係数の理論値α2に対する前記α1の比α1/α2が0.7~0.95であり、
前記金属層のうちの少なくとも一方が金属回路を形成している、セラミックス回路基板。 - 前記セラミックス基材が、AlN、Si3N4又はAl2O3で形成されている、請求項1に記載のセラミックス回路基板。
- 前記セラミックス基材の厚みが0.2~1.5mmである、請求項1又は2に記載のセラミックス回路基板。
- 前記第二金属層が、Cu、Al、Cu及びMoを含む合金、並びにCu及びWを含む合金からなる群より選ばれる少なくとも1種で形成されている、請求項1~3のいずれか一項に記載のセラミックス回路基板。
- 前記金属層の厚みが0.1~2.0mmである、請求項1~4のいずれか一項に記載のセラミックス回路基板。
- 前記第二金属層がCuを含む、請求項1~5のいずれか一項に記載のセラミックス回路基板。
- 前記第一金属層の端面と前記第二金属層の端面とが面一である、又は、前記第一金属層の端面が前記第二金属層の端面よりも外側にはみ出ている、請求項1~6のいずれか一項に記載のセラミックス回路基板。
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Application Number | Priority Date | Filing Date | Title |
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JP2017151888 | 2017-08-04 | ||
JP2017151888 | 2017-08-04 | ||
PCT/JP2018/028422 WO2019026834A1 (ja) | 2017-08-04 | 2018-07-30 | セラミックス回路基板 |
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JPWO2019026834A1 JPWO2019026834A1 (ja) | 2020-06-18 |
JP7211949B2 true JP7211949B2 (ja) | 2023-01-24 |
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US (1) | US11096278B2 (ja) |
EP (1) | EP3664585B1 (ja) |
JP (1) | JP7211949B2 (ja) |
CN (1) | CN110999544B (ja) |
WO (1) | WO2019026834A1 (ja) |
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DE102018104521B4 (de) * | 2018-02-28 | 2022-11-17 | Rogers Germany Gmbh | Metall-Keramik-Substrate |
JP7237032B2 (ja) * | 2020-02-17 | 2023-03-10 | 富士フイルム株式会社 | 圧電膜付き基板、圧電素子及び振動発電素子 |
CN114171663A (zh) * | 2021-12-07 | 2022-03-11 | 丰鹏电子(珠海)有限公司 | 散热基板及其制备方法 |
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JP2006100640A (ja) * | 2004-09-30 | 2006-04-13 | Hitachi Metals Ltd | セラミックス回路基板及びこれを用いたパワー半導体モジュール |
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2018
- 2018-07-30 WO PCT/JP2018/028422 patent/WO2019026834A1/ja unknown
- 2018-07-30 CN CN201880050613.2A patent/CN110999544B/zh active Active
- 2018-07-30 EP EP18841449.4A patent/EP3664585B1/en active Active
- 2018-07-30 JP JP2019534494A patent/JP7211949B2/ja active Active
- 2018-07-30 US US16/636,239 patent/US11096278B2/en active Active
Patent Citations (6)
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JP2000294699A (ja) | 1999-04-08 | 2000-10-20 | Mitsubishi Electric Corp | 半導体装置の絶縁性放熱板およびその製造方法 |
JP2001127157A (ja) | 1999-11-01 | 2001-05-11 | Hitachi Ltd | 半導体装置 |
JP2002203942A (ja) | 2000-12-28 | 2002-07-19 | Fuji Electric Co Ltd | パワー半導体モジュール |
JP2006245437A (ja) | 2005-03-04 | 2006-09-14 | Hitachi Metals Ltd | セラミックス回路基板およびパワーモジュール並びにパワーモジュールの製造方法 |
JP2008283184A (ja) | 2007-05-12 | 2008-11-20 | Semikron Elektronik Gmbh & Co Kg | 焼結されたパワー半導体基板並びにそのための製造方法 |
JP2015220295A (ja) | 2014-05-15 | 2015-12-07 | 三菱電機株式会社 | パワーモジュール及びその製造方法 |
Also Published As
Publication number | Publication date |
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EP3664585B1 (en) | 2022-04-13 |
WO2019026834A1 (ja) | 2019-02-07 |
EP3664585A4 (en) | 2020-07-15 |
US20200375029A1 (en) | 2020-11-26 |
EP3664585A1 (en) | 2020-06-10 |
CN110999544B (zh) | 2024-06-07 |
US11096278B2 (en) | 2021-08-17 |
CN110999544A (zh) | 2020-04-10 |
JPWO2019026834A1 (ja) | 2020-06-18 |
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