JP7206882B2 - Phase difference adjustment circuit - Google Patents

Description

The present invention relates to a circuit that adjusts the phase difference between transmission channels in a system that has a plurality of transmission channels and transmits phase-modulated signals.

In a device that transmits, for example, BPSK (Binary Phase Shift Keying) modulated signals through a plurality of transmission channels, the effective value of phase error between the plurality of channels is required to be less than 10°.

Japanese Patent Publication No. 10-503634

In order to correct the phase difference according to the above requirements, it was necessary to use a separate measuring instrument.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase difference adjusting circuit capable of correcting phase errors between a plurality of channels and between each channel without using a measuring instrument.

According to the phase difference adjustment circuit of claim 1, one of a plurality of transmission channels for transmitting phase-modulated signals is used as a reference channel when performing phase correction. A phase difference detection circuit is connected between the output terminal of the reference channel and the output terminal of the other transmission channel, and detects a state in which the relative phase difference between the transmission signals of the two is a predetermined value. Then, the adjustment circuit sets a correction vector for each channel and refers to the output of the phase difference detection circuit, so that the relative phase difference between the correction vector for the reference channel and the correction vector for the other transmission channels is Adjustment is made so as to obtain the predetermined value. Specifically, intra-channel phase accuracy correction is first performed on the reference channel, and then inter-channel relative phase correction is performed between the reference channel and the other transmission channels.

With this configuration, the phase difference adjustment circuit can adjust the relative phase difference between a plurality of transmission channels using a phase difference detection circuit that detects a phase difference of a predetermined value that can be easily configured. It is no longer necessary to make adjustments using

According to the phase difference adjusting circuit of claim 2, a phase difference detecting circuit in which the predetermined value is set to 180° is used, and the adjusting circuit detects the difference between the correction vector of the reference channel and the correction vector of the other transmission channels. Set and adjust the relative phase difference to 180°. That is, since the phase difference detection circuit in which the predetermined value is set to 180° can be configured more simply, the phase difference adjustment circuit itself can be configured easily.

1 is a functional block diagram showing the configuration of a transmission device according to the first embodiment; FIG. FIG. 4 shows correction vectors set for transmission channels TX1 and TX2, respectively; Flowchart showing intra-channel quadrature phase accuracy correction processing Flowchart showing inter-channel relative phase correction processing FIG. 11 is a diagram showing correction vectors set in the transmission channels TX1 and TX2, respectively, according to the second embodiment; Flowchart showing inter-channel relative phase correction processing

(First embodiment)
As shown in FIG. 1, a transmission device 1 of this embodiment transmits a BPSK signal, which is a phase-modulated signal, and has two transmission channels TX1 and TX2. The PLL circuit 2 multiplies a reference frequency signal Xtal input from an external oscillator (not shown) by a predetermined multiplication rate, and supplies it to the transmission channels TX1 and TX2 and the first phase adjuster 3 . A reference frequency signal Xtal is also input to the first phase adjuster 3 . For example, the frequency of the reference frequency signal Xtal is about 50 MHz, and the frequency of the signal output from the PLL circuit 2 is about 40 GHz.

The transmit channel TX1 comprises an input buffer 4(1), a phase shifter 5(1), a doubler 6(1), an output buffer 7(1), a combiner or coupler 8(1) and a power detector 9(1). ). The transmission channel TX2 is configured symmetrically with the transmission channel TX1, and includes an input buffer 4(2) to a power detector 9(2). The phase shifters 5 ( 1 ) and 5 ( 2 ) are controlled via the central logic section 10 from the logic section 12 incorporated in the first phase adjustment section 3 .

The output signal of the PLL circuit 2 is input to the IQ mixer 11 of the first phase adjustment section 3 and the reference frequency signal Xtal is input to the logic section 12 of the first phase adjustment section 3 . The logic unit 12 generates a phase IQ (Δ _BB ) to be input to the IQ mixer 11 . The IQ mixer 11 outputs to the 2-multiplying circuit 13 an IQ signal containing IQ for the input phase. The doubling circuit 13 inputs to the mixer 14 a signal S2 obtained by doubling the frequency of the input IQ signal.

The output signal of the transmission channel TX2 is input to the mixer 14 via the coupler 8(2) and the switch 15 as the signal S1. The switch 15 is turned off when the transmitting device 1 performs normal transmission. The mixer 14 inputs to the A/D converter 16 a signal S3 obtained by multiplying the signals S1 and S2. The A/D converter 16 inputs data obtained by A/D converting the signal S3 to the logic section 12 . The logic section 12 inputs a control signal to the central logic section 10 . The logic units 10 and 12 correspond to adjustment circuits.

In this embodiment, the transmission channel TX2 is used as a reference channel for correction. Here, each of the signals S1 to S3 is represented by the following equations.
S1=A·sin {ωt+φr(T)+φr(PSr)}
S2=B·sin(ωt+ _2ΔBB +Δ)
S3=AB/2·cos{φr(T)+φr(PSr) _−2ΔBB −Δ}
A, B: Amplitude coefficients of signals S1 and S2 φr(T): Fluctuation of reference channel phase due to temperature T φr(PSr): Phase given by phase shifter 5(2) _ΔBB : Logic unit 12 Δ: the phase difference between the reference channel TX2 and the first phase adjuster 3

A second phase adjuster 17 is connected between the transmission channels TX1 and TX2 via couplers 8(1) and 8(2). The second phase adjustment section 17 has a phase detection circuit 18 . The phase detection circuit 18 is configured to detect only the state where the relative phase difference between the output signals of the transmission channels TX1 and TX2 is 180°. A detection signal from the phase detection circuit 18 is input to the logic section 12 .

Next, the operation of this embodiment will be described. In adjusting the relative phases of the transmission channels TX1 and TX2, correction vectors (1) and (2) are set for each transmission channel, respectively, as shown in FIG. For the transmission channel TX1, the correction vectors (1) and (2) are both set to "1" on the unit circle. For transmission channel TX2, correction vector (1) is set to 10 ^a1/20 e ^jφ1 and correction vector (2) is set to 10 ^a2/20 e ^j(φ2+180) . a1 and a2 are amplitude variations [dB], and φ1 and φ2 are phase variations [deg]. First, the intra-channel quadrature phase accuracy is corrected, and then the inter-channel relative phase correction is performed.

<Intra-channel quadrature phase accuracy correction>
As shown in FIG. 3, first, the phase adjusters 3 and 17, the transmission channels TX1 and TX2, the PLL circuit 2 and the central logic section 10 are activated (S1). Next, the central logic unit 10 controls the phase shifter 5(2) of the transmission channel TX2 to give a phase for setting the correction vector (1) (S2).

Next, the logic unit 12 sets an arbitrary phase _ΔBB0 to the IQ mixer 11 (S3) and turns on the switch 15 (S4). _At this time, data obtained by A/D converting the DC value of the signal S3 output from the mixer 14 by the A/D converter 16 is set as S30 and stored in the logic section 12 (S5).

Next, the central logic unit 10 controls the phase shifter 5(2) of the transmission channel TX2 to give a phase for setting the correction vector (2) (S6). The logic unit 12 sets the phase _ΔBB90 , which is obtained by increasing the phase _ΔBB0 by 90°, in the IQ mixer 11 (S7). At this time, data obtained by A/D converting the DC value of the signal S3 output from the mixer 14 by the A/D converter 16 is set as S3 ₁₈₀ and stored in the logic section 12 (S8).

Then, central logic unit 10 increases the phase of phase shifter 5(2) (S12) so that data S3 ₀ and data S3 ₁₈₀ are equal (S9). When the data _S30 and the data _S3180 are equal (S9; YES), the logic section 12 stores the phase set in the phase shifter 5(2) at that time (S10). After that, the switch 15 is turned off (S11).

<Inter-channel relative phase correction>
As shown in FIG. 4, when the same processing as step S1 is first performed (S21), the central logic unit 10 gives the phase for setting the correction vector (2) to the phase shifter 5 (2) ( S22), the phase for setting the correction vector (1) is given to the phase shifter 5(1) (S23). Then, referring to the output of the phase detection circuit 18, it is determined whether or not the phase difference between the output signals of the transmission channels TX1 and TX2 has reached 180° (S24).

If the phase difference is not 180° (S24; NO), the logic section 12 increases the phase of the phase shifter 5(1) via the central logic section 10 (S16). When the phase difference reaches 180° (S24; YES), the logic section 12 stores the phase set in the phase shifter 5(1) at that time (S25).
It should be noted that the amount of drift caused by the influence of temperature during normal communication may be corrected by executing the processing shown in FIGS.

As described above, according to the present embodiment, of the transmission channels TX1 and TX2, the transmission channel TX2 is used as the reference channel when performing phase correction. A phase difference detection circuit 18 is connected between the output terminal of the reference channel TX2 and the output terminal of the transmission channel X1, and detects a state where the relative phase difference between the transmission signals of both is a predetermined value of 180°. Then, the logic units 10 and 12 set a correction vector for each channel and refer to the output of the phase difference detection circuit 18 to determine the relative values of the correction vector of the reference channel and the correction vectors of the other transmission channels. The phase difference is adjusted to 180°.

With this configuration, it is possible to adjust the relative phase difference between a plurality of transmission channels by using the phase difference detection circuit 18 for detecting the 180° phase difference, which can be easily configured, so that a separate measuring device is used for adjustment. you don't have to do it.

(Second embodiment)
Hereinafter, the same parts as those of the first embodiment are denoted by the same reference numerals, and descriptions thereof are omitted, and different parts are described. In the second embodiment, instead of the phase difference detection circuit 18, a phase difference detection circuit that detects a phase difference of 90° is used. As shown in FIG. 5, four vectors (1) to (4) are set for each 90° phase difference in the transmission channel TX2, which is the reference channel. If correction vector (1) is set to 10 ^a1/20 e ^jφ1 , vectors (2) to (4) are expressed as follows.
Correction vector (2): 10 ^a2/20 e ^{j (φ2+90)}
Correction vector (3): 10 ^a3/20 e ^{j (φ3+180)}
Correction vector (4): 10 ^a4/20 e ^{j (φ4+270)}

In the flowchart shown in FIG. 6, in step S27 instead of step S22, the central logic unit 10 gives the phase for setting the correction vector (1) to the phase shifter 5(2). In step S28 replacing step S24, the output of the phase detection circuit is referenced to determine whether or not the phase difference between the output signals of the transmission channels TX1 and TX2 has reached 90°.
As described above, according to the second embodiment, even when a phase difference detection circuit that detects a phase difference of 90° is used, the same effect as in the first embodiment can be obtained.

(Other embodiments)
The number of transmission channels may be "3" or more.
The transmission signal is not limited to a BPSK signal, and may be a QPSK signal.
Specific numerical values of the frequency may be appropriately changed according to individual designs.
A circuit that multiplies by 3 or more may be used instead of the 2-multiply circuit.

Although the present disclosure has been described with reference to examples, it is understood that the present disclosure is not limited to such examples or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

In the drawing, 1 is a transmitter, 3 is a first phase adjuster, 5 is a phase shifter, 10 is a central logic section, 12 is a logic section, and 18 is a phase difference detection circuit.

Claims (2)

Using one (TX2) of a plurality of transmission channels (TX1, TX2) for transmitting phase-modulated signals as a reference channel when performing phase correction,
a phase difference detection circuit (18) connected between the output terminal of the reference channel and the output terminal of the other transmission channel and detecting a state in which the relative phase difference between the two transmission signals is a predetermined value;
By setting a correction vector for each channel and referring to the output of the phase difference detection circuit, the relative phase difference between the correction vector of the reference channel and the correction vector of the other transmission channel is the predetermined value. and an adjustment circuit (3, 1 0 ) that adjusts so that
The adjustment circuit first performs intra-channel phase accuracy correction for the reference channel, and then performs inter-channel relative phase correction between the reference channel and the other transmission channels . The predetermined value of the phase difference detection circuit is set to 180°,
2. The phase difference adjustment circuit according to claim 1, wherein said adjustment circuit sets and adjusts the relative phase difference between the correction vector of said reference channel and the correction vector of said other transmission channel to 180 degrees.

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