JP7168487B2 - Transfer control device, information processing device and machine tool - Google Patents

Description

The present invention relates to a transfer control device, an information processing device and a machine tool.

A multiprocessor system is known in which a plurality of processors transfer data to and from the same memory. In a multiprocessor system, the fact that a plurality of processors monitor each other's data transfer and transfer data at a timing that does not overlap with other processors is a factor that limits the computing power of the processors. Therefore, a DMA controller (DMA processor) is widely used that accepts data transfer requests from a plurality of processors, temporarily stores the information, and sequentially transfers data without duplication.

For example, Patent Literature 1 discloses that "outside each processor, a generating means for generating a trigger signal for activating a DMA processor, and a transmission bus for transmitting the trigger signal from this generating means to the DMA processor of each processor, A multiprocessor system characterized by inputting a trigger signal so that the operation periods of the DMA processors of the respective processors do not overlap each other.

JP-A-2006-29386

Each processor may split the data multiple times and request the data transfer from the DMA controller. In such a case, it may be impossible to process the data unless a series of data transfers is completed, so it is desirable to perform a series of data transfers continuously. However, in the system described in Patent Document 1, a data transfer request from another processor may interrupt a series of data transfers.

Although it is possible for each processor to monitor the status of other processors' data transfer requests so as not to interrupt the other processor's series of data transfers, the latency of the processors increases. For example, in a control device of a machine tool, since the computation load is large, there is a possibility that the processing time becomes long if the processor has a waiting time. For this reason, a transfer control device is desired that can continuously perform a series of data transfers continuously requested by one processor.

A transfer control device according to an aspect of the present disclosure is a transfer control device that performs data transfer in response to requests from a plurality of processors, and includes: a schedule storage unit capable of storing an instruction set describing information for each data transfer; a transfer control unit that sequentially executes the instruction set stored in the schedule storage unit; a transfer instruction set that is the instruction set describing information related to the data transfer according to requests from the plurality of processors; a primary storage unit for storing a plurality of dummy instruction sets corresponding to a plurality of processors and each of which is the instruction set describing information for performing an empty data transfer; and writing the instruction sets to the primary storage unit, an instruction set setting unit that writes the instruction set read from the primary storage unit to the scheduled storage unit, wherein the instruction set setting unit issues a request when a data transfer request is received from the processor. If the transfer instruction set corresponding to the processor exists, a new transfer instruction set is interrupted after the last transfer instruction set corresponding to the processor that issued the request, and the transfer instruction set corresponds to the processor that issued the request. If the transfer instruction set does not exist, the new transfer instruction set is interrupted next to the dummy instruction set corresponding to the processor that issued the request.

When data transfer requests are made continuously from the same processor, these data transfers can be performed continuously.

1 is a block diagram showing the configuration of an information processing device according to an embodiment of the present disclosure; FIG. 2 is a flow chart showing a control procedure in a transfer control device of the information processing device of FIG. 1; 3 is a schematic diagram illustrating an example of an instruction set that is set when there is no data transfer request in the primary storage unit of the transfer control device of the information processing device of FIG. 1; FIG. 2 is a schematic diagram illustrating an example of an instruction set set when a data transfer request is made in a primary storage unit of a transfer control device of the information processing device of FIG. 1; FIG. 2 is a schematic diagram illustrating an example of an instruction set set when there is a transfer request to be subsequently performed in a primary storage unit of a transfer control device of the information processing device of FIG. 1; FIG. 2 is a schematic diagram illustrating an example of an instruction set set when a final data transfer request of a series of data transfer requests is made in a primary storage unit of a transfer control device of the information processing device of FIG. 1; FIG. 2 is a schematic diagram illustrating an example of an instruction set set when a final data transfer request of a series of data transfer requests is made following a primary storage unit of a transfer control device of the information processing apparatus of FIG. 1; FIG. 2 is a block diagram of a machine tool including the information processing device of FIG. 1; FIG.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an information processing device 100 according to an embodiment of the present disclosure. The information processing apparatus 100 of FIG. 1 includes n (n is plural) processors P1, P2, . and a communication interface 2 for communicating with an external device according to data transferred from the processors P1, P2, . . . Pn.

The processors P1, P2, . Each of the processors P1, P2, . . . Pn requests the transfer control device 1 to transfer data each time data transfer becomes necessary. Multiple processors P1, P2 . . . Pn may be formed in a single integrated circuit. As an example, the plurality of processors P1, P2 . . . Pn may be cores of a multi-core CPU.

As will be described in detail below, the transfer control device 1 does not process data transfer requests from other processors when successive data transfer requests are made from one of the processors. Continuous data transfer.

The transfer control device 1 includes a schedule storage unit 10 capable of storing an instruction set describing data transfer information, a transfer control unit 20 sequentially executing the instruction sets stored in the schedule storage unit 10, and a plurality of processors. P1, P2, . A primary storage unit 30 that stores a plurality of dummy instruction sets that are described instruction sets, an instruction set setting unit 40 that writes the instruction sets read from the primary storage unit 30 to the scheduled storage unit 10, and a timer 50 for inputting a trigger signal.

The schedule storage unit 10 is composed of a memory. The instruction set stored in the schedule storage unit 10 includes read source information specifying the address of the read source of the data to be transferred, transfer destination information specifying the address of the transfer destination of the data, and then the instruction set setting unit 40 Next address information specifying the address of the instruction set to be read from the primary storage unit 30 and command information specifying the operation of the communication interface 2 can be included.

Each time a trigger signal is input from the timer 50, the transfer control unit 20 sequentially executes the instruction sets stored in the schedule storage unit 10, that is, according to the information described in the instruction set, using the communication interface 2 Transfer data. A known DMA controller can be used as such a transfer control unit 20 .

The primary storage unit 30 is composed of memory. The instruction set stored in primary storage 30 may contain the same types of information as the instruction set stored in schedule storage 10 may contain.

The instruction sets stored in the primary storage unit 30 include a plurality of transfer instruction sets and dummy instruction sets corresponding to the processors Pi (i is a natural number between 1 and n), and a dummy instruction set corresponding to the processors Pi in the primary storage unit 30. and a return instruction set for transferring overwriting the next address information in the instruction set with the address of the dummy instruction set corresponding to processor Pi+1 (P1 when i=n). The next address information for the transfer instruction set describes the next address information for executing the transfer instruction set in order and finally reading the dummy instruction set corresponding to the processor Pi+1 into the schedule storage unit 10 .

The dummy instruction set stored in the primary storage unit 30 corresponds to a plurality of processors P1, P2, . In the dummy instruction set corresponding to Pi, next address information for reading the dummy instruction set corresponding to processor Pi+1 into the schedule storage unit 10 is described.

The instruction set setting unit 40 is composed of an arithmetic unit (MPU). When the transfer control unit 20 performs the transfer, the instruction set setting unit 40 reads out the next scheduled transfer from the primary storage unit 30 according to the next address information described in the instruction set, and stores the free space in the scheduled storage unit 10. Add to

The processors P1, P2, . . . Pn overwrite the next address information of the dummy instruction set corresponding to themselves in the primary storage unit 30 with the address of the transfer instruction set corresponding to themselves as an operation for requesting the transfer.

Specifically, when there is no transfer request, when the transfer control unit 20 executes the dummy instruction set corresponding to the processor Pi, the next address information describes the address of the dummy instruction set corresponding to the processor Pi+1. Therefore, the instruction set setting unit 40 reads the dummy instruction set corresponding to the processor Pi+1 from the primary storage unit 30 and adds it to the empty area of the scheduled storage unit 10 . By repeating this, dummy instruction sets corresponding to all processors continue to be executed in order.

As an operation for the processor Pi to request the transfer, by rewriting the next address information of the dummy instruction set corresponding to the processor Pi to the address of the transfer instruction set corresponding to the processor Pi, the transfer instruction set corresponding to the processor Pi is executed. In the process, the next address information of the dummy instruction set corresponding to processor Pi returns to the address of the dummy instruction set corresponding to processor Pi+1.

The timer 50 outputs, for example, a square-wave trigger signal at regular time intervals. As such a timer 50, one having a well-known configuration can be used. The interval at which the timer 50 outputs the trigger signal is the time during which the transfer control unit 20 can complete one transfer. Therefore, the interval between trigger signals output by the timer 50 is sufficiently longer than the interval between a plurality of data transfer requests to be processed continuously issued from the processors P1, P2 . . . Pn. Therefore, it is considered that the processors P1, P2, .

The communication interface 2 is a well-known control device that controls data exchange with an external device via a data bus. As such a communication interface 2, for example, an SPI controller (Serial Periheral Interface Controller) or the like can be used.

The communication interface 2 cannot operate with only one data transfer (write) from the processor. A device or the like that communicates with other devices may be used. If another processor transfers data to the same communication interface 2 immediately after one processor starts a series of data transfers to the communication interface 2, the communication interface 2 cannot operate normally.

However, since the transfer control device 1 includes the instruction set setting unit 40 that interrupts a new transfer instruction set after the last transfer instruction set corresponding to the processor that issued the request, a series of data requested by one processor cannot be processed. Even if another processor requests data transfer before the transfer is completed, the transfer control unit 20 preferentially performs a series of data transfers for the processors that requested the transfer first. This ensures normal communication of the communication interface 2 .

Next, the flow of data transfer processing in the transfer control device 1 having the above configuration will be described. FIG. 2 is a flow chart showing a control procedure in the transfer control device 1 of FIG. 3 to 7 schematically show instruction sets stored in the primary storage unit 30. FIG.

The data transfer processing by the transfer control device 1 is such that the dummy instruction sets D1, D2 corresponding to the respective processors P1, P2 . . . Pn stored in the primary storage unit 30 are sequentially executed. . . Dn next address information setting step (step S1: dummy instruction set setting step), a step of confirming the absence of a transfer request from the processors P1, P2 . . . Pn (step S2: transfer request confirmation step), A transfer instruction set Ti(k) (k is a natural number indicating the number of the previous data transfer request issued by each of the processors P1, P2, . ) exists (step S3: transfer instruction set confirmation step), and a step of interrupting a new transfer instruction set Ti(1) next to the dummy instruction set corresponding to the requesting processor ( step S4: initial instruction set interrupt step), and a step of interrupting the transfer instruction set Ti(k+1) following the new data transfer request next to the last transfer instruction set Ti(k) corresponding to the requesting processor (step S5). : continuous instruction set interrupt step); and a step of checking whether the last transfer instruction set Ti (1 or k+1) is the last data transfer request of a series of data transfer requests (step S6: end confirmation step); , after the last transfer instruction set Ti (1 or k+1), the address of the dummy instruction set Di+1 corresponding to the processor Pi+1 next to the processor Pi that issued the data transfer request related to the transfer instruction set Ti (1 or k+1) as follows: a step of interrupting a return instruction set Ri, which is an instruction set describing information for performing empty data transfer as address information (step S7: return instruction set interruption step).

In the dummy instruction set setting process of step S1, as shown in FIG. 3, the instruction set setting unit 40 writes the dummy instruction sets D1, D2, . . . In FIG. 3, it is assumed that the transfer control unit 20 processes (executes data transfer) in order from the upper instruction set. In FIG. 3, the dummy instruction set D1 corresponding to the processor P1 is processed first. Then write a new dummy instruction set D1.

In the transfer request confirmation process of step S2, the instruction set setting section 40 confirms whether there is a data transfer request from the processors P1, P2, . . . Pn. This step is executed when the dummy instruction set Di corresponding to the processor Pi is executed. The address information is the address of the dummy instruction set Di+1, and when there is a transfer request, the next address information is any address of the transfer instruction set Ti(k) of each processor. If there is a data transfer request from any one of the processors P1, P2, . If there is no transfer request, the process returns to step S1.

In the transfer instruction set confirmation process of step S3, the instruction set setting unit 40 confirms the instruction set of the primary storage unit 30, and determines whether or not there is a transfer instruction set Ti(k) corresponding to the processor Pi requesting the data transfer. determine whether If the transfer instruction set Ti(k) corresponding to the processor Pi that requested the data transfer does not exist, the process advances to step S4. goes to step S5.

In the initial instruction set interrupt step of step S4, as shown in FIG. 4, a new transfer instruction set Ti(1) related to the data transfer requested next to the dummy instruction set Di corresponding to the processor Pi that requested the data transfer is generated. is performed, the next address information of the dummy instruction set Di is changed to the address of the transfer instruction set Ti(1). This initial instruction set interrupt process is executed when there is no transfer instruction set Ti(k) corresponding to the processor Pi that requested data transfer to the primary storage unit 30 in the transfer instruction set confirmation process of step S3. , the number of the transfer instruction set explained for convenience is 1.

In the continuous instruction set interrupt step of step S5, the instruction set setting unit 40, as shown in FIG. 5, sets the k-th transfer instruction set Ti ( After k), a new transfer instruction set Ti(k+1) relating to the requested data transfer is interrupted. For the sake of convenience, the data transfer and the corresponding instruction set are numbered for explanation. number k of .

After executing either the initial instruction set interruption process of step S4 or the continuous instruction set interruption process of step S5, the process proceeds to step S6.

In the end confirmation process of step S6, the instruction set setting unit 40 checks that the transfer instruction set Ti (1 or k+1) performed by the transfer control unit 20 is a series of data to be processed continuously issued from the processor Pi requesting the data transfer. is related to the last data transfer request of the other data transfer requests. If the transfer command set Ti(1 or k+1) performed by the transfer control unit 20 is related to the last data transfer request of a series of data transfer requests, the process proceeds to step S7, and the newly written transfer command set Ti(1 Alternatively, if k+1) is not related to the last data transfer request of the series of data transfer requests, the process returns to step S1.

In the return instruction set interrupt process of step S7, as shown in FIG. 6, after the transfer instruction set Ti (1 or k+1) related to the last data transfer request, the processor Pi requesting the data transfer to the transfer control unit 20 Transfer processing for overwriting the next address information of the dummy instruction set Di with the address of the dummy instruction set Di+1 corresponding to the next processor Pi+1 is executed, and the next address information of the transfer processing itself is the address of the dummy instruction set Di+1. Interrupt instruction set Ri.

The processes of steps S1 to S7 are repeatedly executed while the transfer control device 1 is in operation.

According to such control, before the last data transfer request of a series of data transfer requests to be continuously processed by the processor Pi, another processor Pj (j is 1 or more and n or less and a natural number other than i) requests data transfer, the transfer instruction set Tj(1) corresponding to the data transfer request from the processor Pj is written after the corresponding dummy instruction set Dj as shown in FIG. There is no interruption between transfer instruction sets Ti(1 to k) corresponding to a series of requested data transfers. In FIG. 7, j is illustrated as being larger than i, but if j is smaller than i, the data transfer requested by the processor Pj later than the series of data transfers requested by the processor Pj. A transfer instruction set Tj(1) corresponding to a data transfer may be written.

The transfer control device 1 of this embodiment described above corresponds to a plurality of processors P1, P2, . Dummy instruction sets D1, D2, . If the set Ti(k) exists, a new transfer instruction set Ti(k+1) is interrupted next to the last transfer instruction set Ti(k) corresponding to the requesting processor Pi, and the requesting processor Pi If there is no transfer instruction set corresponding to , a new transfer instruction set Ti(1) is interrupted next to the dummy instruction set Di corresponding to the processor Pi that issued the request. For this reason, when the transfer control unit 20 continuously issues data transfer requests from the same processor Pi, the transfer control device 1 does not receive a data transfer request from the processor Pi even if there is a data transfer request from another processor. data transfers can be performed continuously.

Next, an embodiment of a machine tool according to the present disclosure will be described. FIG. 8 is a block diagram of a machine tool including the information processing device 100 of FIG.

The machine tool of this embodiment includes an information processing device 100 in FIG. and a plurality of drive axes X1, X2, X3 controlled by

The servo controllers 201, 202, 203 can be configured by known servo controllers, and the plurality of drive axes X1, X2, X3 are configured to be driven by servo motors controlled by the respective servo controllers 201, 202, 203. can be

The processors P1, P2, . Specifically, the processors P1, P2, . Processors P1, P2, .

In the machine tool according to the present disclosure, the information processing device 100 including the transfer control device 1 that continuously transfers data requested by the same processor Pi as described above controls the drive axes X1, X2, and X3 based on the machining program. , there is no waiting time when the processors P1, P2 . . . Thus, the processors P1, P2, . . . Pn can be programmed to calculate a more favorable motion of the drive axes X1, X2, X3 based on more information. Therefore, the machine tool according to the present disclosure can achieve high machining accuracy.

Although the embodiments of the present disclosure have been described above, the transfer control device, the information processing device, and the machine tool according to the present disclosure are not limited to the above-described embodiments. Moreover, the effects described in the present embodiment are merely enumerations of the most suitable effects resulting from the present disclosure, and the effects of the present disclosure are not limited to those described in the present embodiment.

Although the dummy instruction set setting unit of the above-described embodiment writes the same number of dummy instruction sets as the number of processors into the primary storage unit, the dummy instruction set setting unit writes one dummy instruction set corresponding to each processor. More dummy instruction sets than the number of processors may be written as long as they are written sequentially.

The instruction set setting unit of the above-described embodiment is configured to interrupt the return instruction set after the transfer instruction set corresponding to the last data transfer request. By setting the address of the dummy instruction set corresponding to the processor next to the processor that issued the transfer request, the dummy instruction set corresponding to the next processor can be processed after a series of data transfers without writing the return instruction set. You may make it

The transfer control device described above processes one instruction set each time a trigger is input from the timer. The next instruction set may be processed immediately after the processing of .

1 transfer control device 10 schedule storage unit 20 transfer control unit 30 primary storage unit 40 instruction set setting unit 50 timer 100 information processing device 201, 202, 203 servo controller P1, P2 .

Claims (5)

A transfer control device that transfers data in response to requests from a plurality of processors,
a schedule storage unit capable of storing an instruction set each describing data transfer information;
a transfer control unit that sequentially executes the set of instructions stored in the schedule storage unit;
a transfer instruction set, which is the instruction set in which information related to the data transfer is described in response to requests from the plurality of processors; a primary storage unit that stores a plurality of dummy instruction sets that are instruction sets;
an instruction set setting unit that writes the instruction set to the primary storage unit and writes the instruction set read from the primary storage unit to the scheduled storage unit;
with
When there is a data transfer request from the processor, the instruction set setting unit, if there is the transfer instruction set corresponding to the requesting processor, transfers the last transfer instruction set corresponding to the requesting processor. interrupting a new transfer instruction set next to the transfer instruction set, and if the transfer instruction set corresponding to the processor that issued the request does not exist, following the dummy instruction set corresponding to the processor that issued the request; A transfer controller for interrupting a new set of transfer instructions. The instruction set includes next address information specifying the address of the instruction set to be executed next,
The instruction set setting unit
when a data transfer request is received from the processor, writing the new transfer instruction set to the scheduled storage unit;
2. The transfer according to claim 1, wherein the next address information of the last transfer instruction set corresponding to the processor that issued the request or the dummy instruction set corresponding to the processor that issued the request is rewritten to the address of the new transfer instruction set. Control device. The instruction set setting unit
Next to the newly written transfer instruction set, the address of the dummy instruction set corresponding to the processor next to the processor that issued the request is used as the next address information, and information for performing an empty data transfer is described. 3. The transfer control device according to claim 2, wherein a return instruction set, which is said instruction set, is interrupted. A transfer control device according to any one of claims 1 to 3, a plurality of processors requesting data transfer from said transfer control device, and a communication interface communicating with the outside in accordance with data transferred via said transfer control device. An information processing device comprising: An information processing device according to claim 4, and a servo controller that communicates with the information processing device and controls a drive shaft,
A machine tool, wherein the processor of the information processing device calculates a desired motion of the drive axis based on a machining program.

Images