CN100481044C

CN100481044C - Data processing apparatus

Info

Publication number: CN100481044C
Application number: CNB2007100788221A
Authority: CN
Inventors: 南崇博
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2006-02-22
Filing date: 2007-02-15
Publication date: 2009-04-22
Anticipated expiration: 2027-02-15
Also published as: JP4446968B2; US20070208886A1; CN101025722A; JP2007226374A

Abstract

The present invention provides a DMA mode data processing device capable of high-speed data processing and effective use of a memory bus. For the DMA circuit that performs at least one of writing data into the memory and reading data from the memory, a switch SW that operates according to an instruction of the CPU is provided, and the memories of the first DMA circuit and the second DMA circuit can be transferred based on the CPU instruction. The data lines and the command signal lines are connected by wires. Thus, while one DMA circuit is performing writing data to or reading data from memory, another DMA circuit can retrieve data and can transfer data to other addresses in memory or transfer data to an input/output device.

Description

Data processing equipment

Technical field

The present invention relates to a kind of data processing equipment that can transmit data with the direct memory access (DMA) pattern.

Background technology

For being installed on the composite set that comprises duplicating machine, scanner, Printers and Faxes machine and the data processing equipment of image data processing, in recent years, owing to support colorize day by day and need data processing faster, therefore accelerate data processing by transmitting data with direct memory access (DMA) (being called for short DMA) pattern.

The prior art of above-mentioned data processing equipment comprises content for example shown in Figure 1.This routine data treating apparatus comprises CPU 1, storer 2 and three the inner piecemeals 3 (3a, 3b, 3c) as main control unit.Each inner piecemeal 3 comprises register 4, as the dma circuit 5 and the control circuit 6 of memory processes unit.

Fig. 2 is the illustrative flow of the DMA associative operation of CPU 1.In Fig. 1, for each register 4 provides imposing a condition from CPU 1.Dma circuit 5 is carried out to storer 2 and is write data and at least one among the reading of data from storer 2 based on being stored in imposing a condition in the register 4.Dma circuit 5 responds from the starting order of CPU 1 and starts.Write data and from storer 2 during at least one among the reading of data, dma circuit 5 proposes interrupt request to CPU 1 when finishing to storer 2.

In this data processing equipment, each dma circuit 5 is finished to storer 2 at every turn and is write data and from storer 2 during at least one among the reading of data, each dma circuit 5 proposes interrupt request to CPU 1.When CPU 1 obtained interrupt request, 1 pair of dma circuit that should start next time of CPU 5 was carried out register and is set, and provides starting order to dma circuit 5.Therefore, each dma circuit 5 is started in turn.

Under the situation of above-mentioned routine data treating apparatus, when starting each dma circuit 5 in turn, each dma circuit 5 finish at every turn to storer 2 write data and from storer 2 at least one Xiang Shixiang CPU among the reading of data 1 interrupt request is proposed, and when CPU 1 obtained interrupt request, CPU 1 was necessary for that the dma circuit that should start next time 5 carries out that registers are set and provides starting order for dma circuit 5.Therefore, produced the processing load of CPU and make the performance degradation of CPU.

In order to address this problem, the applicant has proposed a kind of data processing equipment shown in the Japanese patent application publication No. 2006-172107.

Fig. 3 is the simplified block diagram of the data processing equipment shown in the Japanese patent application publication No. 2006-172107.This data processing equipment can be carried out to storer 2 with the DMA pattern and write data and at least one among the reading of data from storer 2, and need not the intervention of CPU1, and this data processing equipment comprises CPU 1, storer 2, a plurality of (being three of 11a, 11b and 11c in the example of Fig. 3) dma circuit 11 and a plurality of (being three of 12a, 12b and 12c in this embodiment) selector circuit 12.

Dma circuit 11 (11a, 11b and 11c) is the memory processes unit, and common storage 2 is carried out access.Each dma circuit 11 is carried out to storer 2 and is write data and from storer 2 reading of data, and when at least one of finishing among writing and reading the end of output notice.Response is from the starting order of each selector circuit 12 (12a, 12b and 12c), and each dma circuit 11 beginning writes data and among storer 2 reading of data at least one to storer 2.

CPU 1 output writes data and from the sign on of storer 2 reading of data to storer 2.CPU 1 output indication is to select from the sign on of CPU 1 or from the selection instruction of the end notification of each dma circuit 11.12 responses of each selector circuit are from the sign on of CPU 1 or from the end notification of each dma circuit 11, output sign on.Each selector circuit 12 is according to the selection instruction from CPU, to making response from the sign on of CPU 1 or from the end notification of each dma circuit 11.

Fig. 4 writes data and from the key diagram of an example of storer 2 reading of data by

dma circuit

11a, 11b and 11c to storer 2.The first dma circuit 11a is arranged to write data to storer 2; Start address is arranged to address A; And will transmit byte number and be arranged to the N byte.The second dma circuit 11b is arranged to reading of data from storer 2; Start address is arranged to address A; And will transmit byte number and be arranged to the N byte.The 3rd dma circuit 11c is arranged to write data in storer 2; Start address is arranged to address B; To transmit byte number and be arranged to the M byte.

About

selector switch

12a, 12b and 12c, first selector circuit 12a is arranged to respond from the sign on of CPU 1 and exports starting order.Second selector circuit 12b is arranged to respond from the end notification of the first dma circuit 11a and exports starting order.Third selector circuit 12c is arranged to respond from the end notification of the second dma circuit 11b and exports starting order.

When dma circuit 11 and selector circuit 12 were set in this way, if CPU 1 output sign on, then first selector circuit 12a response was exported starting order from the sign on of CPU 1.The first dma circuit 11a responds from the starting order of first selector circuit 12a and starts, and with in the writing data into memory 2.Data are by in the write store 2 in turn, and the address A from storer 2 takies the N byte.When finishing with writing data into memory 2, first dma circuit 11a end of output notice.

Second selector circuit 12b response is exported starting order from the end notification of the first dma circuit 11a.Second dma circuit 11b response is started from the starting order of second selector circuit 12b, and from storer 2 reading of data.Begin from storer 2, to read the data of N byte in turn from address A.When finishing from storer 2 reading of data, second dma circuit 11b end of output notice.

Third selector circuit 12c responds from the end notification of the second dma circuit 11b and exports starting order.The 3rd dma circuit 11c responds from the starting order of third selector circuit 12c and starts, and writes data in storer 2.In turn in the write store 2, the address B from storer 2 takies the M byte with data.

Fig. 5 is the integrally-built block scheme of data processing equipment, and Fig. 6 is the block scheme of the details of expression inside piecemeal 13a shown in Figure 5.This data processing equipment comprises Memory Controller 9, arbiter and selector switch 8, a plurality of (in the example illustrated being three) inner piecemeals 13 (13a to 13c) (back can be described) of storer 2, control store 2, and CPU1.Arbiter and selector switch 8 are selected in the inner piecemeal 13 (13a to 13c) between Memory Controller 9 and inner piecemeal 13, and the bus right to use is distributed to selected inside piecemeal.

Inner piecemeal 13 comprises register 14, dma circuit 15, selector circuit 16 and control circuit 17, and dma circuit 15 can write data and among storer 2 reading of data at least one and have each function that for example scans among input function, compression input and expansion output function, rotation I/O function and the laser output function to carry out to storer 2 by arbiter and selector switch 8 control store controllers 9.

CPU 1 provides cpu address CPU_ADR and cpu data CPU_DATA for register 14.The address of cpu address CPU_ADR indicator register 14, cpu data CPU_DATA indicates imposing a condition of control circuit 17, dma circuit 15 and selector circuit 16.The cpu data CPU_DATA that provides from register 14 is provided CPU 1.The state of cpu data CPU_DATA indication control circuit 17, dma circuit 15 and selector circuit 16.

Register 14 decoding cpu address CPU_ADR, and obtain cpu data CPU_DATA writing fashionable place, address by cpu address CPU_ADR appointment.Register 14 begins to transmit cpu data CPU_DATA from the address by cpu address CPU_ADR appointment when reading.

Control circuit 17 imposes a condition computational data based on the control circuit 17 of storage in the register 14.Control circuit 17 provides the state of control circuit 17 for register 14.Control circuit 17 control input/output devices 10.Control circuit 17 provides data for input/output device 10.Control circuit 17 comprises the buffer circuit of storing data, and the data that provide from input/output device 10 are provided.

For example, if the first inner piecemeal 13a is the inside piecemeal with scanning input function, then control circuit 17 comprises timing signal generation circuit and buffering circuit.Timing signal generation circuit produces the timing of reading by the scan-data that reads from original copy as the image fetching unit of input/output device 10.Buffer circuit memory scanning data.

Dma circuit 15 transmits data based on the imposing a condition of dma circuit 15 of storage in the register 14.Impose a condition the indication start address and the transmission byte number of dma circuit 15.Dma circuit 15 provides the state of dma circuit 15 for register 14.Dma circuit 15 responds from the starting order D_TRG1 of selector circuit (back will be described) and starts.Dma circuit 15 reads the data in the buffer circuit that is stored in the control circuit 17, and writes data in the storer 2.Alternately, dma circuit 15 reads the data that are stored in the storer 2, and writes data in the buffer circuit in the control circuit 17.

Particularly, dma circuit 15 provides DMA address DMA_ADR1 by arbiter and selector switch 8 for Memory Controller 9.The address of DMA address DMA_ADR1 instruction memory 2.Dma circuit 15 provides DMA control signal DMA_CONT1 by arbiter and selector switch 8 for Memory Controller 9.The instruction of this DMA control signal DMA_CONT1 indication write store 2 and the instruction of reading from storer 2.The DMA control signal DMA_CONT1 that provides from Memory Controller 9 is provided by arbiter and selector switch 8 dma circuit 15.The state of this DMA control signal DMA_CONT1 instruction memory controller 9.

Dma circuit 15 usefulness DMA address DMA_ADR1 come the address of designated memory 2.At least one item among dma circuit 15 usefulness DMA control signal DMA_CONT1 indicate and write and read.In this way, dma circuit 15 can carry out with the assigned address of writing data into memory 2 and from the assigned address of storer 2 at least one among the reading of data.These data are corresponding to the DMA data DMA_DATA among Fig. 6.

When finishing with writing data into memory 2 with from storer 2 during at least one among the reading of data, dma circuit 15 end of outputs notice DMA_END1 also exports interrupt request INTR1.Imposing a condition of dma circuit 15 also indicates whether to shield interrupt request INTR1.When shielding interrupt request INTR1, under at least one the situation of having finished among writing and reading, dma circuit 15 is not exported interrupt request INTR1.

Provide interrupt request INTR1 to ＂ or ＂ circuit 7.The interrupt request INTR1 to INTR3 that provides from the dma circuit 15 of each inner piecemeal 13 is provided for ＂ or ＂ circuit 7.During in obtaining interrupt request INTR1 to INTR3 any, ＂ or ＂ circuit 7 output interrupt request INTR.Interrupt request INTR is provided for CPU 1.

Selector circuit 16 is exported starting order based on the selection instruction that imposes a condition as the selector circuit 16 of being stored in the register 14.Selector circuit 16 response from CPU1 pass through sign on DMA_TRG1 that register 14 provides and from the end notification DMA_END2 of the dma circuit 15 of second, third inside piecemeal 13b, 13c, any among the DMA_END3, output starting order D_TRG1.

Fig. 7 is the illustrative flow of the DMA associative operation of CPU 1.In Fig. 7, suppose sequential firing dma circuit 15 according to the first dma circuit 15a, the second dma circuit 15b and the 3rd dma circuit 15c.

When input scheduled operation sign on, CPU 1 beginning DMA associative operation, the imposing a condition of control circuit 17 of each inner piecemeal 13 is provided to the register 14 of each inner piecemeal 13, register with the control circuit 17 of each inner piecemeal 13 of execution in step S11 is set, and advances to step S12.

At step S12, provide imposing a condition of the first dma circuit 15a to the register 14 of the first inner piecemeal 13a, set with the register of carrying out the first dma circuit 15a; At step S13, provide imposing a condition of the second dma circuit 15b to the register 14 of the second inner piecemeal 13b, set with the register of carrying out the second dma circuit 15b; At step S14, provide imposing a condition of the 3rd dma circuit 15c to the register 14 of the 3rd inner piecemeal 13c, set with the register of carrying out the 3rd dma circuit 15c.In these steps of S12 to S14, carry out setting to start address, transmission byte number etc.

At step S15, the register 14 of each inner piecemeal 13 obtains the selection instruction that imposes a condition as each selector circuit 16, and program advances to step S16.In Fig. 6, the register 14 of the first inner piecemeal 13a obtains selection instruction, and the sign on from CPU 1 has been selected in indication.The register 14 of the second inner piecemeal 13b obtains selection instruction, and the end notification from the first dma circuit 15a has been selected in indication.The register 14 of the 3rd inner piecemeal 13c obtains selection instruction, and the end notification from the second dma circuit 15b has been selected in indication.Register 14 by inside part piece 13 provides selection instruction, and CPU 1 carries out the coordination setting that is used to coordinate each dma circuit 15.

At step S16, internally the register 14 of part piece 13 is carried out and is set, and to shield unnecessary interrupt request, program advances to step S17.Unnecessary interrupt request is meant, from the interrupt request of all the other dma circuits 15 the dma circuit 15 of the last starting in each dma circuit 15 that should start.In Fig. 6, from the interrupt request conductively-closed of first,

second dma circuit

15a, 15b.

At step S17, the output sign on is to be provided with the start bit of the first dma circuit 15a, and program advances to step S18.At step S18,, that is, during from the interrupt request of the 3rd dma circuit among Fig. 7, stop the DMA associative operation when the interrupt request that obtains providing from dma circuit 15.

As CPU 1 during in step S17 output sign on, first selector circuit 16a response is exported starting order from the sign on of CPU 1.The first dma circuit 15a responds from the starting order of first selector circuit 16a and starts.Response is from the end notification of the first dma circuit 15a, and second selector circuit 16b exports starting order.The second dma circuit 15b responds from the starting order of second selector circuit 16b and starts.Response is from the end notification of the second dma circuit 15b, and third selector circuit 16c exports starting order.The 3rd dma circuit 15c responds from the starting order of third selector circuit 16c and starts.When finishing writing data into memory 2 and among storer 2 reading of data at least one, the 3rd dma circuit 15c exports interrupt request.Provide interrupt request to ＂ or ＂ circuit 7.＂ or ＂ circuit 7 offer CPU 1 with interrupt request.

Obtain from CPU 1 output sign on to CPU 1 interrupt request during, each dma circuit 15 can be with writing data into memory neutralization reading of data from storer, and does not need the intervention of CPU1.During this period, CPU 1 can carry out other processing.

In above-mentioned prior art, each selector circuit 16 not only can respond the sign on from CPU 1, can also respond the end notification from each dma circuit 15, exports starting order.Therefore, if the sign on that provides from CPU 1 is provided any in each selector circuit 16, even when other selector circuit 16 does not obtain from sign on that CPU 1 provides, selector circuit 16 also can be started dma circuit 15 in turn.

In other words, can under the situation of the intervention that does not have CPU 1, coordinate each dma circuit 15.Therefore, because each dma circuit can be as previous routine techniques, when each dma circuit is finished writing data into memory and among memory read data at least one, just provide interrupt request to CPU, with from CPU output sign on, bear the performance degradation that also can prevent CPU so can reduce the processing of CPU.

Yet, if a plurality of processing blocks are carried out a series of processing to identical data, even know that in advance a plurality of processing blocks are at identical address reading of data or the handling procedure that read by above-mentioned another processing block of the prior art by the data that a processing block writes, unless reading or writing of a DMA finished, otherwise next DMA can not begin operation, and this has limited further high speed.

Make a plurality of DMA devices simultaneously on the identical address at storer in the prior art of reading of data a kind of, when detecting a plurality of DMA devices that are connected on different I/O bus when attempting on the same memory address reading of data, data are carried out (Japanese patent application publication No. H11-134287) from the electric bridge that memory bus is sent to a plurality of I/O buses by using.Yet this routine techniques is only just carried out when each DMA device is attempted simultaneously in the identical address reading of data detecting, and is not difficult to enforcement simultaneously in each data processing speed that transmits the destination reading after.

Summary of the invention

The object of the present invention is to provide a kind of data processing equipment, by knowing that in advance a plurality of processing blocks are under the situation of the handling procedure that identical address reading of data or the data that write by a processing block are read by another processing block, even when a plurality of processing blocks have different disposal speed, also make other dma circuit obtain identical data, this data processing equipment can further be accelerated data processing speed and effectively use memory bus.

Another object of the present invention is to provide a kind of data processing equipment, comprising: the permission data write the storer with data read; Main control unit, its output write data into storer and from the sign on of memory read data; A plurality of dma circuits, it is carried out writing data into memory and among the memory read data at least one, with end of output notice when finishing writing data into memory and among memory read data at least one; With a plurality of starting orders unit, its output is used for starting the starting order of each dma circuit, this starting order cell response is from the sign on of main control unit or from the end notification of dma circuit and export starting order, dma circuit responds from the starting order of starting order unit and starts, data processing equipment has arranged side by side group and forms circuit, side by side group forms circuit and is used for based on form in the dma circuit any two or a plurality of dma circuits from the instruction of main control unit arranged side by side group, this side by side group form circuit and make other dma circuit can obtain writing of a dma circuit to handle or read the data of handling in the processing.

Another object of the present invention is to provide a kind of data processing equipment, wherein be configured to main circuit by arranged side by side group of of forming in the dma circuit that circuit forms arranged side by side group, another is configured to controlled circuit, wherein makes the signal wire in the dma circuit that is configured to controlled circuit invalid.

Another object of the present invention is to provide a kind of data processing equipment, wherein form by the starting/end signal in conjunction with dma circuit output and serial coordination DMA group, wherein the interrupt request except that last dma circuit is invalid.

Another object of the present invention is to provide a kind of data processing equipment, wherein another dma circuit provides end notification to a dma circuit at every turn when finishing data processing, unless one of them dma circuit is configured to obtain the end notification that another dma circuit provides, otherwise do not carry out next burst access operation.

Another object of the present invention is to provide a kind of data processing equipment, wherein the predetermined dma circuit in each dma circuit is configured to select to need in the data processing block one of long data processing time.

Another object of the present invention is to provide a kind of data processing equipment, wherein group forms circuit based on the instruction from main control unit side by side, connects the memory data line and the command signal line of a dma circuit and another dma circuit.

Another object of the present invention is to provide a kind of data processing equipment, wherein group formation circuit is arranged in selector switch on each dma circuit side by side, and allows data bus by shared, to make necessary dma circuit effective based on the instruction from main control unit.

Another object of the present invention is to provide a kind of data processing equipment, wherein organize the control signal wire that forms on circuit connection and the corresponding input/output device side of each dma circuit side by side.

Description of drawings

Fig. 1 is the block scheme of the structure of data processing equipment in the routine techniques;

Fig. 2 is the process flow diagram of the DMA associative operation of CPU in the routine techniques;

Fig. 3 is the simplified block diagram of data processing equipment of the prior art of the present invention;

Fig. 4 is with writing data into memory with from the key diagram of an example of memory read data by dma circuit;

Fig. 5 is the integrally-built block scheme of data processing equipment of the prior art of the present invention;

Fig. 6 is the block scheme of the inside partitioned organization of data processing equipment of the prior art of the present invention;

Fig. 7 is the illustrative flow of DMA associative operation of the CPU of data processing equipment of the prior art of the present invention;

Fig. 8 is the simplified block diagram of data processing equipment according to an embodiment of the invention;

Fig. 9 is the integrally-built block scheme of data processing equipment;

Figure 10 shows the structure of the relevant portion of data processing equipment;

Figure 11 is the illustrative flow of the operation of the DMA associative operation of CPU and DMA; With

Figure 12 shows the structure of the relevant portion of data processing equipment according to another embodiment of the present invention.

Embodiment

With reference to accompanying drawing the present invention is described.To repeat no more with part identical in the above-mentioned prior art.

Fig. 8 is the simplified block diagram of data processing equipment according to an embodiment of the invention.Data processing equipment according to the present invention comprises CPU 1, storer 2, a plurality of dma circuit 15 (15a to 15c) and a plurality of selector circuit 16 (16a, 16c).Dma circuit 15 will be known as first to the 3rd dma circuit 15a to 15c sometimes.Selector circuit 16 will be known as first sometimes to third selector circuit 16a to 16c.

The embodiment of Fig. 8 shows two

dma circuit

15a, 15b in three dma circuits is divided into one group example, and show when the time from the first dma circuit 15a and the second dma circuit 15b end of output signal, because the output signal of ＂ and ＂ circuit 18, initiating signal is imported into the 3rd dma circuit 15c from third selector circuit 16c, during processing in finishing the 3rd dma circuit 15c, end signal is imported among the first selector circuit 16a, and the commencing signal of next processing block is imported into the first dma circuit 15a.

Fig. 9 is according to the integrally-built block scheme of the data processing equipment of this embodiment.This data processing equipment comprises CPU 1, storer 2, comprises a plurality of (shown in this example is three) inner piecemeal 13 (13a to 13c) of dma circuit, the Memory Controller 9 of control store 2, and arbiter and selector switch 8, the first inner piecemeal 13a and the second inner piecemeal 13b are divided into one group.

Figure 10 shows the details according to the relevant portion of the data processing equipment of this embodiment.In the example of Figure 10, when with writing data into memory or from storer during reading of data, the first dma circuit 15a and the second dma circuit 15b can carry out parallel processing simultaneously, memory data line and the command signal line of the first dma circuit 15a, via the switch SW of moving according to control signal CPU_CONT 1 from CPU, by connecting line L1, L2, be connected to memory data line and the command signal line of the second dma circuit 15b.

Form arranged side by side group of dma circuit in another way, for example, each DMA can use identical bus, and can be provided with chip and select, so that necessary DMA is effective.That is to say, can be when working independently by making DMA effective and a plurality of to be divided into one group DMA effective by making when the concurrent working seriatim, carry out similar operation.

Figure 11 is the illustrative flow of the operation of the DMA associative operation of CPU 1 and DMA.When input scheduled operation sign on, CPU 1 beginning DMA associative operation, the imposing a condition of control circuit 17 of each inner piecemeal 13 is provided to the register 14 of each inner piecemeal 13, sets with the register of the control circuit 17 of in step S1, carrying out each inner piecemeal 13.

At step S2, provide imposing a condition of the first dma circuit 15a to the register 14 of the first inner piecemeal 13a, set with the register of carrying out the first dma circuit 15a; At step S3, provide imposing a condition of the second dma circuit 15b to the register 14 of the second inner piecemeal 13b, set with the register of carrying out the second dma circuit 15b; At step S4, provide imposing a condition of the 3rd dma circuit 15c to the register 14 of the 3rd inner piecemeal 13c, set with the register of carrying out the 3rd dma circuit 15c.In these steps of S2 to S4, carry out setting to start address, transmission byte number etc.

At step S5, by control signal CPU_CONT Closing Switch SW1 from CPU 1, to connect memory data line and the command signal line of the first dma circuit 15a and the second dma circuit 15b by connecting line L1, L2, and the first dma circuit 15a and the second dma circuit 15b are divided into arranged side by side one group, any dma circuit is set to main circuit, and another dma circuit is set to controlled circuit.At step S5, carry out and set to shield the interrupt request of the second dma circuit 15b.

At step S6, CPU 1 provides selection instruction to the register 14 of each inner piecemeal 13, and selection instruction is represented imposing a condition of each selector circuit 16.In Figure 10, the register 14b of the register 14a of the first inner piecemeal 13a and the second inner piecemeal 13b obtains indicating the selection instruction of having selected from the sign on of CPU 1.

Although not shown in Figure 10, the register 14c of the 3rd inner piecemeal 13c obtains selection instruction, and indication has selected end notification, end notification to be owing to export from ＂ and ＂ circuit 18 from the end signal of the first dma circuit 15a and the second dma circuit 15b.Register 14 by inside part piece 13 provides selection instruction, and CPU 1 carries out and coordinates to set, to coordinate each dma circuit 15.

At step S6, the register 14 of the also internal part piece 13 of CPU 1 is set, to shield unnecessary interrupt request.Unnecessary interrupt request is meant the interrupt request from the dma circuit except the dma circuit of last starting in each dma circuit 15 that should start.In Figure 10, from the interrupt request conductively-closed of first, second dma circuit 15a, 15b.Interrupt request is provided for ＂ or ＂ circuit 7, and ＂ or ＂ circuit 7 offer CPU1 with interrupt request.

At step S6, need in this group to select of long process time if preestablish the first dma circuit 15a, for example, the image data acquisition processing of scanner etc., the first dma circuit 15a can carry out the burst access operation under need not be from the situation of the end notification of the second dma circuit 15b.Just, always be shorter than the processing time of the first dma circuit 15a if guarantee the processing time of the second dma circuit 15b, then the second dma circuit 15b needn't send end notification to the first dma circuit 15a at every turn when finishing data processing.

At step S7, CPU 1 output sign on is to be provided with the start bit of the first dma circuit 15a and the second dma circuit 15b; At step S8, the first dma circuit 15a and the second dma circuit 15b actual figure reportedly send; When finishing the data transmission (step S9), the first dma circuit 15a notifies at step S10 end of output.

At step S11, the 3rd dma circuit 15c starts according to the end notification of the first dma circuit 15a; At step S12, the 3rd dma circuit 15c actual figure reportedly send; When finishing the data transmission (step S13), the 3rd dma circuit 15c notifies at step S14 end of output.

In step S15, CPU 1 obtains from the 3rd dma circuit 15c, that is, the interrupt request that last dma circuit provides, the DMA associative operation is finished.

Figure 12 shows an alternative embodiment of the invention, wherein switch SW 2 be disposed in the corresponding I/O side of dma circuit so that can be connected signal wire.Under the situation of this structure, even a plurality of dma circuit also can shared data when input/output device 10 provides and receives data.

From CPU 1 output sign on up to CPU 1 obtain interrupt request during in, when the first dma circuit 15a with writing data into memory or from storer during reading of data, the second dma circuit 15b can obtain the data that are written to the data in the storer 2 or read by the first dma circuit 15a simultaneously from storer 2, and can write data into other address in the storer 2 or data are sent in the impact damper of control circuit 17b and do not need the intervention of CPU1.

Therefore, can use identical data simultaneously; Reduce read operation to use memory bus effectively; Can reduce the quantity of DMA from the viewpoint of CPU.

According to the present invention, because a plurality of dma circuit is handled identical data, thus can further accelerate data processing speed, and can use memory bus effectively.

From the viewpoint of CPU, can reduce the quantity of dma circuit.

And, can under the situation that does not influence each DMA processing speed and do not have to omit, finish the data processing in the DMA group.

Claims

1. data processing equipment comprises:

The permission data write the storer with data read;

Main control unit, its output write data into described storer and from the sign on of described memory read data;

A plurality of dma circuits, it is carried out data is write described storer and among the described memory read data at least one, to finish end of output notice when data being write described storer and among described memory read data at least one; With

A plurality of starting orders unit, its output is used for starting each starting order of described dma circuit, described starting order cell response is exported described starting order from the described sign on of described main control unit or from the described end notification of described dma circuit, and described dma circuit response is started from the starting order of described starting order unit;

Described data processing equipment has arranged side by side group and forms circuit, described arranged side by side group forms circuit and is used for based on any two or a plurality of dma circuits that form described dma circuit from the instruction of described main control unit arranged side by side group, the permission of described arranged side by side group of formation circuit is handled or is read data processed in the processing writing of a dma circuit and obtained by another dma circuit, wherein form and serial coordination DMA group, and the interrupt request except that the interrupt request of last dma circuit was lost efficacy by described starting order in conjunction with the output of described starting order unit.

2. data processing equipment as claimed in claim 1, wherein, by described arranged side by side group form that circuit forms and the described dma circuit of joint group in one be configured to main circuit, another is configured to controlled circuit, and wherein makes the signal wire in the dma circuit that is configured to controlled circuit invalid.

3. data processing equipment as claimed in claim 2, wherein, described another dma circuit provides end notification to a dma circuit at every turn when finishing data processing, wherein, a dma circuit is configured to, unless described another dma circuit provides end notification, otherwise do not carry out next burst access operation.

4. data processing equipment as claimed in claim 2, wherein, the predetermined dma circuit in the described dma circuit is configured to select to need in the data processing block one of long data processing time.

5. data processing equipment as claimed in claim 1 or 2, wherein, described arranged side by side group forms circuit based on the instruction from described main control unit, connects the memory data line and the command signal line of a dma circuit and another dma circuit.

6. data processing equipment as claimed in claim 1 or 2, wherein, described arranged side by side group of formation circuit is arranged in selector switch on the described dma circuit, and allows data bus shared so that make necessary dma circuit effective based on the instruction from described main control unit.

7. data processing equipment as claimed in claim 1, wherein, described arranged side by side group of control signal wire that forms on circuit connection and the corresponding input/output device side of described dma circuit.