JP7060471B2 - Mutual injection phase-locked loop - Google Patents

Description

The present invention relates to a mutual injection phase-locked loop having two phase-locked circuits and injecting each other.

Conventionally, an injection lock that applies a perturbation very close to the oscillation frequency to an oscillator and synchronizes it with the applied signal has been known, and there is a study by Adler et al. In the 1970s in an integrated circuit (see Non-Patent Document 1). Further, a self-injection method using this phenomenon for improving the performance of a single oscillator is also known (see Non-Patent Document 2). The inventor of the present invention has also filed a patent application for an application of the method to a phase-locked loop (PLL) (see Patent Document 1).

On the other hand, the phenomenon of destabilization due to the interference of multiple oscillators with each other has been observed for some time, and as a solution to this phenomenon, an example of widening the PLL band to suppress mutual interference has been reported (). See Non-Patent Document 3).

In addition, as a related technique, it has been reported that a method of changing the operation timing is effective as a countermeasure against interference noise (self-interference) due to wraparound of the self-signal of a circuit having a single oscillator (Non-Patent Document). 4).

Japanese Unexamined Patent Publication No. 2017-055295

R. Adler, "A Study of Locking Phenomena in Oscillators," Proc. IEEE, vol.61, pp. 1380-1385, Oct. 1973 C-H Chang, "Phase noise in self-injection-locked oscillators --Theory and experiment," IEEE Trans. Microwave Theory Tech., Vol. 51, pp. 1994-1999, Sept. 2003 T. Shibasaki, et al., "4 × 25.78 Gb / s Retimer ICs for Optical Links in 0.13 μm SiGe BiCMOS," ISSCC dig. Tech. Papers, pp. 412-414, Feb. 2015 O. E. Eliezer, et al., "A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers," IEEE J.S.S.C, vol. 44, no. 5, pp. 1436-1453, May 2009

A method of suppressing unstable operation due to mutual interference of oscillators by widening the band of the PLL as in the conventional example is effective, but it cannot be made into an infinitely wide band, so that there is a limit. Further, there is a problem that the method cannot be applied when the PLL band is determined by the specifications of the circuit or the like. Further, a method of suppressing the influence of noise by changing the operation timing of a circuit cannot be generally adopted because it affects the operation timing of other related circuits.

The present invention has been made to solve the above problems, and can reduce the influence of mutual interference of oscillators without widening the PLL band or affecting the operation timing of the circuit. The purpose is to provide a circuit that can be used.

In order to achieve the above object, the mutual injection phase-locked loop according to the present invention has a voltage control oscillator that outputs a signal having an oscillation frequency corresponding to a control voltage, and has a first oscillation output signal whose phase is synchronized with the first reference signal. It has a first phase-locked loop circuit that outputs, and a voltage control oscillator that outputs a signal with an oscillation frequency corresponding to the control voltage, and a second phase-locked loop that outputs a second oscillation output signal whose phase is synchronized with the second reference signal. The circuit, the first delay means for outputting the first injection signal obtained by delaying the first oscillation output signal so as to be negative feedback to the voltage control oscillator of the second phase-locked loop, and the second oscillation output signal. , A second delay means for outputting a second injection signal delayed so as to be negative feedback to the voltage control oscillator of the first phase-locked loop, and the first injection signal is the second phase-locked loop. The second injection signal is injected into the voltage control oscillator, and the second injection signal is injected into the voltage control oscillator of the first phase-locked loop.
With such a configuration, it is possible to perform mutual injection in which the oscillation output signal of one phase-locked loop is mutually injected into the other phase-locked loop, and the influence of mutual interference between the two phase-locked loops is reduced. And each oscillation output signal can be made more stable. Further, it is possible to reduce the influence of such mutual interference without widening the bandwidth of the PLL or affecting the operation timing of the circuit.

Further, in the mutual injection phase-locked loop according to the present invention, the first and second oscillation output signals have the same frequency, and the first and second delay means are variable delayers whose delay time can be changed, respectively, and the second phase. The first injection signal injected into the voltage control oscillator of the synchronous circuit is injected into the first delay controller that controls the delay time of the first delay means so that the first injection signal becomes negative feedback, and the voltage control oscillator of the first phase-locked loop. A second delay controller that controls the delay time of the second delay means so that the second injection signal becomes negative feedback may be further provided.
With such a configuration, when the first and second oscillation output signals have the same frequency, the delay time in the first and second delay means is controlled so that each injection signal is injected with negative feedback. It can be controlled automatically.

Further, in the mutual injection phase synchronization circuit according to the present invention, the first delay controller delays at least one of the first injection signal and the second oscillation output signal by a predetermined time, and then the phase of both signals. Controls the delay time of the first delay means so that the signals are synchronized with each other, and the second delay controller delays at least one of the second injection signal and the first oscillation output signal by a predetermined time. The delay time of the second delay means may be controlled so that the phases of both signals are synchronized.
With such a configuration, the delay time in the first and second delay means can be controlled so that each injection signal is injected with negative feedback.

Further, in the mutual injection phase-locked loop according to the present invention, the first and second oscillation output signals have different frequencies, and the first and second delay means have arbitrary positions with respect to the first and second oscillation output signals, respectively. The first delay means for generating the first and second injection signals having a phase difference and controlling the first delay means so as to generate the first injection signal having a predetermined phase difference with respect to the second oscillation output signal. A delay controller and a second delay controller that controls the second delay means so as to generate a second injection signal having a predetermined phase difference with respect to the first oscillation output signal may be further provided.
With such a configuration, when the first and second oscillation output signals have different frequencies, each injection signal is injected with negative feedback by controlling the injection signals generated by the first and second delay means. Can be controlled automatically.

According to the mutual injection phase-locked loop according to the present invention, the influence of mutual interference can be reduced by injecting the outputs of the two phase-locked loops into the other phase-locked loops.

A block diagram showing a configuration of a mutual injection phase-locked loop according to an embodiment of the present invention. A block diagram showing a configuration of a delay controller according to the same embodiment. A block diagram showing another example of the delay means and the delay controller in the same embodiment. A block diagram showing another configuration of the mutual injection phase-locked loop according to the same embodiment. A block diagram showing another configuration of the mutual injection phase-locked loop according to the same embodiment. A graph showing the relationship between the operation timing difference between the two PLLs and the jitter value of the oscillation output signal. Micrograph of circuit chip containing two PLLs

Hereinafter, the mutual injection phase-locked loop according to the present invention will be described with reference to embodiments. In the following embodiments, the components with the same reference numerals are the same or correspond to each other, and the description thereof may be omitted again. The mutual injection phase-locked loop according to the present embodiment has two phase-locked circuits, and performs mutual injection in which the output of each is injected into another phase-locked loop.

FIG. 1 is a block diagram showing a configuration of a mutual injection phase-locked loop 1 according to the present embodiment. The mutual injection phase-locked loop 1 according to the present embodiment includes a first phase-locked loop (PLL) 11, a second phase-locked loop 12, a first delay means 13, a second delay means 14, and a first delay control. A device 15 and a second delay controller 16 are provided. It is assumed that the first and second phase-locked loops 11 and 12 are arranged close to each other so as to affect each other's mutual interference.

The first phase-locked loop 11 outputs a first oscillation output signal whose phase is synchronized with the first reference signal, and is a phase frequency comparator (PFD: Phase Frequency Detector) 21 and a charge pump (CP: Charge Pump). ) 22, a loop filter (LPF) 23, a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) 24, and a frequency divider 25. The first phase-locked loop 11 does not have to include the frequency divider 25.

The phase frequency comparator 21 compares the phase and frequency of the first oscillation output signal and the first reference signal, and outputs a comparison result signal indicating the result of the comparison. The first reference signal is a signal (reference signal) to be synchronized with the first oscillation output signal in the first phase-locked loop 11, and is, for example, a stable low-phase noise signal oscillated by a crystal oscillator or the like. It is preferable to have. Since the first phase-locked loop 11 has the frequency divider 25, the first oscillation output signal to be compared with the first reference signal is the first oscillation output signal divided by the frequency divider 25. The configuration of the phase frequency comparator 21 is not particularly limited, but may be, for example, one that outputs a comparison result signal indicating the difference between the rising edge of the oscillation output signal and the reference signal.

The charge pump 22 converts the comparison result signal output from the phase frequency comparator 21 into a current or a voltage and outputs it to the loop filter 23. That is, the charge pump 22 may be a current charge type or a voltage charge type. The charge pump 22 converts the comparison result of both signals detected by the phase frequency comparator 21 into a current pulse or a voltage pulse.

The loop filter 23 generates a control voltage according to the current or voltage converted by the charge pump 22 and outputs the control voltage to the voltage controlled oscillator 24. The loop filter 23 is a low-pass filter that smoothes and outputs the output from the charge pump 22.

The voltage controlled oscillator 24 outputs a first oscillation output signal having an oscillation frequency corresponding to the control voltage from the loop filter 23. The type of the voltage controlled oscillator 24 is not limited, but may be, for example, an LC tank oscillator, a ring type oscillator, or another type of voltage controlled oscillator. Further, a second injection signal for mutual injection is injected into the voltage controlled oscillator 24. The method of injecting the second injection signal into the voltage controlled oscillator 24 does not matter. Examples of the method of injecting the second injection signal into the voltage controlled oscillator 24 include a method of directly injecting the current of the injection signal into the voltage controlled oscillator 24 (direct current injection) and a method of injecting the pulse of the injection signal into the voltage controlled oscillator 24. There is a method of injection (capacitive coupling injection) and the like. For specific examples of the injection method, refer to the following documents, for example. Further, the voltage controlled oscillator 24 may have a circuit for injecting the second injection signal, for example, a circuit for capacitive coupling injection and the like.
References: S. Morishita, S. Shimizu, T. Kihara, T. Yoshimura, "Subharmonically Injection-Locked PLL with Variable Pulse-Width Injections," ISCAS 2015, pp. 557-560, May 2015

The frequency divider 25 divides the first oscillation output signal output from the voltage controlled oscillator 24 by a predetermined frequency division ratio n, and outputs the divided oscillation output signal to the phase frequency comparator 21. The frequency divider 25 sets the frequency of the first oscillation output signal to 1 / n. Note that n is a positive integer. The frequency divider 25 may or may not have a variable frequency division ratio n.

In this embodiment, the configuration (hereinafter referred to as “voltage generator”) is such that a control voltage is generated according to the comparison result signal output from the phase frequency comparator 21 and output to the voltage controlled oscillator 24. The case of having the charge pump 22 and the loop filter 23 will be described, but it is not necessary. The voltage generator may have any configuration as long as it outputs a control voltage corresponding to the comparison result signal to the voltage controlled oscillator 24. When the PLL is configured on an integrated circuit, the voltage generator usually has a charge pump 22 and a loop filter 23, but when the PLL is configured discretely, it has a charge pump 22. As a voltage generator other than having the loop filter 23, a circuit that operates as an integrator (active filter) using an operational amplifier and sample-holds a voltage corresponding to a comparison result signal can also be used. When the circuit including the PLL is configured on the integrated circuit, it is preferable that the voltage generator is a charge pump type from the viewpoint of noise reduction.

Further, the configurations of the phase frequency comparator 21 and the charge pump 22 of the first phase-locked loop 11 shown in FIG. 1 are described as such for convenience, and any two or more configurations are integrally configured. May be. For example, the phase frequency comparator 21 and the charge pump 22 may be integrally configured, or the charge pump 22 and the loop filter 23 may be integrally configured.

The second phase-locked loop 12 outputs a second oscillation output signal whose phase is synchronized with the second reference signal, and is a phase frequency comparator 31, a charge pump 32, a loop filter 33, and a voltage controlled oscillator 34. And a frequency divider 35. The second reference signal is a signal different from the first reference signal. The second phase-locked loop 12 does not have to include the frequency divider 35. Further, each configuration of the second phase-locked loop 12 is the same as each corresponding configuration in the first phase-locked loop 11, and detailed description thereof will be omitted.

In this embodiment, the case where the frequencies of the first and second oscillation output signals are the same will be mainly described, and the case where the frequencies of the first and second oscillation output signals are different will be described later. When the frequencies of the first and second oscillation output signals are the same, the first and second reference signals are usually the same frequency, and the frequency division ratios of the dividers 25 and 35 are the same, respectively. However, it does not have to be. For example, even if the frequencies of the first and second reference signals are different and the division ratios of the dividers 25 and 35 are different, as a result, the first and second oscillation output signals are different. This is because the frequencies may be the same. The use of the mutual injection phase-locked loop 1 in which the frequencies of the two PLLs are the same is not particularly limited, but for example, the first and second phase-locked loops 11 and 12 have two delay differences. It may be used to perform clock recovery on the data respectively, or it may be used for other purposes.

The first delay means 13 uses a first injection signal in which the first oscillation output signal output from the voltage controlled oscillator 24 is delayed so as to be negative feedback to the voltage controlled oscillator 34 of the second phase-locked loop circuit 12. Output. The first injection signal is injected into the voltage controlled oscillator 34 of the second phase-locked loop 12. In the present embodiment, the case where the first delay means 13 is a variable delay device capable of changing the delay time will be mainly described, but as will be described later, the first delay means 13 has a fixed delay time. It may be a delayer, or may have a different configuration when the frequencies of the first and second oscillation output signals are different. When the first delay means 13 is a variable delay device, the first delay means 13 may delay the input signal by a delay time corresponding to the control voltage, for example.

The first delay controller 15 controls the delay time of the first delay means 13 so that the first injection signal injected into the voltage controlled oscillator 34 of the second phase-locked loop 12 becomes negative feedback. By changing the delay time of the first delay means 13, the phase of the signal output from the first delay means 13 is changed as a result. Therefore, the first delay controller 15 controls the phase of the first injection signal. When the first injection signal injected into the voltage controlled oscillator 34 is delayed by a phase larger than π / 2 and smaller than 3π / 2 with respect to the second oscillation output signal, negative feedback injection is performed. Therefore, it is preferable that the first delay controller 15 controls the delay time so as to be within the range. When the first injection signal injected into the voltage controlled oscillator 34 is out of phase with the second oscillation output signal by π (180 °), the injection is performed with the optimum negative feedback. Therefore, the first delay controller 15 may control the first delay means 13 so that the phase of the first injection signal is delayed by π with respect to the second oscillation output signal. Further, the first delay controller 15 controls the first delay means 13 based on the first injection signal and the second oscillation output signal. The specific control method will be described later with reference to FIG.

The first delay means 13 and the first delay controller 15 may or may not be configured in the same manner as a so-called DLL (Delay-Locked Loop). In the present embodiment, a case where the first delay means 13 and the first delay controller 15 are configured in the same manner as the DLL will be mainly described.

FIG. 2 is a block diagram showing a configuration of the first delay controller 15 according to the present embodiment. In FIG. 2, the first delay controller 15 controls the delay time of the first delay means 13 so that the phases of the first injection signal and the second oscillation output signal after being delayed by a predetermined time are synchronized. It includes a delay device 41, a phase comparator (PD) 42, a charge pump (CP) 43, and a loop filter (LPF) 44.

The delay device 41 delays the first injection signal by a predetermined time and outputs the first injection signal to the phase comparator 42. It is assumed that the delay device 41 is set so that the first injection signal is delayed by a time corresponding to the phase larger than π / 2 and smaller than 3π / 2. Since the frequencies of the first and second oscillation output signals are the same, the phase may be considered as the phase of the first injection signal or the phase of the second oscillation output signal. When the phase of the first injection signal is delayed by θ with respect to the second oscillation output signal, the delay device 41 may be set so that the phase is delayed by 2π−θ. If the first injection signal is delayed by a time corresponding to the phase π, the delay device 41 may be a NOT circuit. The NOT circuit inverts the first injection signal. This inversion shifts the phase of the signal by π. By the phase shift, the phase difference between the first injection signal and the second oscillation output signal is controlled to be π, and the optimum injection to the voltage controlled oscillator 34 can be realized.

The phase comparator 42 compares the phase of the first injection signal output from the first delay means 13 and delayed by the delay device 41 with the second oscillation output signal output from the second phase synchronization circuit 12. A signal indicating the result of the comparison is output. The phase comparator 42 may be a phase frequency comparator, but since it is sufficient here that the phases of both signals can be compared, the frequency comparison may not be performed. Further, the phase comparator 42 may be a phase detector such as a mixer, for example.

The charge pump 43 converts the signal output from the phase comparator 42 into a current or a voltage and outputs the signal to the loop filter 44. That is, the charge pump 43 may be a current charge type or a voltage charge type. The charge pump 43 converts the comparison result of both signals detected by the phase comparator 42 into a current pulse or a voltage pulse.

The loop filter 44 generates a signal for controlling the first delay means 13 according to the signal output from the charge pump 43, and outputs the signal to the first delay means 13. The signal output by the loop filter 44 may be the control voltage of the first delay means 13.

The DLL is configured by the configuration of the first delay means 13 and the first delay controller 15 shown in FIG. 2 other than the delay device 41. Further, due to the presence of the delay device 41, unlike a normal DLL, a predetermined phase difference is generated between the second oscillation output signal and the first injection signal. Further, in the first delay controller 15 shown in FIG. 2, the charge pump 43 may not exist between the phase comparator 42 and the loop filter 44. Further, although FIG. 2 shows a configuration in which the first injection signal is delayed by the delay device 41, the second oscillation output signal may be delayed, and both the first injection signal and the second oscillation output signal may be delayed. It may be delayed. Therefore, the first delay controller 15 is the first delay means so that the phases of the first injection signal and the second oscillation output signal, after delaying at least one of the signals by a predetermined time, are synchronized with each other. It may control the delay time of 13. In any case, the first injection signal is delayed by a time corresponding to the phase larger than π / 2 and smaller than 3π / 2, so that the first injection signal is negatively fed back. It is preferred that it be controlled to be injected.

The second delay means 14 outputs a second injection signal in which the second oscillation output signal is delayed so as to be negative feedback to the voltage controlled oscillator 24 of the first phase-locked loop 11. The second injection signal is injected into the voltage controlled oscillator 24 of the first phase-locked loop 11.

The second delay controller 16 controls the delay time of the second delay means 14 so that the second injection signal injected into the voltage controlled oscillator 24 of the first phase-locked loop 11 becomes negative feedback. The second delay controller 16 is a second delay means 14 so that the phases of both signals after delaying at least one of the second injection signal and the first oscillation output signal by a predetermined time are synchronized. The delay time may be controlled.

In the second delay means 14 and the second delay controller 16, the first injection signal, the first oscillation output signal, and the second oscillation output signal are the second injection signal, the second oscillation output signal, and the first oscillation output signal. Other than the above, they are the same as those of the first delay means 13 and the first delay controller 15, respectively, and detailed description thereof will be omitted. When the frequencies of the first and second oscillation output signals are the same, the degree of delay in the delay device 41 of the first delay controller 15 and the delay in the delay device of the second delay controller 16. The degree is usually the same, but the two may be different. This is because the first and second injection signals need only be output with a delay amount within the range of negative feedback.

Next, the operation of the mutual injection phase-locked loop 1 will be briefly described. When the processing in the mutual injection phase-locked loop 1 is started, the first and second oscillation output signals output in the first and second phase-locked loops 11 and 12 are locked to the first and second reference signals, respectively. Is controlled.

Further, the first oscillation output signal output from the first phase-locked loop 11 is delayed by the first delay means 13 and injected into the voltage controlled oscillator 34 of the second phase-locked loop 12. Further, the second oscillation output signal output from the second phase-locked loop 12 is delayed by the second delay means 14 and injected into the voltage controlled oscillator 24 of the first phase-locked loop 11. In those injections, the delay times in the first and second delay means 13 and 14 are the first and second so that the injection that becomes negative feedback is performed with respect to the oscillation output signal of the voltage controlled oscillator of the injection destination. It is controlled by the delay controllers 15 and 16. As a result, unstable operation and an increase in phase noise due to mutual interference of the oscillators can be suppressed.

FIG. 6 is a graph showing the relationship between the operation timing difference (ps) of the two PLLs and the jitter value (ps) of the oscillation output signal. FIG. 6 shows a graph when the optimum mutual injection is performed in the mutual injection phase-locked loop 1 according to the present embodiment, and a graph when the mutual injection is performed at a timing deviated from the optimum mutual injection by about 90 (ps). , The graph when no injection is performed, and the graph when self-injection is performed are shown. In the optimum mutual injection, the application timing (phase difference) of the injection signal was adjusted so that the jitter value was the smallest. In the optimum mutual injection, the injection signal was delayed by about π (180 °) with respect to the oscillation output signal of the PLL at the injection destination. Therefore, even in the mutual injection performed at the timing deviated from the optimum mutual injection by about 90 (ps), the mutual injection with negative feedback is performed. This is because, as will be described later, 400 (ps) corresponds to one cycle, so 90 (ps) corresponds to 81 °. In addition, self-injection was performed for each of the two PLLs, and the delay amount in self-injection was set so as to have the best characteristics (smaller jitter value).

In the experiment of FIG. 6, the mutual injection phase-locked loop 1 was actually configured and the experiment was performed. FIG. 7 is a photomicrograph of a circuit chip including the two phase-locked loops 11 and 12 used in this experiment. The size of one PLL was about 400 (μm) × about 510 (μm), and a voltage controlled oscillator using an LC resonator was used in each PLL. In each PLL, two inductors were used as the voltage controlled oscillator. The size of one inductor is about 180 (μm) × about 180 (μm). The distance between the two PLLs was the smallest, about 30 (μm). The operating frequency of the PLL was 2.5 GHz, the first and second reference signals were 39.06025 MHz, and the frequency division ratio was 64. Further, by changing only the second reference signal, a difference was generated in the operation timings of the two PLLs, and the influence of mutual interference was measured. When the injection is not performed, the operation timing difference between the two PLLs is around 200 (ps), and the operation is good (that is, the operation with a small jitter value), but the operation timing difference between the two PLLs is about 150. When it was less than (ps) or exceeded about 250 (ps), the jitter value became so large that it became impossible to measure. Since one cycle corresponding to the operating frequency of 2.5 GHz is 400 (ps), if the operating timing difference between the two PLLs is about 200 (ps), which corresponds to a half cycle, the influence of mutual interference is ideal. The result is similar to that of negative feedback, and it is considered that the jitter value is small. On the other hand, when mutual injection was performed, it was possible to suppress the jitter value from becoming large in all the operation timing differences between the two PLLs, and it was confirmed that mutual injection is effective in suppressing mutual interference. We were able to.

In addition, even in the case of mutual injection in which the phase of the injection signal is out of phase by about 90 (ps) from the optimum mutual injection, the jitter value as a whole is slightly larger than that of the optimum mutual injection, but the influence of mutual interference is effectively suppressed. You can see that it is done. Therefore, it was confirmed that mutual interference can be suppressed by injecting the injection signal so as to have negative feedback to the PLL of the injection destination.

In addition, when self-injection was performed, the jitter value was reduced as compared with the case where no injection was performed, but there was still a timing region in which the jitter value became unmeasurable. Theoretically, the injection signal is the same regardless of whether self-injection is performed or mutual injection is performed. Therefore, it is considered that mutual interference can be suppressed by self-injection. In this experiment, it was confirmed that mutual interference cannot be properly suppressed by self-injection. Therefore, it can be seen that performing mutual injection is effective in suppressing mutual interference.

Next, a case where the frequencies of the first and second oscillation output signals are different will be described. When the frequencies of the first and second oscillation output signals are different, the first and second reference signals are usually different frequencies, but they do not have to be. The frequencies of the first and second reference signals are the same, but the frequencies of the first and second oscillation output signals may be different due to the difference in the division ratio. When the frequencies of the first and second oscillation output signals are different, the first delay means 13 generates the first injection signal having an arbitrary phase difference with respect to the first oscillation output signal, not the variable delayer. It becomes a thing. Further, the first delay controller 15 controls the delay time (phase difference) in the first delay means 13 so that the first injection signal injected into the voltage controlled oscillator 34 becomes negative feedback, and the second delay controller 15. The first delay means 13 is controlled so that the first injection signal having a predetermined phase difference with respect to the oscillation output signal is generated. The first delay controller 15 controls the control based on the first injection signal and the second oscillation output signal. When the frequencies of the first and second oscillation output signals are different, the first delay means 13 and the first delay controller 15 may have the configuration shown in FIG. 3, for example.

In FIG. 3, the first delay means 13 includes a polyphase clock generator 51 and a phase selection interpolation means 52. Further, the first delay controller 15 includes a phase comparator (PD) 53 and a controller 54. The multi-phase clock generator 51 outputs a multi-phase clock in which the first oscillation output signal is sequentially phase-shifted by a predetermined phase interval (for example, π / 6). The polyphase clock may be limited to the phase up to π. The phase selection interpolation means 52 selects two clocks from the polyphase clock generated by the polyphase clock generator 51 and the clock obtained by shifting the phase of the polyphase clock by π, and the two selected clocks are selected. By interpolating the clock, it is possible to generate a first injection signal having an arbitrary phase difference (0 to 2π) with respect to the first oscillation output signal. Note that the arbitrary phase difference does not mean a fixed phase difference, but means various phase differences in the range of 0 to 2π, and is the minimum of the phase difference depending on the phase interval of the polyphase clock and the degree of interpolation. The unit of will be decided. Strictly speaking, since the phase difference is the phase difference with respect to the first oscillation output signal, the phase difference may not be in the range of 0 to 2π with respect to the second oscillation output signal. Specifically, when the period T2 of the second oscillation output signal is longer than the period T1 of the first oscillation output signal, the first delay means 13 refers to the second oscillation output with respect to the second oscillation output signal. It is not possible to output the first injection signal delayed by the phase in the range of 2π (T2-T1) / T2 to 2π of the signal. However, as will be described later, when the upper limit of the delay for the second oscillation output signal is 3π / 2 and the frequencies of the first and second oscillation output signals are significantly different, the influence of mutual interference is small in the first place. Considering this, even if the period T2 of the second oscillation output signal is longer than the period T1 of the first oscillation output signal, it usually does not matter. Therefore, even in the first delay means 13 shown in FIG. 3, the first oscillation output signal is usually delayed so as to be negative feedback to the voltage controlled oscillator 34 of the second phase-locked loop. The injection signal can be output.

The phase of the first injection signal output from the phase selection interpolation means 52 and the second oscillation output signal are compared by the phase comparator 53. Then, based on the comparison result, the controller 54 has only a phase larger than π / 2 and smaller than 3π / 2 with respect to the second oscillation output signal (this phase is the phase of the second oscillation output signal). The phase selection and signal interpolation in the phase selection interpolation means 52 are controlled so that the delayed first injection signal is output from the first delay means 13. More specifically, the controller 54 outputs a first injection signal delayed by a predetermined phase with respect to the second oscillation output signal from the first delay means 13 based on the comparison result by the phase comparator 53. It may be controlled so as to be. As described above, the predetermined phase is a phase in a range larger than π / 2 and smaller than 3π / 2. Here, since the frequencies of the first and second oscillation output signals are different, the first injection signal delayed by a predetermined phase with respect to the second oscillation output signal is, for example, the rising edge of the second oscillation output signal. It may mean the first injection signal whose rising timing is delayed by a predetermined phase with respect to the timing. Further, when the first injection signal is a signal delayed by a certain phase with respect to the second oscillation output signal, the frequencies of both signals are different, so that the phase of the first injection signal changes every cycle. Will be done. In this way, even when the frequencies of the first and second oscillation output signals are different, the first injection signal is negatively fed back to the second oscillation output signal of the second phase-locked loop circuit 12. It will be injected into the voltage controlled oscillator 34. As a circuit having the first delay means 13 and the first delay controller 15 shown in FIG. 3, the Dual Delay-Locked Loop described in the following document is known. Therefore, please refer to the document for the details of each configuration shown in FIG. The polyphase clock generator 51 corresponds to the core DLL of the following document, and the phase selection interpolation means 52 corresponds to the phase selection, selective phase inversion, phase interpolation in the peripheral DLL of the following document, and the phase comparator 53 and the controller. 54 corresponds to the phase detector and FSM in the peripheral DLL of the following documents, respectively.
References: S. Sidiropoulos, M. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997

When the frequencies of the first and second oscillation output signals are different, the second delay controller 15 is not a variable delayer, but a second injection signal having an arbitrary phase difference with respect to the second oscillation output signal. The second delay controller 16 controls the second delay means 14 so as to generate a second injection signal having a predetermined phase difference with respect to the first oscillation output signal. Become. Further, the second delay means 14 and the second delay controller 16 have the same configurations as the first delay means 13 and the first delay controller 15 except that the input signal and the output signal are different. Omit.

Further, in the mutual injection phase-locked loop 1 according to the present embodiment, the oscillation output signals input to the first and second delay means 13 and 14 may be divided. FIG. 4 is a block diagram showing an example of the configuration of such a mutual injection phase-locked loop 1. In FIG. 4, the first phase-locked loop 11 further includes a frequency divider 26, and the second phase-locked loop 12 further includes a frequency divider 36. When the frequencies of the first and second oscillation output signals are the same, the frequency division ratios of the frequency dividers 26 and 36 are usually the same, but they may be different.

The frequency divider 26 divides the first oscillation output signal output from the voltage controlled oscillator 24 by a predetermined division ratio m, and divides the first oscillation output signal after division into the frequency divider 25 and the first delay. It is output to the means 13. In this case, since the frequency is divided by the frequency divider 26 and the frequency divider 25, the frequency of the first oscillation output signal becomes 1 / (n × m) and is input to the phase frequency comparator 21. become. Note that m is a positive integer. It is preferable that m is not a large value. For example, when injection is performed according to the injection signal obtained by delaying the first oscillation output signal divided by the frequency divider 26, the voltage controlled oscillator 34 is compared with the case where the frequency divider 26 does not exist. The frequency of the injected pulse is 1 / m. If the frequency is too low, it will be difficult to synchronize with the injection signal. m is preferably 8 or less, and more preferably 4 or less. By providing the frequency divider 26, the frequency of the first injection signal can be determined independently of the first oscillation output signal. When the first injection signal corresponding to the first oscillation output signal divided by the frequency divider 26 is injected into the voltage controlled oscillator 34, the injection of the first injection signal is the second oscillation output signal. Instead of being performed every cycle, it will be performed in a discrete manner (subharmonically injection). Therefore, in that case, it is preferable that the injection to the voltage controlled oscillator 34 is performed by a method of injecting a pulse of the injection signal (capacitive coupling injection). The frequency divider 26 may or may not be capable of changing the frequency division ratio m. Further, the frequency divider 36 is the same as that of the frequency divider 26, and detailed description thereof will be omitted.

When the period of the injection signal input to the first and second delay controllers 15 and 16 and the oscillation output signal are different due to the presence of the frequency dividers 26 and 36, the injection signal The pulse width may be modified by a pulse generator (not shown) to be half an integral length of the period of the oscillation output signal before being injected into the voltage controlled oscillator. For example, the pulse width after the change of the injection signal may match the pulse width of the oscillation output signal. Here, the pulse width of the signal is the time length from the rising point to the falling point of the pulse included in the signal. Even when the pulse width is changed, it is preferable that the timing of the rising edge of the pulse is not changed. When the injection signal with the changed pulse width is input to the first and second delay controllers 15 and 16, the signal is inverted by the NOT circuit in the first and second delay controllers 15 and 16. When delaying by inverting, it is preferable to delay by inverting the oscillation output signal. Further, when the pulse width is changed, the duty ratio (ratio of H and L) of the injection signals input to the first and second delay controllers 15 and 16 does not become 50%, so that the phase comparator is used. It is preferable that 42 is not a mixer type. Further, in order to prevent the cycles of the injection signal and the oscillation output signal input to the first and second delay controllers 15 and 16 from being different, the oscillation output signal after division by the frequency dividers 36 and 26 is set. It may be input to the first and second delay controllers 15, 16.

As described above, according to the mutual injection phase-locked loop 1 according to the present embodiment, the influence of mutual interference can be reduced by performing mutual injection, and as a result, unstable operation due to mutual interference is suppressed. It can also reduce noise. Further, it is possible to reduce the influence of such mutual interference without widening the loop band of the PLL or affecting the operation timing of the circuit. When the frequencies of the first and second oscillation output signals are the same, the first and second delay means 13 and 14 are used as variable delayers, and the injections are made by the first and second delay controllers 15 and 16. By adjusting the timing of each signal, it can be automatically adjusted so that mutual injection that becomes negative feedback is performed in each of the voltage controlled oscillators 24 and 34. Further, when the frequencies of the first and second oscillation output signals are different, the injection signals having arbitrary phase differences are generated by the first and second delay means 13 and 14, respectively, and the first and second delay means are generated. The second delay controllers 15 and 16 control the first and second delay means 13 and 14 so as to generate an injection signal having a predetermined phase difference with respect to the oscillation output signal of the injection destination. Even in situations where the frequencies are different, the voltage controlled oscillators 24 and 34 can be automatically adjusted so that mutual injection that provides negative feedback is performed.

In the present embodiment, it has been described that the first and second delay means 13 and 14 are variable delayers when the frequencies of the first and second oscillation output signals are the same, but this is not the case. May be good. For example, when the phase difference between the first and second reference signals is fixed, the delay times of the first and second delay means 13 and 14 may be fixed. Even in that case, the first and second injection signals are output from the first and second delay means 13 and 14 so as to be negative feedback to the second and first oscillation output signals of the injection destination, respectively. It shall be. That is, it is necessary to determine the fixed delay amount in the first and second delay means 13 and 14 so as to be so. Further, when the first and second delay means 13 and 14 having such a fixed delay time are used, the mutual injection phase-locked loop 1 has the first and second delay controllers 15 and 16. It does not have to be. This is because it is not necessary to control the first and second delay means 13 and 14.

Even if the frequencies of the first and second oscillation output signals are different, when the frequency of one of the first and second oscillation output signals is an integral multiple of the other frequency, the first and second oscillation output signals are used. Mutual injection may be performed depending on the configuration when the frequencies of the oscillation output signals are the same. Even in that case, the timing (delay time) is adjusted so that the injection signal has negative feedback with respect to the PLL of the injection destination. Therefore, for the injection signal having a frequency higher than that of the PLL of the injection destination, it is necessary to divide the frequency so that the frequency is the same as or lower than that of the PLL of the injection destination before injecting. This is to prevent the frequency of the injection signal from becoming higher than the frequency of the PLL of the injection destination, resulting in non-negative feedback injection. More specifically, when the frequency of the first oscillation output signal is higher than the frequency of the second oscillation output signal, the mutual injection phase-locked loop 1 has a frequency divider in the front stage or the rear stage of the first delay means 13. You may be prepared. Further, when the frequency of the second oscillation output signal is higher than the frequency of the first oscillation output signal, the mutual injection phase-locked loop 1 may be provided with a frequency divider in the front stage or the rear stage of the second delay means 14. good. Further, even when the frequency of the injection signal is lower than the frequency of the PLL of the injection destination, it is preferable that the frequency of the injection signal is 1/8 or more of the frequency of the PLL of the injection destination. It is more preferable that the frequency is 1/4 or more. This is to enable proper synchronization with the injection signal in the injection destination PLL. Further, when the injection signal is adjusted so as to have negative feedback with respect to the PLL of the injection destination, the injection signal is larger than π / 2 and 3π / 2 with respect to the oscillation output signal of the PLL of the injection destination. It is adjusted to be delayed by a smaller phase (this phase is the phase of the oscillation output signal of the PLL of the injection destination). When the frequency of the injection signal and the oscillation output signal of the injection destination PLL are different, the adjustment may be performed with reference to the rising edge of the pulse. That is, the rising timing of the injection signal may be adjusted so as to be delayed by a phase larger than π / 2 and smaller than 3π / 2 with respect to the rising timing of the oscillation output signal of the PLL of the injection destination.

Further, in the present embodiment, the case where mutual injection is performed in two phase-locked circuits has been described, but mutual injection may be performed in three or more phase-locked circuits. FIG. 5 is a diagram showing an example of a mutual injection phase-locked loop when mutual injection is performed in three phase-locked circuits. FIG. 5A is a block diagram showing a configuration of a mutual injection phase-locked loop including the first to third phase synchronization circuits 101 to 103 and the first to third injection controllers 111 to 113. The first injection controller 111 delays the second and third oscillation output signals so that they are injected with negative feedback with respect to the first oscillation output signal. FIG. 5B is a block diagram showing the configuration of the first injection controller 111. The first injection controller 111 has a delay means 121 that outputs an injection signal that delays the second oscillation output signal, and an injection signal that is injected into the first phase-locked loop 101 based on the first oscillation output signal is negative. A first phase-locked loop based on the delay controller 131 that controls the delay means 121 so as to be feedback, the delay means 141 that outputs the injection signal delayed from the third oscillation output signal, and the first oscillation output signal. A delay controller 151 that controls the delay means 141 so that the injection signal injected into the 101 becomes negative feedback is provided. Then, the injection signals output from the delay means 121 and 141 are also injected into the first phase-locked loop 101. The second injection controller 112 delays the first and third oscillation output signals to be injected by negative feedback with respect to the second oscillation output signal, and the third injection controller 113 uses the first and third oscillation output signals. The second oscillation output signal is delayed so as to be injected with negative feedback to the third oscillation output signal. The configurations of the second injection controller 112 and the third injection controller 113 are the same as those of the first injection controller 111. Further, the control means and the delay controller in the injection controllers 111 to 113 may be used for mutual injection when the frequencies of the oscillation output signals are the same, or when the frequencies of the oscillation output signals are different. It may be used in mutual injection in. In this way, mutual injection can be performed even in three or more phase-locked loops. Even when the mutual injection phase-locked loop has three or more phase-locked circuits, the configuration relating to the mutual injection of the two phase-locked circuits is as shown in FIGS. 1 and 4. Can be thought of as.

When mutual injection is performed in three or more phase-locked loops, injection signals from two or more phase-locked loops are usually injected into one phase-locked loop. In that case, for example, two or more injection signals may be injected with equal weights or different weights. In the latter case, for example, a weight inversely proportional to the distance between the phase-locked loops may be used, a weight inversely proportional to the square of the distance between the phase-locked loops may be used, or another weight may be used. good. When a weight inversely proportional to the distance between the phase-locked loops is used, specifically, the weight of the injection signal corresponding to the second oscillation output signal injected into the first phase-locked loop 101 and the third oscillation output signal. The ratio to the weight of the injection signal according to the above is the inverse of the distance between the first phase-locked loop 101 and the second phase-locked loop 102 and the inverse of the distance between the first phase-locked loop 101 and the third phase-locked loop 103. Each injection signal may be weighted so as to have a ratio with. For example, it is preferable to use a weight that is inversely proportional to the distance between the phase-locked loops when the influence of the distance is large with respect to mutual interference, and when the influence of the electromagnetic field is large, it is preferable to use the weight between the phase-locked loops. It is preferable to use a weight that is inversely proportional to the square of the distance.

Further, in the first and second phase-locked loops 11 and 12 of the mutual injection phase-locked loop 1 according to the present embodiment, the injection signal is injected into the voltage control oscillators 24 and 34 until the oscillation output signal is synchronized with the reference signal. Instead, the injection signal may be injected into the voltage control oscillators 24 and 34 after the oscillation output signal is synchronized with the reference signal.

Further, in the mutual injection phase-locked loop 1 according to the present embodiment, it goes without saying that any of the components that can be realized by analog or digital may be realized by either of them.

Further, in the above embodiment, each process or each function may be realized by centralized processing by a single device or a single system, or may be distributed processing by a plurality of devices or a plurality of systems. It may be realized by.

Further, in the above embodiment, the transfer of information performed between the components is performed by, for example, one of the components when the two components that transfer the information are physically different. It may be done by outputting information and accepting information by the other component, or if the two components that pass the information are physically the same, one component. It may be performed by moving from the processing phase corresponding to the other component to the processing phase corresponding to the other component.

Further, in the above embodiment, information related to the processing executed by each component, for example, information received, acquired, selected, generated, transmitted, or received by each component. Further, information such as threshold values, mathematical formulas, addresses, etc. used by each component in processing may be temporarily or for a long time held in a recording medium (not shown), even if it is not specified in the above description. In addition, each component or a storage unit (not shown) may store information on a recording medium (not shown). Further, the information may be read from the recording medium (not shown) by each component or a reading unit (not shown).

Further, in the above embodiment, when the information used in each component or the like, for example, the information such as the threshold value and the address used in the processing by each component and various setting values may be changed by the user, the above-mentioned The information may or may not be changed as appropriate by the user, even if it is not specified in the description. When the information can be changed by the user, the change is realized by, for example, a reception unit (not shown) that receives a change instruction from the user and a change unit (not shown) that changes the information in response to the change instruction. You may. The reception unit (not shown) may accept the change instruction from, for example, an input device, information transmitted via a communication line, or information read from a predetermined recording medium. ..

Further, in the above embodiment, each component may be configured by dedicated hardware, or a component that can be realized by software may be realized by executing a program. For example, each component can be realized by a program execution unit such as a CPU reading and executing a software program recorded on a recording medium such as a hard disk or a semiconductor memory. At the time of execution, the program execution unit may execute the program while accessing the storage unit or the recording medium. This program may be executed by being downloaded from a server or the like, and is executed by reading a program recorded on a predetermined recording medium (for example, an optical disk such as a CD-ROM, a magnetic disk, a semiconductor memory, etc.). May be done. Further, this program may be used as a program constituting a program product. Further, the number of computers that execute this program may be singular or plural. That is, centralized processing may be performed, or distributed processing may be performed.

Further, the present invention is not limited to the above embodiments, and various modifications can be made, and it goes without saying that these are also included in the scope of the present invention.

From the above, the mutual injection phase-locked loop according to the present invention has the effect of reducing the influence of mutual interference, and is useful as a circuit having two or more phase-locked loops.

1 Mutual injection phase-locked loop 11, 101 1st phase-locked loop 12, 102 2nd phase-locked loop 13 1st delay means 14 2nd delay means 15 1st delay controller 16 2nd delay controller 24, 34 Voltage controlled oscillator 41 Delayer 51 Multi-phase clock generator 52 Phase selection interpolation means 103 Phase-locked loop 111-113 1st to 3rd injection controllers 121, 141 Delay means 131, 151 Delay controller

Claims (4)

A first phase-locked loop that has a voltage controlled oscillator that outputs a signal with an oscillation frequency corresponding to the control voltage and outputs a first oscillation output signal whose phase is synchronized with the first reference signal.
A second phase-locked loop that has a voltage controlled oscillator that outputs a signal with an oscillation frequency corresponding to the control voltage and outputs a second oscillation output signal whose phase is synchronized with the second reference signal.
A first delay means for outputting a first injection signal obtained by delaying the first oscillation output signal so as to be negative feedback to the voltage controlled oscillator of the second phase-locked loop.
A second delay means for outputting a second injection signal obtained by delaying the second oscillation output signal so as to be negative feedback to the voltage controlled oscillator of the first phase-locked loop is provided.
The first injection signal is injected into the voltage controlled oscillator of the second phase-locked loop.
The second injection signal is a mutual injection phase-locked loop that is injected into the voltage controlled oscillator of the first phase-locked loop. The first and second oscillation output signals have the same frequency.
The first and second delay means are variable delay devices whose delay time can be changed, respectively.
A first delay controller that controls the delay time of the first delay means so that the first injection signal injected into the voltage controlled oscillator of the second phase-locked loop becomes negative feedback.
The claim further comprises a second delay controller that controls the delay time of the second delay means so that the second injection signal injected into the voltage controlled oscillator of the first phase-locked loop becomes negative feedback. 1. The mutual injection phase-locked loop according to 1. The first delay controller delays at least one of the first injection signal and the second oscillation output signal by a predetermined time, and then synchronizes the phases of both signals with the first delay. Control the delay time of the means,
The second delay controller delays at least one of the second injection signal and the first oscillation output signal by a predetermined time, and then synchronizes the phases of both signals with the second delay. The mutual injection phase-locked loop according to claim 2, which controls the delay time of the means. The first and second oscillation output signals have different frequencies.
The first and second delay means generate the first and second injection signals having an arbitrary phase difference with respect to the first and second oscillation output signals, respectively.
A first delay controller that controls the first delay means so that a first injection signal having a predetermined phase difference with respect to the second oscillation output signal is generated.
The first aspect of the present invention, further comprising a second delay controller that controls the second delay means so that a second injection signal having a predetermined phase difference with respect to the first oscillation output signal is generated. Mutual injection phase-locked loop.

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