JP7543071B2 - Oscillator Circuit - Google Patents

Description

The present invention relates to an oscillator circuit.

Frequency synthesizers that generate a clock of any frequency from a reference clock are used in various ICs (Integrated Circuits). PLL circuits are widely used as such frequency synthesizers. Figures 1(a) to (c) are block diagrams that explain the basic architecture of a PLL circuit.

1A shows an analog PLL circuit 1. The analog PLL circuit 1 includes a phase comparator (PFD: Phase Frequency Detector) 10, a charge pump circuit 12, a low-pass filter 14, a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) 16, and a frequency divider 18. The VCO 16 oscillates at a frequency according to an analog control voltage V _CTRL . The output clock CLK_VCO of the VCO 16 is divided by N by the frequency divider 18. The phase detector 10 detects the phase difference between the divided clock CLK_DIV and the reference clock CLK_REF, and controls the charge pump circuit 12. The low-pass filter 14 is a loop filter that smoothes the output voltage of the charge pump circuit 12, and generates the control voltage V _CTRL .

The analog PLL circuit 1 in FIG. 1(a) has been used for a long time in various applications and is highly reliable, but there is a problem that the chip size becomes large due to the loop filter. In addition, to achieve sufficient performance, the circuit designer must optimize the circuit layout.

FIG. 1B shows an all digital PLL circuit (ADPLL: All Digital PLL) 2. The ADPLL circuit 2 receives a frequency control word (FCW) and a reference clock CLK_REF, and generates an output clock CLK_DCO by multiplying the reference clock CLK_REF according to the FCW. The ADPLL circuit 2 includes a frequency phase detector 20, a digital filter 22, and a digitally controlled oscillator (DCO: Digital Controlled Oscillator) 24. The DCO 24 oscillates at a frequency according to the input control code D _CTRL . The frequency phase comparator 20 has functions equivalent to the phase comparator 10, the charge pump circuit 12, and the divider 18 in FIG. 1, and is composed of a TDC (time-to-digital converter), an adder, and a counter. The digital signal generated by the frequency phase comparator 20 is filtered by the digital filter 22 and input to the DCO 24.

The ADPLL circuit 2 in FIG. 1(b) has the advantage that it can be configured with digital circuits that are easy to design using fine semiconductor processes, making it possible to reduce the chip area. On the other hand, even though it is all-digital, the circuit designer must manually optimize the layout of the frequency phase comparator 20 and DCO 24 to meet the desired specifications.

Figure 1(c) shows an injection-locked PLL circuit 3 (also called IL-PLL (Injection Locked PLL)). The IL-PLL circuit 3 can be designed with an analog or digital circuit architecture, but here we will explain the case where it is configured with a digital circuit. The IL-PLL circuit 3 includes a DCO 30, a feedback circuit 40, and an edge injection circuit 50. The IL-PLL circuit 3 is understood as a hybrid of feedback control and feedforward control, and stabilizes the oscillation frequency of the DCO 30 by feedback control using the feedback circuit 40, which corresponds to the frequency phase comparator 20 and digital filter 22 in Figure 1(b). The edge injection circuit 50 extracts an edge of the reference clock CLK_REF and injects the extracted edge into the DCO 30 to realign the phase of the output clock CLK_DCO. The IL-PLL circuit may also be called an MDLL (Multiplying Delay Locked Loop) circuit depending on the method of edge injection.

The IL-PLL circuit has the advantage that (i) the loop bandwidth is widened by injection locking, making it possible to achieve low phase noise (low jitter), and when configured as a digital circuit, (ii) the absence of the phase comparator 10 and charge pump circuit 12 in Figure 1(a) makes it possible to achieve low noise. In addition, (iii) it is less susceptible to the effects of noise from the feedback path, allowing for a high degree of freedom in layout, and therefore the desired characteristics can be obtained even with automatic placement and routing using design support tools such as a P&R (Place and Route) tool.

JP 2017-143398 A

R. Farjad-rad et al., "A 0.2-2GHz 12mW multiplying DLL for low-jitter clock synthesis in highly-integrated data-communication chips", 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No. .02CH37315), San Francisco, CA, USA, 2002, pp. 56-400 S. Kundu, B. Kim and C. H. Kim, "A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection", 2016 IEEE International Solid -State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 326-327 R. Wang and F. F. Dai, "A 0.8-1.3 GHz multi-phase injection-locked PLL using capacitive coupled multi-ring oscillator with reference suppression spur", 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, pp .1-4 H. C. Ngo, K. Nakata, T. Yoshioka, Y. Terashima, K. Okada and A. Matsuzawa, "A 0.42ps-jitter -241.7dB-FOM synthesized injection-locked PLL with noise-isolation LDO", 2017 IEEE International Solid -State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 150-151 S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi, "A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple -Point Frequency/Phase/Slope Calibrator", 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 490-492 S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi, "A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point "Background Calibrator", IEEE Journal of Solid-State Circuits (Early Access) B. M. Helal, M. Z. Straayer, G. Wei and M. H. Perrott, "A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance", IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 855-863, April 2008 Y. Lee, T. Seong, S. Yoo and J. Choi, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique", IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 1192-1202, April 2018 G. Tak and K. Lee, "A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 2, pp. 485-497, Feb. 2018 T. Liao, J. Su and C. Hung, "Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 3, pp. 589-592, March 2013 N. Da Dalt, "An Analysis of Phase Noise in Realigned VCOs", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 3, pp. 143-147, March 2014 W. Deng et al., "A 0.048mm2 3mW synthesized fractional-N PLL with a soft injection-locking technique", 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, 2015, pp. 1-3

IL-PLL circuits are wideband and can generate clocks with very low phase noise (low jitter). However, IL-PLL circuits have problems with frequency jumps and reference spurs, as explained below.

Fig. 2(a) is a diagram showing frequency changes in a normal PLL circuit, and Fig. 2(b) is a diagram explaining a frequency jump in an IL-PLL circuit. As shown in Fig. 2(a), in a normal PLL circuit, when the frequency f _REF of the reference clock CLK_REF changes sharply from f _c1 to f _c2 , the frequency of the output clock gradually approaches the changed frequency f _c2 over time.

In contrast, in an IL-PLL circuit, as shown in Figure 2(b), when a frequency fluctuation occurs in the reference clock CLK_REF, the feedforward control causes forced edge replacement, which causes a frequency jump.

When the output clock CLK_DCO of the IL-PLL circuit is used as the system clock, a frequency jump in the system clock may cause the entire system to malfunction.

One of the important characteristics of a frequency synthesizer is the reference spurious characteristic. Figure 3 is a diagram explaining the reference spurious. The reference spurious (Ref-Spur.) occurs at an offset frequency f _c ±n×f REF, which is an integer multiple (n=1, 2, ...) of the reference frequency f _REF , with the output clock frequency (carrier frequency) fc at the _center .

High spurious emissions can cause degradation of RF system performance and become unwanted noise components in A/D and D/A converters. In principle, the output clock spectrum of a conventional IL-PLL circuit contains many reference spurious emissions, which are unwanted frequency components, so improvements are needed.

The present disclosure has been made in consideration of such problems, and one exemplary objective of one aspect thereof is to provide an injection-locked oscillator circuit that can suppress frequency jumps and/or reference spurious.

One aspect of the present disclosure relates to an injection-locked oscillator circuit. The oscillator circuit includes a variable frequency oscillator that generates an oscillator clock, a feedback circuit that controls the variable frequency oscillator so that the frequency of the oscillator clock approaches a target frequency corresponding to a reference clock, and a phase interpolator that receives the oscillator clock and the reference clock and generates an interpolated clock obtained by phase-interpolating the oscillator clock and the reference clock. The oscillator circuit is configured so that the oscillator clock of the variable frequency oscillator can be replaced by the interpolated clock.

Another aspect of the present disclosure is also an injection-locked oscillator circuit. The oscillator circuit includes a window generator that generates a window signal, a variable delay circuit, a phase interpolator that receives an oscillator clock corresponding to a reference clock and the output of the variable delay circuit, the output of which is connected to the input of the variable delay circuit, (i) outputs an interpolated clock obtained by phase-interpolating the reference clock and the oscillator clock during a period in which the window signal is asserted, and (ii) outputs the oscillator clock during a period in which the window signal is negated, a phase comparator that generates an up-down signal corresponding to the phase of the oscillator clock and the phase of the reference clock, and a loop filter that controls the delay amount of the variable delay circuit according to the up-down signal.

In addition, any combination of the above components, or conversion of the present invention between methods, devices, etc., are also valid aspects of the present invention.

According to certain aspects of the present disclosure, it is possible to suppress frequency jumps and/or reference spurs.

1(a) to 1(c) are block diagrams illustrating the basic architecture of a PLL circuit. FIG. 2(a) is a diagram showing frequency changes in a normal PLL circuit, and FIG. 2(b) is a diagram explaining a frequency jump in an IL-PLL circuit. FIG. 13 is a diagram illustrating a reference spurious. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention; FIG. 2 is a diagram illustrating the operation of a phase interpolator. 5 is an operation waveform diagram of the PLL circuit of FIG. 4. 5 is an operation waveform diagram of the edge injection circuit of the PLL circuit of FIG. 4. FIG. 8(a) is a diagram showing frequency changes in the PLL circuit of FIG. 4, and FIG. 8(b) is a diagram showing frequency changes in a conventional PLL circuit. 9A to 9C are diagrams for explaining the jitter of the oscillator clock. FIG. 2 is a circuit diagram illustrating an example of the configuration of a phase interpolator. FIG. 2 is a circuit diagram showing a configuration example of a PLL circuit. FIG. 11 is a circuit diagram of a PLL circuit according to a first modified example. FIG. 11 is a circuit diagram of a PLL circuit according to a second modified example.

(Overview of the embodiment)
A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified summary of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not an exhaustive summary of all possible embodiments, and is not intended to limit essential components of the embodiments. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

An injection-locked oscillator circuit according to one embodiment includes a variable frequency oscillator, a feedback circuit, and an edge injection circuit. The variable frequency oscillator generates an oscillator clock. The feedback circuit controls the variable frequency oscillator so that the frequency of the oscillator clock approaches a target frequency according to a reference clock. The edge injection circuit receives the oscillator clock and the reference clock, generates an injection edge by phase-interpolating the oscillator clock and the reference clock, and injects the injection edge into the variable frequency oscillator.

Compared to the conventional configuration in which the edge of the reference clock is used as the injection edge to replace the clock of the variable frequency oscillator, frequency jumps can be suppressed. Reference spurious can also be suppressed.

In one embodiment, the edge injection circuit may include a phase interpolator that phase-interpolates the oscillator clock and the reference clock to generate an interpolated clock. The edge injection circuit may inject the interpolated clock as an injected edge into the variable frequency oscillator.

In one embodiment, the variable frequency oscillator may include a variable delay circuit. The interpolation clock may be provided to an input of the variable delay circuit. The phase interpolator may be switchable between an enabled state and a disabled state, and in the enabled state, the interpolation clock may have a phase that is an internal division of the phases of the oscillator clock and the reference clock according to a set value of the phase ratio. In the disabled state, the interpolation clock may have a phase that corresponds to the oscillator clock. With this configuration, the phase interpolator can achieve an operation equivalent to that of a multiplexer.

In one embodiment, the phase interpolator may include a capacitor and M driving units whose outputs are connected to the capacitor. Each of the M driving units receives a reference clock and an oscillator clock, drives the capacitor in response to the reference clock in a first state, and drives the capacitor in response to the oscillator clock in a second state. By substituting the input capacitance of a logic gate for the capacitor, the phase interpolator can be designed by logic synthesis and automatic placement and routing.

In one embodiment, during the period when the window signal is negated, all of the M driving units may be in the second state, and during the period when the window signal is asserted, k of the M driving units (k≦M) may be in the first state.

In one embodiment, the oscillator circuit may further include a window generator that generates a window signal that is asserted once every N cycles (N≧2) of the oscillator clock. The timing of opening (asserting) the window and closing (negating) the window, which are specified by the window signal, do not depend on the reference clock. Therefore, the window can be reliably opened and closed regardless of the presence or absence of the reference clock while the variable frequency oscillator is oscillating. In addition, by adjusting the timing so that the injection edge of the reference clock is reliably included in the period when the window is open, glitches and harmonic oscillations caused by the window signal do not occur. If no transition (edge) of the reference clock occurs during the period when the window is open, the period of the oscillator clock becomes longer at a rate of once per predetermined cycle (multiplication number), but the oscillation does not stop. In addition, if the injection strength of the phase complementer is less than 1/2, the fluctuation of the period can be minimized. In this way, according to one embodiment, some of the conventional problems can be solved.

An injection-locked oscillator circuit according to one embodiment includes a window generator that generates a window signal, a variable delay circuit, a phase interpolator that receives an oscillator clock corresponding to a reference clock and the output of the variable delay circuit, the output of which is connected to the input of the variable delay circuit, (i) outputs an interpolated clock obtained by phase-interpolating the reference clock and the oscillator clock during a period in which the window signal is asserted, and (ii) outputs the oscillator clock during a period in which the window signal is negated, a phase comparator that generates an up-down signal corresponding to the phase of the oscillator clock and the phase of the reference clock, and a loop filter that controls the delay amount of the variable delay circuit according to the up-down signal.

The phase interpolator may include a capacitor and M drive units. Each of the M drive units receives a reference clock and an internal clock, and has an output connected to the capacitor, and drives the capacitor in response to the reference clock in a first state and drives the capacitor in response to the oscillator clock in a second state.

(Embodiment)
The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions are omitted as appropriate. In addition, the embodiments are not intended to limit the invention, but are merely examples, and all of the features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, "a state in which component A is connected to component B" includes not only cases in which component A and component B are directly physically connected, but also cases in which component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved by their combination.

Similarly, "a state in which component C is provided between components A and B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect their electrical connection state or impair the function or effect achieved by their combination.

Figure 4 is a block diagram of a PLL circuit 100 according to an embodiment. The PLL circuit 100 is an injection-locked oscillator circuit (frequency synthesizer) and includes a variable frequency oscillator 200, an edge injection circuit 220, a feedback circuit 300, and a window generator 400.

The variable frequency oscillator 200 includes a variable delay circuit 210 and an inverter 230, and generates an oscillator clock CLK_OSC having a frequency according to the delay amount set in the variable delay circuit 210. This oscillator clock CLK_OSC is extracted as the output clock CLK_DCO of the PLL circuit 100. The oscillator clock CLK_OSC at the output of the inverter 230 is referred to as the internal clock CLK_INT.

The feedback circuit 300 controls the delay amount of the variable delay circuit 210 so that the frequency of the oscillator clock CLK_OSC approaches a target frequency f _REF according to the reference clock CLK_REF. The configuration and control method of the feedback circuit 300 are not particularly limited, and any known technology may be used.

The edge injection circuit 220 receives the oscillator clock CLK_OSC and the reference clock CLK_REF, generates an injection edge INJ_EDGE by phase-interpolating the oscillator clock CLK_OSC and the reference clock CLK_REF, and injects the injection edge INJ_EDGE into the variable frequency oscillator 200.

In this embodiment, the edge injection circuit 220 is incorporated into the variable frequency oscillator 200, and outputs an injection edge INJ_EDGE during the period when the window signal INJ_WIND is asserted, and outputs an internal clock CLK_INT during the period when the window signal INJ_WIND is negated.

The window generator 400 generates a window signal INJ_WIND. This window signal INJ_WIND is a timing signal that defines the timing (period) of injection locking in the PLL circuit 100. That is, the edge injection circuit 220 injects an injection edge INJ_EDGE into the variable frequency oscillator 200 in response to the window signal INJ_WIND.

The edge injection circuit 220 includes a phase interpolator 250. The phase interpolator 250 generates the interpolated clock CLK_PI by phase-interpolating the oscillator clock CLK_OSC and the reference clock CLK_REF.

Specifically, the phase interpolator 250 receives the reference clock CLK_REF at the first input IN1 and the internal clock CLK_INT, which is the oscillator clock CLK_OSC, at the second input IN2. The phase interpolator 250 generates an interpolated clock CLK_PI obtained by phase-interpolating the signal at the first input IN1 (reference clock CLK_REF) and the signal at the second input IN2 (oscillator clock CLK_INT), and generates it at the output OUT. The edge injection circuit 220 injects the interpolated clock CLK_PI into the variable frequency oscillator 200 as an injection edge INJ_EDEG.

5 is a diagram for explaining the operation of the phase interpolator 250. Here, a case is taken as an example in which the phase (edge occurrence time) _φ1 of the signal of the first input IN1 is advanced, and the phase _φ2 of the signal of the second input IN2 is delayed. The phase _φOUT of the output of the phase interpolator 250 can be expressed by equation (1).
φ _OUT =φ ₁ +k/M×(φ ₂ -φ ₁ )+τ _DELAY
= {(M-k)×φ ₁ +k×φ ₂ }/M+τ _DELAY …(1)
τ _DELAY is a delay inherent to the phase interpolator 250. M is the resolution (number of gradations) of the phase interpolator 250, and is a constant equal to or greater than 2. k is a set value of the phase ratio, and k can be selected from 0 to M. FIG. 5 shows the case where M=3. That is, the phase φ _OUT of the output OUT of the phase interpolator 250 is obtained by adding a delay τ _DELAY to the phase obtained by internally dividing the phases φ ₁ and φ ₂ of the two inputs IN1 and IN2 at k:(M−k). When k=0, φ _OUT =φ ₁ +τ _DELAY , and when k=M, φ _OUT =φ ₂ +τ _DELAY .

Returning to FIG. 4, in this embodiment, the output OUT of the phase interpolator 250 is connected to the input of the variable delay circuit 210, and the interpolation clock CLK_PI is supplied to the variable delay circuit 210.

The phase interpolator 250 is configured to be switchable between an enabled state and a disabled state according to the window signal INJ_WIND. In the enabled state, the interpolation clock CLK_PI has a phase that is the internal division of the phases of the internal clock CLK_INT, which is the oscillator clock, and the reference clock CLK_REF according to the set value of the phase ratio. In other words, in the enabled state, the phase interpolator 250 operates in a state where the phase ratio k ≠ M.

Conversely, in the disabled state, the phase of the interpolated clock CLK_PI contains phase information of only the oscillator clock CLK_INT, and does not contain phase information of the reference clock CLK_REF. In other words, in the disabled state, the phase interpolator 250 operates in a state where k=M.

The above is the configuration of the PLL circuit 100. Next, the operation will be described. Fig. 6 is a waveform diagram showing the operation of the PLL circuit 100 shown in Fig. 4. Here, for the sake of simplicity and ease of understanding, the delay τ _DELAY of the edge injection circuit 220 (phase interpolator 250) is ignored.

The vertical and horizontal axes of the waveform diagrams and time charts referred to in this specification have been appropriately enlarged or reduced to facilitate understanding, and the waveforms shown have been simplified, exaggerated, or emphasized to facilitate understanding.

The window signal INJ_WIND is asserted once per predetermined cycle of the reference clock CLK_REF. Of the interpolated clock CLK_PI obtained by phase-interpolating the reference clock CLK_REF and the internal clock CLK_INT, the portion included in the section in which the window signal INJ_WIND is asserted (high) is used as the injection edge INJ_EDGE. When this injection edge INJ_EDGE is injected, the edge of the oscillator clock CLK_DCO is replaced with the edge of the injection edge INJ_EDGE, forcing phase synchronization. UP_DN indicates the result of the phase comparison in the feedback circuit 300.

7 is an operation waveform diagram of the edge injection circuit 220 of the PLL circuit 100 of FIG. 4. FIG. 7 shows an enlarged edge injection period. In this example, the resolution of the phase interpolator 250 is M=3. During the period in which the window signal INJ_WIND is negated (low), the phase interpolator 250 operates in a state of k=3, and the output of the phase interpolator 250, i.e., the oscillator clock CLK_DCO, is delayed by τ _DELAY with respect to the internal clock CLK_INT. In other words, the phase interpolator 250 of the edge injection circuit 220 passes the internal clock CLK_INT, forming a ring oscillator.

During the period in which the window signal INJ_WIND is asserted (high), the phase interpolator 250 operates in any one of states k = 0, 1, 2, and 3. The output of the phase interpolator 250, that is, the oscillator clock CLK_DCO, is delayed by τ _DELAY + k × Δt with respect to the internal clock CLK_INT.
Δt=|T _ref −T _int |/3
That is, the edges of the oscillator clock CLK_DCO are replaced by the injection edges of the interpolated clock CLK_PI.

Figures 6 and 7 show the case where the internal clock CLK_INT leads, but the same operation occurs when the phase relationship is reversed.

Figure 8(a) is a diagram showing frequency changes in the PLL circuit 100 of Figure 4, and Figure 8(b) is a diagram showing frequency changes in a conventional PLL circuit. With the PLL circuit 100 of Figure 4, it is possible to suppress frequency jumps, as shown in Figure 8(a).

Figures 9(a) to (c) are diagrams explaining the jitter of the oscillator clock. Figure 9(a) shows the waveform of the oscillator clock CLK_DCO. Figure 9(b) shows the integrated value of the jitter of a conventional PLL circuit, and Figure 9(c) shows the integrated value of the jitter of the PLL circuit of Figure 4. According to this embodiment, it is possible to reduce the influence of the reference spurious. Note that in this embodiment, the RMS jitter increases slightly in exchange for the reduction in the reference spurious.

In the configuration of FIG. 4, the injection strength can be adjusted according to the phase ratio k during the injection period in which the window signal INJ_WIND is asserted. By adjusting the injection strength according to the application of the PLL circuit 100, the degree of frequency jump suppression and the degree of reference spurious suppression can be adjusted.

If k = M is set, it can be operated as a conventional PLL circuit, and if k = 0 is set, it can be operated as a conventional injection-locked PLL circuit that directly injects the reference clock CLK_REF.

10 is a circuit diagram showing a configuration example of the phase interpolator 250. ENPI is a 2-bit setting value that specifies the phase ratio k in the injection period. The phase interpolator 250 includes an encoder 252, logic gates 254 and 256, M (in this example, M=3) driving units 260_1 to 260_3, and a capacitor C _OUT . When designing using logic synthesis and automatic placement and wiring, the capacitor C _OUT may be substituted with the input capacitance of the logic gate, etc.

The encoder 252 converts the binary control code ENPI[1:0] into a negative logic thermometer code PIB[2:0]. The logic gate 254 logically inverts the window signal INJ_WIND to generate a negative logic window signal INJ_WINDB.

Logic gate 256 performs a NOR on each bit of thermometer code PIB[2:0] and window signal INJ_WINDB to generate thermometer code PI[2:0]. Thermometer code PI[2:0] has the inverted logic of PIB[2:0] during the window period (INJ_WIND = H, INJ_WINDB = L), and is all zeros [000] during other periods (INJ_WIND = B, INJ_WINDB = H).

Each drive unit 260 receives input signals IN1, IN2 (CLK_REF, CLK_INT) and thermometer codes PIB[2:0], PI[2:0].

Each drive unit 260 can be switched between a first state in which its output changes in response to the input signal IN1 (CLK_REF) and a second state in which its output changes in response to the input signal IN2 (CLK_INT).

The state of each drive unit 260_i (i = 1 to 3) changes according to the window signal INJ_WINDB and the corresponding bit PIB[i-1] of the thermometer code PIB.

When INJ_WIND=1, ENPI[11], all the driving units 260_1 to 260_3 are in the first state, and the driving units 260_1 to 260_M charge and discharge the output capacitor C _OUT according to the reference clock CLK_REF. As a result, the output clock CLK_DCO has a phase according to the reference clock CLK_REF.

When INJ_WIND=1 and ENPI[00], all the driving units 260_1 to 260_3 are in the second state, and the driving units 260_1 to 260_M charge and discharge the output capacitor C _OUT according to the internal clock CLK_INT. As a result, the output clock CLK_DCO has a phase according to the internal clock CLK_INT.

When INJ_WIND = 1 and ENPI [01] or [10], one or two drive units 260 operate in the first state, and the rest operate in the second state. As a result, the output clock CLK_DCO has a phase that is an interpolation of the phases of the internal clock CLK_INT and the reference clock CLK_REF.

When INJ_WIND = 0, all drive units 260_1 to 260_3 are in the second state, and the output clock CLK_DCO has a phase that corresponds to the internal clock CLK_INT.

This phase interpolator 250 can be designed using logic synthesis and automatic placement and routing.

As described above, the configurations of the variable frequency oscillator 200, feedback circuit 300, and window generator 400 may each use publicly known technology and are not particularly limited, but several configuration examples are shown below.

Figure 11 is a circuit diagram showing an example configuration (100A) of the PLL circuit 100. The feedback circuit 300 includes a phase detector 310 and a loop filter 320. The phase detector 310 is enabled during the period in which the window signal INJ_WIND is asserted, and compares the phase of the reference clock CLK_REF with that of the oscillator clock (internal clock CLK_INT) to generate an up-down signal UP_DN. The loop filter 320 increases or decreases the delay amount of the variable delay circuit 210 according to the up-down signal UP_DN.

The phase detector is preferably a symmetric phase detector. By enabling the symmetric phase detector only during the period when the window signal is asserted, the phase pull-in range can be expanded to the range of one period of the reference clock.

Instead of the phase detector 310, the feedback circuit 300 may include a phase frequency detector that is enabled during the period when the window signal INJ_WIND is asserted, compares the phase and frequency of the oscillator clock CKL_OSC and the reference clock CLK_ERF, and generates up and down pulses that indicate the comparison result. By employing a phase frequency detector that originally has a wide phase pull-in range and has a frequency pull-in function, and further enabling the phase frequency detector only during the period when the window signal is asserted, the phase pull-in range can be expanded practically infinitely.

If an injection edge does not occur even though the window is open, the frequency of the variable frequency oscillator will fluctuate in the short term for each period of the reference clock. Therefore, the window generator may keep the window signal negated when it cannot detect an edge of the reference clock. This allows the PLL circuit to continue generating clocks even when the reference clock stops. Alternatively, the injection strength of the phase complementer can be made less than 1/2 to minimize the fluctuation in the period. Furthermore, the frequency of the variable frequency oscillator will fluctuate only immediately after the reference clock is lost, but can be kept constant thereafter.

The window generator 400 includes a counter 410 and a selection logic 420. The counter 410 asserts an output once every N cycles of the oscillator clock CLK_INT. The selection logic 420 extracts the internal clock CLK_INT while the output of the counter 410 is asserted to generate the window signal INJ_WIND.

The above embodiments are merely examples, and those skilled in the art will understand that various modifications are possible in the combination of each component and each processing process, and that such modifications are also within the scope of the present invention. The following describes such modifications.

(Variation 1)
12 is a circuit diagram of a PLL circuit 100B according to Modification 1. An adaptive control unit 500 dynamically changes the phase ratio k (control code ENPI) of the phase interpolator 250 in accordance with the operating state of the PLL circuit 100B.

For example, the adaptive control unit 500 includes a window monitor circuit 510. The window monitor circuit 510 determines whether the reference clock CLK_REF is included within the injection period defined by the window signal INJ_WIND. When the reference clock CLK deviates from the injection period, the OUTSIDE signal is asserted (H). When the OUTSIDE signal is asserted, the setting circuit 520 outputs a pre-set phase ratio value and supplies it to the phase interpolator 250. The adaptive control unit 500 may include a ΔΣ modulator 530. This makes it possible to set a non-integer, decimal phase ratio for the phase interpolator 250.

(Variation 2)
13 is a circuit diagram of a PLL circuit 100C according to the second modification. The edge injection circuit 220 includes a phase interpolator 250 and a multiplexer 222. The multiplexer 222 selects the output CLK_PI of the phase interpolator 250 during an injection period in which the window signal INJ_WIND is asserted, and selects the internal clock CLK_INT during a period in which the window signal INJ_WIND is negated. This modification also makes it possible to suppress frequency jumps or reference spurious.

(Variation 3)
The technology according to the present disclosure can be applied to an oscillator circuit in which an edge is injected by a selector, that is, an IL-PLL circuit or an MDLL (Multiplying Delay Locked Loop) circuit. The technology can be applied to both digital PLL/DLL and analog PLL/DLL, and the variable frequency oscillator 200 may be a DCO or a VCO.

The present invention has been described using specific terms based on the embodiments, but the embodiments merely show the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the concept of the present invention as defined in the claims.

REFERENCE SIGNS LIST 100 PLL circuit 200 Variable frequency oscillator 210 Variable delay circuit 220 Edge injection circuit 230 Inverter 250 Phase interpolator 260 Driving unit 300 Feedback circuit 310 Phase detector 320 Loop filter 400 Window generator 410 Counter 420 Selection logic 500 Adaptive control section 510 Window monitor circuit 520 Setting circuit

Claims (8)

An injection-locked oscillator circuit,
a variable frequency oscillator which is a ring oscillator including a variable delay circuit and generates an oscillator clock having a frequency according to the delay amount of the variable delay circuit ;
a feedback circuit that controls the variable delay circuit so that the frequency of the oscillator clock approaches a target frequency corresponding to a reference clock;
an edge injection circuit including a phase interpolator inserted in the ring oscillator, the phase interpolator performing phase interpolation between the oscillator clock and the reference clock to generate an interpolated clock and supplying the interpolated clock to an input of the variable delay circuit;
Equipped with
The phase interpolator is switchable between an enabled state and a disabled state, and is configured to output the interpolated clock having a phase obtained by dividing the phases of the oscillator clock and the reference clock internally in accordance with a set value of a phase ratio in the enabled state, and to output the interpolated clock having a phase corresponding to the oscillator clock in the disabled state . The phase interpolator comprises:
A capacitor;
M driving units, each of which receives the reference clock and the oscillator clock, has an output connected to the capacitor, drives the capacitor in response to the reference clock in a first state, and drives the capacitor in response to the oscillator clock in a second state;
2. The oscillator circuit of claim 1 , comprising: The phase interpolator comprises:
During a period in which the window signal is negated, the disabled state is reached, and all of the M driving units are in the second state;
3. The oscillator circuit according to claim 2 , wherein during a period in which a window signal is asserted , k of the M driving units (k≦M) are in the enabled state and in the first state. 4. The oscillator circuit of claim 3 , further comprising a window generator that generates the window signal that is asserted once every N cycles (N≧2) of the oscillator clock. a window generator for generating a window signal that is asserted once every N cycles (N≧2) of the oscillator clock;
2. The oscillator circuit according to claim 1, wherein the phase interpolator is in the enabled state during a period in which the window signal is asserted, and in the disabled state during a period in which the window signal is negated. An injection-locked oscillator circuit,
a window generator for generating a window signal;
A variable delay circuit;
a phase interpolator that receives a reference clock and an internal clock corresponding to the output of the variable delay circuit, has an output connected to an input of the variable delay circuit, (i) outputs an interpolated clock having a phase obtained by dividing the phases of the internal clock and the reference clock internally in accordance with a set value of a phase ratio during a period in which the window signal is asserted, and (ii) outputs the internal clock during a period in which the window signal is negated;
a feedback circuit that controls the delay amount of the variable delay circuit in response to a phase of the internal clock and a phase and/or a frequency of the reference clock;
1. An oscillator circuit comprising: The phase interpolator comprises:
A capacitor;
M driving units, each of which receives the reference clock and the internal clock, has an output connected to the capacitor, drives the capacitor in response to the reference clock in a first state, and drives the capacitor in response to the internal clock in a second state;
7. The oscillator circuit of claim 6 , comprising: An injection-locked oscillator circuit,
a variable frequency oscillator which is a ring oscillator including a variable delay circuit and generates an oscillator clock having a frequency according to the delay amount of the variable delay circuit;
a feedback circuit that controls the variable delay circuit so that the frequency of the oscillator clock approaches a target frequency corresponding to a reference clock;
a phase interpolator that outputs an interpolated clock having a phase obtained by dividing the phases of the oscillator clock and the reference clock internally in accordance with a set value of a phase ratio;
a multiplexer that receives the interpolation clock and the oscillator clock, selects one of them, and supplies it to an input of the variable delay circuit;
1. An oscillator circuit comprising:

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