JP6966844B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device including a semiconductor layer in which a trench is formed and having a structure in which a bidirectional Zener diode is formed in the trench.

Patent Document 1 discloses a semiconductor device including a bidirectional Zener diode. The semiconductor device includes an n ⁺ type semiconductor substrate. On a semiconductor substrate, n ^- -type epitaxial layer is formed. A trench is formed in the surface layer portion of the epitaxial layer. A gate oxide film is formed on the inner wall of the trench. A bidirectional Zener diode including an n ⁺ type region, a p-type region, and an n ⁺ type region is formed in the trench.

Japanese Unexamined Patent Publication No. 2001-257349

The semiconductor device according to Patent Document 1 has a structure in which a p-type region of a bidirectional Zener diode faces an n ^{-type epitaxial layer with a gate oxide film interposed therebetween.} Therefore, if a ^{voltage drop occurs between a pair of n +} -type regions sandwiching the p-type region, electrons may be attracted to the region facing the ^{n − -type epitaxial layer in the p-type region.} In this case, an inverted layer in which the p-type is inverted to the n-type is formed in the p-type region, and as a result, an undesired increase in current may be caused.

Therefore, one object of the present invention is to provide a semiconductor device capable of suppressing an undesired increase in current in a structure in which a bidirectional Zener diode is formed in a trench.

A semiconductor device according to an embodiment of the present invention includes a first conductive type semiconductor layer having a main surface on which a diode trench is formed, a side wall insulating film formed along the side wall of the diode trench, and the diode. An inner wall insulating film including a bottom wall insulating film formed along the bottom wall of the trench and having a thickness larger than the thickness of the side wall insulating film, and formed on the bottom wall insulating film in the diode trench. A bidirectional Zener diode having at least one second conductive mold portion formed between the pair of first conductive mold portions and the pair of first conductive mold portions.

The semiconductor device according to another embodiment of the present invention includes a first conductive type semiconductor layer having a main surface on which a diode trench is formed, an inner wall insulating film formed along the inner wall of the diode trench, and the diode. In the semiconductor layer, a bidirectional Zener diode having at least one second conductive mold portion formed in a trench and formed between a pair of first conductive mold portions and the pair of first conductive mold portions. It includes a second conductive type floating region formed in a region along the bottom wall of the diode trench.

In the semiconductor device according to the embodiment of the present invention, a bottom wall insulating film is interposed between the bottom wall of the diode trench and the bidirectional Zener diode. The bottom wall insulating film forms an inversion suppression structure that suppresses the inversion of the conductive type of the second conductive type portion of the bidirectional Zener diode to the first conductive type.
As a result, even if a voltage drop occurs between the pair of first conductive mold portions, it is possible to prevent the conductive mold of the second conductive mold portion from reversing to the first conductive mold portion. Therefore, it is possible to provide a semiconductor device capable of suppressing an undesired increase in current.

In the semiconductor device according to another embodiment of the present invention, an inner wall insulating film is interposed between the bottom wall of the diode trench and the bidirectional Zener diode. In addition, the semiconductor layer is formed with a second conductive type floating region facing the bidirectional Zener diode with the inner wall insulating film interposed therebetween. These inner wall insulating films and floating regions form an inversion suppression structure that suppresses the inversion of the conductive type of the second conductive type portion of the bidirectional Zener diode to the first conductive type.

As a result, even if a voltage drop occurs between the pair of first conductive mold portions, it is possible to prevent the conductive mold of the second conductive mold portion from reversing to the first conductive mold portion. Therefore, it is possible to provide a semiconductor device capable of suppressing an undesired increase in current.

FIG. 1 is a plan view showing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. FIG. 3 is a diagram showing a main part of the trench gate structure. FIG. 4 is an enlarged view of the region surrounded by the alternate long and short dash line IV of FIG. FIG. 5 is a cross-sectional view taken along the line VV of FIG. FIG. 6 is a diagram showing a main part of the trench diode structure. FIG. 7 is a diagram showing a main part of the electric field relaxation structure. FIG. 8A is a cross-sectional view for explaining the manufacturing method of the semiconductor device of FIG. FIG. 8B is a cross-sectional view showing the process after FIG. 8A. FIG. 8C is a cross-sectional view showing the process after FIG. 8B. FIG. 8D is a cross-sectional view showing the process after FIG. 8C. FIG. 8E is a cross-sectional view showing the process after FIG. 8D. FIG. 8F is a cross-sectional view showing the process after FIG. 8E. FIG. 8G is a cross-sectional view showing the process after FIG. 8F. FIG. 8H is a cross-sectional view showing the process after FIG. 8G. FIG. 8I is a cross-sectional view showing the process after FIG. 8H. FIG. 8J is a cross-sectional view showing the process after FIG. 8I. FIG. 8K is a cross-sectional view showing the process after FIG. 8J. FIG. 8L is a cross-sectional view showing the process after FIG. 8K. FIG. 8M is a cross-sectional view showing the process after FIG. 8L. FIG. 9 is a diagram for explaining the operation of the bidirectional Zener diode. FIG. 10 is a diagram for explaining the operation of the bidirectional Zener diode. FIG. 11 is a cross-sectional view of a portion corresponding to FIG. 5, and is a diagram showing a semiconductor device according to a second embodiment of the present invention. FIG. 12 is a cross-sectional view of a portion corresponding to FIG. 5, and is a diagram showing a semiconductor device according to a third embodiment of the present invention. FIG. 13 is a cross-sectional view of a portion corresponding to FIG. 4, and is a diagram showing a modified example of the bidirectional Zener diode. FIG. 14 is a plan view showing a modified example of the surface electrode. FIG. 15 is a schematic plan view of the semiconductor device according to the embodiment of the reference invention. FIG. 16 is a diagram showing a cross section of the XVI-XVI cutting line of FIG. FIG. 17 is a diagram showing a main part of the gate insulating film. FIG. 18 is an enlarged view of the area surrounded by the broken line XVIII of FIG. FIG. 19 is a diagram showing a cross section of the XIX-XIX cutting line of FIG. FIG. 20 is a diagram showing a flow of a method for manufacturing the semiconductor device. 21A to 21D are cross-sectional views for explaining a process related to the formation of the gate insulating film. FIG. 22 is a diagram showing a breakdown waveform between the gate and the source. FIG. 23 is a diagram for explaining the breakdown mechanism of the bidirectional Zener diode according to the first embodiment. FIG. 24 is a diagram for explaining the breakdown mechanism of the bidirectional Zener diode according to the second embodiment. FIG. 25 is a diagram for comparing the breakdown waveforms of the avalanche design and the punch-through design. FIG. 26 is a diagram for explaining how the breakdown voltage BVgss and electrostatic breakdown tolerance between the gate and the source change with respect to the design dimensions ^{of the p-type layer of the bidirectional Zener diode.} FIG. 27 is a diagram showing the relationship between the area of the active region and the electrostatic breakdown resistance for each transistor having a different structure from each other.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1 is a plan view showing a semiconductor device 1 according to the first embodiment of the present invention.
The semiconductor device 1 according to the present embodiment is a composite type semiconductor device including an insulated gate type field effect transistor Tr and a bidirectional Zener diode D integrally. The bidirectional Zener diode D is formed as a protection element that protects the insulated gate type field effect transistor Tr from, for example, overvoltage and overcurrent.

With reference to FIG. 1, the semiconductor device 1 includes a semiconductor layer 2. The semiconductor layer 2 includes a first main surface 3, a second main surface 4 located on the opposite side of the first main surface 3, and a side surface 5 connecting the first main surface 3 and the second main surface 4. The semiconductor layer 2 is formed in a rectangular chip shape in a plan view (hereinafter, simply referred to as “plan view”) viewed from the normal direction of the first main surface 3.
The semiconductor layer 2 is set with an element forming region 6 and an outer region 7 which is an outer region of the element forming region 6. The element forming region 6 is a region in which the insulated gate type field effect transistor Tr and the bidirectional Zener diode D are formed.

In the present embodiment, the element forming region 6 is set in a planar view square shape having four sides parallel to each side of the semiconductor layer 2 in a plan view. The element forming region 6 is set at a distance from the peripheral edge of the semiconductor layer 2 to the inside of the semiconductor layer 2. In the present embodiment, the outer region 7 is set in an endless shape (square ring in a plan view) in the region between the side wall of the semiconductor layer 2 and the peripheral edge of the element forming region 6 so as to surround the element forming region 6. ..

A surface electrode 8 is formed on the first main surface 3 of the semiconductor layer 2. The surface electrode 8 may contain, for example, copper, an alloy containing copper, aluminum, or at least one of alloys containing aluminum. The surface electrode 8 may contain, for example, an aluminum-copper alloy (Al-Cu alloy) or an aluminum-silicon-copper alloy (Al-Si-Cu alloy).

The surface electrode 8 includes a gate pad 9, a gate finger 10, and a source pad 11. The gate pad 9 and the gate finger 10 form a gate electrode of an insulated gate type field effect transistor Tr. The source pad 11 forms the source electrode of the insulated gate type field effect transistor Tr.
The gate pad 9 is formed along one corner portion connecting the two side surfaces 5 of the semiconductor layer 2 in a plan view. The gate pad 9 is formed in a rectangular shape in a plan view. The gate finger 10 is integrally formed with the gate finger 10. The gate finger 10 is formed in the outer region 7 along the periphery of the element forming region 6. The gate finger 10 is formed in an endless shape (square ring in a plan view) surrounding the element forming region 6.

An insulating region 12 is formed in the region surrounded by the gate pad 9 and the gate finger 10. The insulating region 12 extends along the inner edge of the gate pad 9 and the inner edge of the gate finger 10 to electrically separate the gate pad 9 and the source pad 11. The source pad 11 is formed in an L-shape in a plan view in the region surrounded by the insulating region 12.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG.
With reference to FIG. 2, the semiconductor layer 2 includes an n ⁺ type semiconductor substrate 21 ^{made of silicon and an n −} type epitaxial layer 22 formed on the main surface of ^{the n + type semiconductor substrate 21.} n ^- type by epitaxial layer 22, the first major surface 3 of the semiconductor layer 2 is formed by n ⁺ -type semiconductor substrate 21 and the second major surface 4 of the semiconductor layer 2 is formed.

The n-type impurity concentration of the n ⁺ type semiconductor substrate 21 is, for example, 1.0 × 10 ¹⁹ cm ^-3 or more and 1.0 × 10 ²⁰ cm ^-3 or less. n ^- n-type impurity concentration of the type epitaxial layer 22 is 1.0 × ¹⁰ 17 ^{cm -3} or less for example 1.0 × ¹⁰ 15 ^{cm -3} or more.
A drain electrode 23 is connected to the second main surface 4 of the semiconductor layer 2. As a result, the n ⁺ type semiconductor substrate 21 is ^{formed as the n +} type drain region 24, and the n ⁻ type epitaxial layer 22 is ^{formed as the n −} type drift drain region 25. As the electrode material of the drain electrode 23, the same electrode material as that of the surface electrode 8 can be applied.

A trench gate structure 27 is formed in the element forming region 6 directly below the source pad 11. The trench gate structure 27 partitions the unit cell 26 of the insulated gate type field effect transistor Tr. The trench gate structure 27 includes a gate trench 28, a first inner wall insulating film 29, and an embedded gate electrode 30. In the trench gate structure 27, the first inner wall insulating film 29 is formed as a gate insulating film.

The gate trench 28 is formed on the first main surface 3 of the semiconductor layer 2. The gate trench 28 may be formed in a plan view stripe shape or may be formed in a plan view grid shape. The cell pitch P of the unit cell 26 defined by the distance between the adjacent gate trenches 28 is, for example, 1.0 μm or more and 2.0 μm or less. The gate trench 28 has an inner wall including a side wall and a bottom wall.

The first inner wall insulating film 29 is formed along the inner wall of the gate trench 28. The embedded gate electrode 30 is embedded in the gate trench 28 with the first inner wall insulating film 29 interposed therebetween. The first inner wall insulating film 29 may contain _{silicon oxide (SiO 2).} The embedded gate electrode 30 may contain polysilicon having conductivity.
Although not shown, the trench gate structure 27 is electrically connected to the gate finger 10 in the outer region 7. Power is supplied to the unit cell 26 by the trench gate structure 27.

FIG. 3 is a diagram showing a main part of the trench gate structure 27.
With reference to FIG. 3, the first inner wall insulating film 29 integrally includes a first side wall insulating film 31, a first bottom wall insulating film 32, and a first connection insulating film 33. The first side wall insulating film 31 is formed along the side wall of the gate trench 28. The first bottom wall insulating film 32 is formed along the bottom wall of the gate trench 28. The first connection insulating film 33 is formed along a connection portion connecting the side wall and the bottom wall of the gate trench 28.

The thickness t1 of the first bottom wall insulating film 32 is larger than the thickness t2 of the first side wall insulating film 31 (thickness t2 <thickness t1). The thickness t3 of the first connection insulating film 33 is equal to or less than the thickness t2 of the first side wall insulating film 31 (thickness t3 ≦ thickness t2 <thickness t1).
The ratio t1 / Dg of the thickness t1 of the first bottom wall insulating film 32 to the depth Dg of the gate trench 28 is, for example, 0.08 or more and 0.35 or less. The ratio t2 / t1 of the thickness t2 of the first side wall insulating film 31 to the thickness t1 of the first bottom wall insulating film 32 is, for example, 0.16 or more and 0.6 or less.

The depth Dg of the gate trench 28 is, for example, 9000 Å or more and 12000 Å or less (about 10000 Å in this embodiment). The thickness t1 of the first bottom wall insulating film 32 is, for example, 1000 Å or more and 3000 Å or less. The thickness t2 of the first side wall insulating film 31 is, for example, 500 Å or more and 600 Å or less. The thickness t3 of the first connection insulating film 33 is, for example, 400 Å or more and 600 Å or less.

With reference to FIG. 2 again, a p-type body region 34 is formed on the surface layer portion of the first main surface 3 of the semiconductor layer 2 on the side of the trench gate structure 27. The p-shaped body region 34 is shared by a trench gate structure 27 adjacent to each other. In the present embodiment, the p-type body region 34 is formed over almost the entire area of the first main surface 3 of the semiconductor layer 2. The impurity concentration of the p-type body region 34 is, for example, 1.0 × 10 ¹⁵ cm ^-3 or more and 1.0 × 10 ¹⁷ cm ^-3 or less.

On the side of the trench gate structure 27, an n ⁺ type source region 35 is formed on the surface layer portion of the p-type body region 34. The n ⁺ type source region 35 is exposed from the first main surface 3 of the semiconductor layer 2. The n-type impurity concentration in the n ⁺ -type source region 35 is higher than the n-type impurity concentration in the n ⁻ -type epitaxial layer 22, for example, 1.0 × 10 ¹⁹ cm ^-3 or more and 1.0 × 10 ²⁰ cm ^-3 or less. be.

On the side of the trench gate structure 27, a p ⁺ type body contact region 36 is formed on the surface layer portion of the p-type body region 34. The p ^{+ type body contact region 36 penetrates the n +} type source region 35 from the first main surface 3 of the semiconductor layer 2 and is connected to the p-type body region 34. The p- ^{type impurity concentration in the p +} type body contact region 36 is higher than the p-type impurity concentration in the p-type body region 34, for example, 1.0 × 10 ¹⁶ cm ^-3 or more and 1.0 × 10 ¹⁷ cm ^-3 or less. be.

On the side of the trench gate structure 27, from the first main surface 3 to the second main surface 4 of the semiconductor layer 2, an n ⁺ type source region 35, a p-type body region 34, and an n ⁻ type epitaxial layer 22 (n). ^{The −} type drift drain region 25) is formed in order.
^{The embedded gate electrode 30 faces the n +} type source region 35, the p-type body region 34, and the n ⁻ type epitaxial layer 22 with the first side wall insulating film 31 interposed therebetween. In p-type body region 34, n ⁺ -type source region 35 and the n ^- region between -type epitaxial layer 22 is a channel of an insulated gate field effect transistor Tr.

An insulating layer 40 that covers the trench gate structure 27 is formed on the first main surface 3 of the semiconductor layer 2. The insulating layer 40 may have a laminated structure in which a plurality of insulating films are laminated, or may have a single-layer structure including only one insulating film. The insulating layer 40 may contain, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiN).
A source contact hole 41 is formed in the insulating layer 40. The source contact hole 41 ^{exposes the n +} type source region 35 and the p-type body region 34 from the insulating layer 40.

The source pad 11 described above is formed on the insulating layer 40. The source pad 11 enters the source contact hole 41 from above the insulating layer 40. The source pad 11 is ^{connected to the n +} type source region 35 and the p ⁺ type body contact region 36 at the source contact hole 41.
FIG. 4 is an enlarged view of the region surrounded by the alternate long and short dash line IV of FIG. FIG. 5 is a cross-sectional view taken along the line VV of FIG. In FIG. 4, for convenience of explanation, the gate pad 9 and the source pad 11 are shown by a broken line, and the layout of the first main surface 3 of the semiconductor layer 2 is shown by a solid line.

With reference to FIGS. 4 and 5, a trench diode structure 45 is formed in the element forming region 6 directly below the gate pad 9. The trench diode structure 45 includes a diode trench 46, a second inner wall insulating film 47, and a bidirectional Zener diode D.
The diode trench 46 is formed on the main surface of the semiconductor layer 2. The diode trench 46 is drawn out from the region directly below the gate pad 9 to the region directly below the source pad 11. In the present embodiment, the diode trench 46 is formed in a rectangular shape in a plan view.

The diode trench 46 has a depth Dd substantially equal to the depth Dg of the gate trench 28. Therefore, the depth Dd of the diode trench 46 is, for example, 9000 Å or more and 12000 Å or less (about 10000 Å in this embodiment).
The diode trench 46 has one end located in the region directly below the gate pad 9 and the other end located in the region directly below the source pad 11. The diode trench 46 has an inner wall including a side wall and a bottom wall.

The second inner wall insulating film 47 is formed along the inner wall of the diode trench 46. The bidirectional Zener diode D is embedded in the diode trench 46 with the second inner wall insulating film 47 interposed therebetween.
FIG. 6 is a diagram showing a main part of the trench diode structure 45.
With reference to FIG. 6, the second inner wall insulating film 47 has a structure substantially equal to that of the first inner wall insulating film 29. More specifically, the second inner wall insulating film 47 integrally includes the second side wall insulating film 48, the second bottom wall insulating film 49, and the second connection insulating film 50. The second side wall insulating film 48 is formed along the side wall of the diode trench 46. The second bottom wall insulating film 49 is formed along the bottom wall of the diode trench 46. The second connection insulating film 50 is formed along the connection portion connecting the side wall and the bottom wall of the diode trench 46.

The thickness t4 of the second bottom wall insulating film 49 is larger than the thickness t5 of the second side wall insulating film 48 (thickness t5 <thickness t4). The thickness t6 of the second connection insulating film 50 is equal to or less than the thickness t5 of the second side wall insulating film 48 (thickness t6 ≦ thickness t5 <thickness t4).
The ratio t4 / Dd of the thickness t4 of the second bottom wall insulating film 49 to the depth Dd of the diode trench 46 is, for example, 0.08 or more and 0.35 or less. The ratio t5 / t4 of the thickness t5 of the second side wall insulating film 48 to the thickness t4 of the second bottom wall insulating film 49 is, for example, 0.16 or more and 0.6 or less.

In the present embodiment, the thickness t4 of the second bottom wall insulating film 49 is substantially equal to the thickness t1 of the first bottom wall insulating film 32 (thickness t4 = thickness t1 or thickness t4 ≈ thickness t1). ). In the present embodiment, the thickness t5 of the second side wall insulating film 48 is substantially equal to the thickness t2 of the first side wall insulating film 31 (thickness t5 = thickness t2, or thickness t5 ≈ thickness t2). In the present embodiment, the thickness t6 of the second connecting insulating film 50 is substantially equal to the thickness t3 of the first connecting insulating film 33 (thickness t6 = thickness t3, or thickness t6 ≈ thickness t3).

With reference to FIGS. 4 and 5 again, the bidirectional Zener diode D is formed on the second bottom wall insulating film 49 in the diode trench 46. In the present embodiment, the bidirectional Zener diode D is formed in a rectangular shape in a plan view extending along the diode trench 46. The bidirectional Zener diode D has one end located in the region directly below the gate pad 9 and the other end located in the region directly below the source pad 11.

The bidirectional Zener diode D has a flat top surface 51 facing the opening of the diode trench 46. The upper surface 51 of the bidirectional Zener diode D is formed substantially parallel to the bottom wall of the diode trench 46.
With respect to the normal direction of the first main surface 3 of the semiconductor layer 2, the distance between the first main surface 3 of the semiconductor layer 2 and the bottom wall of the diode trench 46 is the distance between the upper surface 51 of the bidirectional Zener diode D and the diode trench 46. It is almost equal to the distance between the bottom walls. Therefore, the upper surface 51 of the bidirectional Zener diode D is formed on the same plane as the first main surface 3 of the semiconductor layer 2.

The bidirectional Zener diode D is formed at a distance from the side wall of the diode trench 46. The side wall of the bidirectional Zener diode D is formed in the region surrounded by the side wall of the diode trench 46. The distance between the side wall of the bidirectional Zener diode D and the side wall of the diode trench 46 is larger than the thickness of the bidirectional Zener diode D.

The bidirectional Zener diode D includes an n ⁺ mold portion 52 (first conductive mold portion) and a p-type portion 53 (second conductive mold portion), and the n ⁺ mold portion 52 and the p-type portion 53 are alternately repeated. It has a structure. The n ⁺ mold portion 52 is formed at one end and the other end of the bidirectional Zener diode D, respectively. ^{N +} mold portions 52 and p mold portions 53 are alternately and repeatedly formed in a region between ^{a pair of n +} mold portions 52 formed at both ends of the bidirectional Zener diode D.

In ^{the present embodiment, the n +} type portion 52 and the p-type portion 53 are formed in a band shape extending along an intersecting direction in which the diode trench 46 intersects in the extending direction in a plan view. As a result, the n ⁺ mold portion 52 and the p-type portion 53 are formed in a striped shape extending along the crossing direction. The crossing direction may be an orthogonal direction orthogonal to the direction in which the diode trench 46 extends.

A ^{pn junction is formed in the region between the n +} type portion 52 and the p type portion 53. The pn junction ^{forms Zener diodes DZ1 and DZ2 having the n +} type portion 52 as the cathode and the p-type portion 53 as the anode.
The bidirectional Zener diode D includes a plurality of (four in this embodiment) bidirectional Zener diode elements DE. The bidirectional Zener diode element DE includes a pair of Zener diodes DZ1 and DZ2 electrically connected to each other via an anode (p-type portion 53).

Bidirectional Zener diode elements DE adjacent to each other are ^{electrically connected via a cathode (n +} mold portion 52). In the present embodiment, one bidirectional Zener diode D is formed by such a plurality of bidirectional Zener diode elements DE.
The bidirectional Zener diode D may have a structure including only one bidirectional Zener diode element DE. Therefore, the bidirectional Zener diode D may have at least one p-type portion 53 formed between ^{the pair of n +} mold portions 52 and the pair of n ^{+ mold portions 52.}

The bidirectional Zener diode D includes a polysilicon body 54 in this embodiment. In ^{the present embodiment, the n + type portion 52 includes an n +} type impurity region formed by selectively injecting an n-type impurity into the polysilicon body 54. In the present embodiment, the p-type portion 53 includes a p-type impurity region formed by selectively injecting p-type impurities into the polysilicon body 54.
The n ⁺ type portion 52 may have an n-type impurity concentration substantially equal to the n-type impurity concentration in ^{the n + type source region 35.} The p-type portion 53 may have a p-type impurity concentration substantially equal to the p-type impurity concentration in the p-type body region 34.

With reference to FIG. 5, a p-type floating region 55 is formed in the region of the semiconductor layer 2 along the bottom wall of the diode trench 46. The p-type floating region 55 is formed along a part of the side wall of the diode trench 46 in addition to the bottom wall of the diode trench 46. The p-shaped floating region 55 also covers the corners connecting the side walls and the bottom wall of the diode trench 46. The p-type impurity concentration in the p-type floating region 55 is, for example, 1.0 × 10 ¹⁵ cm ^-3 or more and 1.0 × 10 ¹⁷ cm ^-3 or less.

In the present embodiment, the second bottom wall insulating film 49 is interposed between the bottom wall of the diode trench 46 and the bidirectional Zener diode D. In addition, the semiconductor layer 2 is formed with a p-type floating region 55 facing the bidirectional Zener diode D with the second bottom wall insulating film 49 interposed therebetween. The second bottom wall insulating film 49 and the p-type floating region 55 form a reversal suppression structure 56 that suppresses the reversal of the conductive type of the p-type portion 53 of the bidirectional Zener diode D into an n-type.

With reference to FIG. 5, an insulating side wall protective film 57 is formed on the side wall of the bidirectional Zener diode D. The side wall protective film 57 fills the area between the side wall of the bidirectional Zener diode D and the side wall of the diode trench 46. The side wall protective film 57 protects the bidirectional Zener diode D from the side wall side. Further, the side wall protective film 57 enhances the insulating property between the bidirectional Zener diode D and the semiconductor layer 2 in the lateral direction parallel to the first main surface 3 of the semiconductor layer 2.

With reference to FIGS. 4 and 5, in the element forming region 6, an electric field relaxation structure 61 for relaxing the electric field in the peripheral region is formed in the peripheral region along the peripheral edge of the diode trench 46. In the present embodiment, the electric field relaxation structure 61 includes a plurality of (four in this embodiment) electric field relaxation structures 61A, 61B, 61C, 61D formed in this order at intervals in the direction away from the diode trench 46.

The electric field relaxation structures 61A, 61B, 61C, 61D are formed so as to surround the diode trench 46. The electric field relaxation structures 61A, 61B, 61C, 61D include an electric field relaxation trench 62, a third inner wall insulating film 63, an embedded conductor 64, and a p-type floating region 65, respectively.
The electric field relaxation trench 62 is formed on the first main surface 3 of the semiconductor layer 2. In the present embodiment, the electric field relaxation trench 62 is formed in a planar view endless shape (planar view square ring) surrounding the diode trench 46.

The electric field relaxation trench 62 has a depth Dg substantially equal to the depth Dg of the gate trench 28 and the depth of the diode trench 46. Therefore, the depth De of the electric field relaxation trench 62 is, for example, 9000 Å or more and 12000 Å or less (about 10000 Å in this embodiment). The electric field relaxation trench 62 has an inner wall including a side wall and a bottom wall.
The third inner wall insulating film 63 is formed along the inner wall of the electric field relaxation trench 62. The embedded conductor 64 is embedded in the electric field relaxation trench 62 with the third inner wall insulating film 63 interposed therebetween. The third inner wall insulating film 63 may contain silicon oxide. The embedded conductor 64 may contain polysilicon having conductivity.

FIG. 7 is a diagram showing a main part of the electric field relaxation structure 61.
The third inner wall insulating film 63 has a structure substantially equal to that of the first inner wall insulating film 29 and the second inner wall insulating film 47. More specifically, the third inner wall insulating film 63 integrally includes the third side wall insulating film 66, the third bottom wall insulating film 67, and the third connection insulating film 68.
The third side wall insulating film 66 is formed along the side wall of the electric field relaxation trench 62. The third bottom wall insulating film 67 is formed along the bottom wall of the electric field relaxation trench 62. The third connection insulating film 68 is formed along the connection portion connecting the side wall and the bottom wall of the electric field relaxation trench 62.

The thickness t7 of the third bottom wall insulating film 67 is larger than the thickness t8 of the third side wall insulating film 66 (thickness t7 <thickness t8). The thickness t9 of the third connection insulating film 68 is equal to or less than the thickness t8 of the third side wall insulating film 66 (thickness t9 ≦ thickness t8 <thickness t7).
The ratio t7 / De of the thickness t7 of the third bottom wall insulating film 67 to the depth De of the electric field relaxation trench 62 is, for example, 0.08 or more and 0.35 or less. The ratio t8 / t7 of the thickness t8 of the third side wall insulating film 66 to the thickness t7 of the third bottom wall insulating film 67 is, for example, 0.16 or more and 0.6 or less.

In the present embodiment, the thickness t7 of the third bottom wall insulating film 67 is substantially equal to the thickness t4 of the second bottom wall insulating film 49 (thickness t7 = thickness t4, or thickness t7 ≈ thickness t4). ). In the present embodiment, the thickness t8 of the third side wall insulating film 66 is substantially equal to the thickness t5 of the second side wall insulating film 48 (thickness t8 = thickness t5, or thickness t8 ≈ thickness t5). In the present embodiment, the thickness t9 of the third connecting insulating film 68 is substantially equal to the thickness t6 of the second connecting insulating film 50 (thickness t9 = thickness t6, or thickness t9 ≈ thickness t6).

With reference to FIG. 5 again, the p-type floating region 65 is formed in the semiconductor layer 2 along the bottom wall of the electric field relaxation trench 62. The p-type floating region 65 is formed along a part of the side wall of the electric field relaxation trench 62 in addition to the bottom wall of the electric field relaxation trench 62. Therefore, the p-type floating region 65 also covers the corner portion connecting the side wall and the bottom wall of the electric field relaxation trench 62.

The p-type floating region 65 may have a p-type impurity concentration substantially equal to the p-type impurity concentration of the p-type floating region 55 on the diode trench 46 side. Further, the p-type floating region 65 may be formed at a depth substantially equal to the depth of the p-type floating region 55. The p-type floating region 65 can relax the electric field at the bottom of the electric field relaxation trench 62, particularly at the corner of the electric field relaxation trench 62.

The number and shape of the electric field relaxation structure 61 can be appropriately changed according to the electric field to be relaxed. Therefore, a structure in which only one electric field relaxation structure 61 is formed may be adopted, or a structure in which eight or more electric field relaxation structures 61 are formed may be adopted. Further, a dot-shaped or line-shaped intermittent electric field relaxation structure 61 may be formed so as to surround the peripheral edge of the diode trench 46.

The trench diode structure 45 and the electric field relaxation structure 61 are covered with the above-mentioned insulating layer 40. The side wall protective film 57 formed in the trench diode structure 45 may be formed by a part of the insulating layer 40. The insulating layer 40 is formed with a first contact hole 71 and a second contact hole 72.
^{The first contact hole 71 exposes one end (n +} mold portion 52) of the bidirectional Zener diode D located directly below the gate pad 9. The bottom of the first contact hole 71 may be located in one end of the bidirectional Zener diode D.

^{The second contact hole 72 exposes the other end (n +} mold portion 52) of the bidirectional Zener diode D located directly below the source pad 11. The bottom of the second contact hole 72 may be located in the other end of the bidirectional Zener diode D.
A first contact plug 73 is embedded in the first contact hole 71. ^{The first contact plug 73 is electrically connected to one end (n +} mold portion 52) of the gate pad 9 and the bidirectional Zener diode D. The first contact plug 73 may contain tungsten (W).

A second contact plug 74 is embedded in the second contact hole 72. The second contact plug 74 is electrically connected to the other end (p-type portion 53) of the source pad 11 and the bidirectional Zener diode D. The second contact plug 74 may contain tungsten (W).
Next, an example of the manufacturing method of the semiconductor device 1 will be described. 8A to 8M are cross-sectional views for explaining the manufacturing method of the semiconductor device 1 of FIG. 8A to 8M are cross-sectional views of a portion corresponding to FIG. 5 described above. 8A to 8M mainly focus on the trench diode structure 45 and the surrounding structure.

^{First, the n +} type semiconductor substrate 21 is prepared with reference to FIG. 8A. Next, silicon is epitaxially grown from the main surface of the semiconductor substrate 21 while the n-type impurities are introduced. Thus, n on the major surface of the n ⁺ -type semiconductor substrate 21 ^- -type epitaxial layer 22 is formed. The semiconductor layer 2 is formed by a laminated structure including an ^{n +} type semiconductor substrate 21 and an n ^{− type epitaxial layer 22.} The semiconductor layer 2 has a first main surface 3 and a second main surface 4.

Next, with reference to FIG. 8B, the mask 81 is formed on the first main surface 3 of the semiconductor layer 2. The mask 81 may be a silicon oxide film formed by selectively oxidizing the first main surface 3 of the semiconductor layer 2. The mask 81 selectively has an opening 82 that exposes a region to form a gate trench 28, a diode trench 46, and an electric field relaxation trench 62.
Next, the unnecessary portion of the semiconductor layer 2 is selectively removed by etching via the mask 81. As a result, the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 are formed on the first main surface 3 of the semiconductor layer 2.

Next, with reference to FIG. 8C, p-type impurities are introduced into the semiconductor layer 2 exposed from the bottom of the diode trench 46 and the electric field relaxation trench 62. The p-type impurities are implanted into the semiconductor layer 2 through, for example, an ion implantation mask (not shown). As a result, the p-type floating region 55 along the bottom of the diode trench 46 is formed, and the p-type floating region 65 along the bottom of the electric field relaxation trench 62 is formed.

Next, with reference to FIG. 8D, the insulating material layer 83 is formed by, for example, a CVD (Chemical Vapor Deposition) method. The insulating material layer 83 is formed so as to fill the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 and cover almost the entire area of the first main surface 3 of the semiconductor layer 2.
Next, referring to FIG. 8E, the etch back removes unnecessary portions of the insulating material layer 83 up to the middle of the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 in the depth direction. As a result, the first bottom wall insulating film 32, the second bottom wall insulating film 49, and the third bottom wall insulating film 67 are formed.

Next, referring to FIG. 8F, the semiconductor layer 2 exposed from the side wall of the gate trench 28, the side wall of the diode trench 46, and the side wall of the electric field relaxation trench 62 is oxidized by, for example, a thermal oxidation method or a wet oxidation method. As a result, the first side wall insulating film 31, the second side wall insulating film 48, and the third side wall insulating film 66 are formed. Further, as a result, the first connection insulating film 33, the second connection insulating film 50, and the third connection insulating film 68 are formed.

Next, with reference to FIG. 8G, the polysilicon layer 84 is formed, for example, by the CVD method. The polysilicon layer 84 is formed so as to fill the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 and cover almost the entire area of the first main surface 3 of the semiconductor layer 2.
Next, a mask 86 is formed in the polysilicon layer 84 that selectively covers the flat region 85 located in the diode trench 46. A step portion 87 is formed between the polysilicon layer 84 formed in the diode trench 46 and the polysilicon layer 84 formed on the first main surface 3 of the semiconductor layer 2. The flat region 85 refers to a flat region surrounded by a step portion 87 in the polysilicon layer 84 located in the diode trench 46.

Next, with reference to FIG. 8H, the unnecessary portion of the polysilicon layer 84 is removed by etchback via the mask 86. As a result, the embedded gate electrode 30 is formed in the first bottom wall insulating film 32. Further, a polysilicon body 54, which is a base of the bidirectional Zener diode D, is formed in the diode trench 46. Further, the embedded conductor 64 is formed in the electric field relaxation trench 62.

In this step, a polysilicon body 54 having a flat upper surface 51 facing the opening of the diode trench 46 is formed. With respect to the normal direction of the first main surface 3 of the semiconductor layer 2, the distance between the first main surface 3 of the semiconductor layer 2 and the bottom wall of the diode trench 46 is the distance between the upper surface 51 of the polysilicon body 54 and the bottom of the diode trench 46. Approximately equal to the distance between the walls. Therefore, the upper surface 51 of the polysilicon body 54 is formed on a plane substantially the same as the first main surface 3 of the semiconductor layer 2.

Further, in this step, the polysilicon body 54 is formed in the diode trench 46 at a distance from the side wall of the diode trench 46. The side wall of the polysilicon body 54 is formed in the region surrounded by the side wall of the diode trench 46. The distance between the side wall of the polysilicon body 54 and the side wall of the diode trench 46 is formed to be larger than the thickness of the polysilicon body 54.

As a result, the stepped portion 87 existing between the polysilicon layer 84 formed on the first main surface 3 of the semiconductor layer 2 and the polysilicon layer 84 formed in the diode trench 46 can be removed. Therefore, since it is possible to prevent the stepped portion 87 from remaining as a part of the polysilicon body 54, it is possible to form the bidirectional Zener diode D having a flat upper surface 51.

Next, with reference to FIG. 8I, a photomask 88 is formed on the first main surface 3 of the semiconductor layer 2. The photomask 88 may be a negative type or a positive type. Here, a negative type photomask 88 will be described as an example.
Next, the photomask 88 has an opening 89 that exposes the region where the p-type body region 34 should be formed by exposure and development, and an opening 90 that exposes the region where the p-type portion 53 of the polysilicon body 54 should be formed. Is selectively formed in.

Next, the p-type impurities are injected into the surface layer portion of the first main surface 3 of the semiconductor layer 2 and the entire area of the polysilicon body 54 via the photomask 88. The p-type impurities injected into the surface layer portion of the first main surface 3 of the semiconductor layer 2 become the p-type body region 34. The p-type impurities injected into the polysilicon body 54 become the p-type portion 53 through the steps described below. After the p-type impurities are injected, the photomask 88 is removed.

Here, consider a case where the photomask 88 has a relatively large step between the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. ..
When the photomask 88 is exposed, different focus margins must be set for the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. Must be. Therefore, it is not realistic to expose the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2 in the same process.

The focus margin is the width of the depth region in which the photomask can be maintained in a practical state when the focus of light on the photomask shifts upward or downward from the optimum focal position during exposure.
On the other hand, in the present embodiment, the upper surface 51 of the polysilicon body 54 is formed on substantially the same plane as the first main surface 3 of the semiconductor layer 2. Therefore, in the photomask 88, it is possible to suppress the formation of a step between the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. Moreover, since the upper surface 51 of the polysilicon body 54 is formed flat, it is possible to suppress the formation of a step on the photomask 88 on the upper surface 51 of the polysilicon body 54.

Therefore, when the photomask 88 is exposed, equal focus margins are set for the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. be able to.
Thereby, the step of forming the p-type body region 34 and the step of forming the p-type portion 53 of the polysilicon body 54 can be made common. At the same time, it is possible to simplify the process of forming the p-type portion 53 with respect to the polysilicon body 54 formed in the diode trench 46.

Next, with reference to FIG. 8J, another photomask 91 is formed on the first main surface 3 of the semiconductor layer 2. The photomask 91 may be a negative type or a positive type. Here, a negative type photomask 91 will be described as an example.
^{Next, an opening (not shown) that exposes the region where the n +} type source region 35 should be formed by exposure and development, and an opening 92 that exposes the region where the p-type portion 53 of the polysilicon body 54 should be formed are exposed. Is selectively formed on the photomask 91.

Next, the n-type impurities are injected into the surface layer portion of the first main surface 3 of the semiconductor layer 2 and the polysilicon body 54 via the photomask 91. The n-type impurities injected into the surface layer portion of the first main surface 3 of the semiconductor layer 2 ^{become the n +} type source region 35. The n-type impurities injected into the polysilicon body 54 ^{become the n +} mold portion 52.
This step includes an n ⁺ 52 and the p-type portion 53, the bidirectional Zener diode D of the n ⁺ -type portion 52 and the p-type portion 53 are repeated alternately structure is formed in the diode trench 46 .. After the n-type impurities are injected, the photomask 91 is removed.

In this step, it is possible to prevent the photomask 91 from forming a step between the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. Moreover, since the upper surface 51 of the polysilicon body 54 is formed flat, it is possible to suppress the formation of a step on the photomask 91 on the upper surface 51 of the polysilicon body 54.

Therefore, when the photomask 91 is exposed, equal focus margins are set for the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. be able to.
Thereby, the ^{step of forming the n +} type source region 35 and the step of forming the n ⁺ type portion 52 of the polysilicon body 54 can be shared. At the same time, it is possible to simplify the process of forming the ^{n +} mold portion 52 with respect to the polysilicon body 54 formed in the diode trench 46.

Next, referring to FIG. 8K, the insulating layer 40 is formed by, for example, the CVD method. The insulating layer 40 is formed so as to fill the region between the side wall of the polysilicon body 54 and the side wall of the diode trench 46 and cover almost the entire area of the first main surface 3 of the semiconductor layer 2. The portion of the insulating layer 40 that fills the area between the side wall of the polysilicon body 54 and the side wall of the diode trench 46 becomes the side wall protective film 57 that protects the side wall of the polysilicon body 54.

Next, with reference to FIG. 8L, a mask 93 is formed on the insulating layer 40. The mask 93 has an opening 94 that selectively exposes the region where the first contact hole 71 and the second contact hole 72 should be formed.
Next, the unnecessary portion of the insulating layer 40 is removed by etching via the mask 93. As a result, the first contact hole 71 that exposes one end of the polysilicon body 54 and the second contact hole 72 that exposes the other end of the polysilicon body 54 are formed in the insulating layer 40. After the first contact hole 71 and the second contact hole 72 are formed, the mask 93 is removed.

Next, with reference to FIG. 8M, tungsten is embedded in the first contact hole 71 and the second contact hole 72 by, for example, a CVD method and etch back. As a result, the first contact plug 73 is formed in the first contact hole 71. Further, as a result, the second contact plug 74 is formed in the second contact hole 72.
Next, for example, by a sputtering method, an electrode material (for example, aluminum) is deposited on the insulating layer 40 to form an electrode material layer. The unwanted portion of the electrode material layer is then removed, for example by etching through a mask (not shown). As a result, the surface electrode 8 including the gate pad 9, the gate finger 10, and the source pad 11 is formed. After that, for example, the drain electrode 23 is formed on the second main surface 4 of the semiconductor layer 2 by a sputtering method. Through the above steps, the semiconductor device 1 is obtained.

Next, the operation of the bidirectional Zener diode D will be described. Here, two bidirectional Zener diodes D in which the width Wp of the p-type portion 53 is adjusted are prepared, and the operation of each is investigated.
9 and 10 are diagrams for explaining the operation of the bidirectional Zener diode D, respectively. 9 and 10, respectively, show the operation when the bidirectional Zener diode D is broken down by the avalanche breakdown.

In the bidirectional Zener diode D of FIG. 9, the width Wp of the p-type portion 53 is larger than the width Wd of the depletion layer extending from the pn junction formed between ^{the n + mold portion 52 and the p-type portion 53 (} Width Wp> Width Wd) is set. The width Wd of the depletion layer is the width of the depletion layer that expands from the pn junction when a breakdown voltage is applied between the gate pad 9 and the source pad 11.

With reference to FIG. 9, when a breakdown voltage is applied between the gate pad 9 and the source pad 11, the avalanche breakdown causes the bidirectional Zener diode D to conduct. Then, a gate current including a noise component flows between the gate pad 9 and the source pad 11 via the bidirectional Zener diode D.
The width Wp of the p-type portion 53 is set to a value larger than the width Wd of the depletion layer (width Wp> width Wd). Therefore, in the breakdown state, each p-type portion 53 is not filled with the depletion layer, and a part of the p-type portion 53 remains with a constant width.

Since the remaining portion of the p-type portion 53 becomes a series resistance, it hinders the escape of the gate current to the ground potential (gate pad 9). As a result, inconveniences such as destruction of the gate insulating film occur.
On the other hand, in the bidirectional Zener diode D of FIG. 10, the width Wp of the p-type portion 53 is a value equal to or less than the width Wd of the depletion layer extending from the pn junction formed between ^{the n + mold portion 52 and the p-type portion 53.} It is set to (width Wp ≦ width Wd).

Therefore, when a breakdown voltage is applied between the gate pad 9 and the source pad 11, the region of each p-type portion 53 can be filled with the depletion layer. Thus, the punch-through to the n ⁺ -type portion 52 of the n ⁺ -type portion 52 and the gate of the source side can be conducted by, and it is possible to reduce the series resistance is formed by the p-type portion 53.
In the present embodiment, the inversion suppression structure 56 including the second bottom wall insulating film 49 and the floating region is formed directly under the bidirectional Zener diode D (see FIG. 5). The inversion suppression structure 56 suppresses the inversion of the conductive type of the p-type portion 53 of the bidirectional Zener diode D to n-type. Therefore, it is possible to suppress the formation of an undesired current path between the gate pad 9 and the source pad 11. Therefore, the stability of the on / off operation by the bidirectional Zener diode D can be improved.

As a result, the gate current can be satisfactorily released to the ground potential (gate pad 9). Therefore, it is possible to suppress inconveniences such as breakage of the gate insulating film and improve the resistance to static electricity breakage and the avalanche resistance. The avalanche withstand is the withstand that the bidirectional Zener diode D does not break when the avalanche yields.
As described above, in the semiconductor device 1 according to the present embodiment, the second bottom wall insulating film 49 is interposed between the bottom wall of the diode trench 46 and the bidirectional Zener diode D. The thickness t4 of the second bottom wall insulating film 49 is larger than the thickness t5 of the second side wall insulating film 48.

In addition, the semiconductor layer 2 is formed with a p-type floating region 55 facing the bidirectional Zener diode D with the second bottom wall insulating film 49 interposed therebetween. The second bottom wall insulating film 49 and the floating region form an inversion suppression structure 56 that suppresses the inversion of the conductive type of the p-type portion 53 of the bidirectional Zener diode D to n-type.
As a result, ^{even if a voltage drop occurs between the pair of n +} mold portions 52, it is possible to prevent the conductive mold of the p-type portion 53 from inverting to the n-type. Therefore, in the bidirectional Zener diode D, it is possible to suppress an undesired increase in current such as leakage current. Therefore, since the stability of the on / off operation of the bidirectional Zener diode D can be enhanced, the stability of the on / off operation can contribute to the improvement of the resistance to electrostatic breakdown and the improvement of the avalanche resistance.

Further, in the semiconductor device 1 according to the present embodiment, the bidirectional Zener diode D has an upper surface 51 facing the opening of the diode trench 46, and the upper surface 51 of the bidirectional Zener diode D is the second surface of the semiconductor layer 2. 1 It is formed on the same plane as the main surface 3.
As a result, in the photomask 88 used in the step of forming the p-type body region 34 and the p-type portion 53, the portion covering the upper surface 51 of the polysilicon body 54 and the first main surface 3 of the semiconductor layer 2 are formed. It is possible to suppress the formation of a step between the covering portion and the portion (see FIG. 8I).

Moreover, the upper surface 51 of the polysilicon body 54 is formed flat on the bottom wall of the diode trench 46. As a result, it is possible to prevent the photomask 88 from forming a step on the upper surface 51 of the polysilicon body 54.
Therefore, when the photomask 88 is exposed, equal focus margins are set for the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. be able to. Thereby, the step of forming the p-type body region 34 and the step of forming the p-type portion 53 of the polysilicon body 54 can be made common. At the same time, it is possible to simplify the process of forming the p-type portion 53 with respect to the polysilicon body 54 formed in the diode trench 46.

Further, ^{in the photomask 91 used in the step of forming the n +} type source region 35 and the n ⁺ type portion 52, the portion covering the upper surface 51 of the polysilicon body 54 and the first main surface 3 of the semiconductor layer 2 It is possible to suppress the formation of a step between the portion covering the surface (see FIG. 8J).
Moreover, the upper surface 51 of the polysilicon body 54 is formed flat on the bottom wall of the diode trench 46. As a result, it is possible to suppress the formation of a step on the photomask 91 on the upper surface 51 of the polysilicon body 54.

Therefore, when the photomask 91 is exposed, equal focus margins are set for the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. be able to. Thereby, the ^{step of forming the n +} type source region 35 and the step of forming the n ⁺ type portion 52 of the polysilicon body 54 can be shared. At the same time, it is possible to simplify the process of forming the ^{n +} mold portion 52 with respect to the polysilicon body 54 formed in the diode trench 46.

Further, in the semiconductor device 1 according to the present embodiment, the bidirectional Zener diode D is formed in the diode trench 46 at a distance from the side wall of the diode trench 46. The distance between the side wall of the bidirectional Zener diode D and the side wall of the diode trench 46 is larger than the thickness of the bidirectional Zener diode D.
According to this configuration, in the steps of FIGS. 8G to 8H described above, the polysilicon layer 84 formed on the first main surface 3 of the semiconductor layer 2 and the polysilicon layer 84 formed in the diode trench 46 are formed. The stepped portion 87 existing between them can be removed. As a result, the stepped portion 87 can be prevented from remaining as the polysilicon body 54, so that the bidirectional Zener diode D having a flat upper surface 51 can be formed.

Further, the semiconductor device 1 according to the present embodiment is formed in a region between the side wall of the diode trench 46 and the side wall of the bidirectional Zener diode D, and has an insulating side wall protection that protects the side wall of the bidirectional Zener diode D. Includes membrane 57. The side wall protective film 57 fills the area between the side wall of the diode trench 46 and the side wall of the bidirectional Zener diode D.
According to this configuration, the bidirectional Zener diode D can be protected from the side wall side by the side wall protective film 57. Further, the side wall protective film 57 can enhance the insulating property between the bidirectional Zener diode D and the semiconductor layer 2 in the lateral direction parallel to the first main surface 3 of the semiconductor layer 2. Therefore, the influence of the electric field exerted by the bidirectional Zener diode D on the semiconductor layer 2 can be reduced.

Further, the semiconductor device 1 according to the present embodiment is an electric field relaxation structure 61 formed on the surface layer portion of the main surface of the semiconductor layer 2 in the peripheral region along the peripheral edge of the diode trench 46 and relaxing the electric field in the peripheral region. including.
According to this configuration, the electric field relaxation structure 61 can suppress the concentration of the electric field in the peripheral region along the peripheral edge of the diode trench 46. Therefore, it is possible to suppress a decrease in the resistance to electrostatic breakdown and a decrease in the avalanche withstand due to the concentration of the electric field.

Further, in the semiconductor device 1 according to the present embodiment, the trench gate structure 27, the trench diode structure 45, and the electric field relaxation structure 61 have substantially the same configurations. Therefore, the trench gate structure 27, the trench diode structure 45, and the electric field relaxation structure 61 can be formed in the semiconductor layer 2 by a common process. Therefore, the manufacturing process can be simplified and the man-hours can be reduced.
<Second Embodiment>
FIG. 11 is a cross-sectional view of a portion corresponding to FIG. 5, and is a diagram showing a semiconductor device 95 according to a second embodiment of the present invention. In FIG. 11, the same reference numerals as those described in the above-described first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The semiconductor device 95 according to the present embodiment has the same configuration as the semiconductor device 1 according to the first embodiment described above, except that the p-type floating region 55 along the bottom wall of the diode trench 46 is not provided. ing.
In the semiconductor device 95 according to the present embodiment, the conductive type of the p-type portion 53 of the bidirectional Zener diode D is formed by the second bottom wall insulating film 49 interposed between the bottom wall of the diode trench 46 and the bidirectional Zener diode D. An inversion suppression structure 56 that suppresses inversion to the n-type is formed.

Even with such a configuration, the same action and effect as those described in the above-mentioned first embodiment can be obtained.
<Third Embodiment>
FIG. 12 is a cross-sectional view of a portion corresponding to FIG. 5, and is a diagram showing a semiconductor device 97 according to a third embodiment of the present invention. In FIG. 12, the same reference numerals as those described in the above-described first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The semiconductor device 97 according to the present embodiment is described in the first embodiment described above, except that the thickness t4 of the second bottom wall insulating film 49 is formed to be substantially equal to the thickness t5 of the second side wall insulating film 48. It has the same configuration as the semiconductor device 1 according to the embodiment.
In the semiconductor device 97 according to the present embodiment, the bidirectional Zener diode D is formed by the thin second bottom wall insulating film 49 interposed between the bottom wall of the diode trench 46 and the bidirectional Zener diode D, and the p-type floating region 55. A reversal suppression structure 56 that suppresses the reversal of the conductive type of the p-type portion 53 to the n-type is formed.

Even with such a configuration, the same action and effect as those described in the above-mentioned first embodiment can be obtained.
Although the embodiments of the present invention have been described above, the present invention can also be implemented in other embodiments.
In the above-mentioned first embodiment, ^{an example in which the n +} type portion 52 and the p-type portion 53 are formed in a striped shape in the bidirectional Zener diode D has been described. However, the bidirectional Zener diode D may have a structure as shown in FIG.

FIG. 13 is a cross-sectional view of a portion corresponding to FIG. 4, and is a diagram showing a modified example of the bidirectional Zener diode D. In FIG. 13, the same reference numerals as those described in the above-described first embodiment are designated by the same reference numerals, and the description thereof will be omitted.
In the bidirectional Zener diode D according to this modification, the n ⁺ mold portion 52 at one end is arranged in the center of the inner region of the gate pad 9. The remaining p-shaped portion 53 and the n ⁺ mold portion 52 are arranged concentrically so as to surround the central n ^{+ mold portion 52.} The first contact plug 73 is connected to ^{the n +} mold portion 52 at one end located at the center. Further, the second contact plug 74 is connected to ^{the n +} mold portion 52 at the other end located on the outermost circumference.

With such a structure, toward the n ⁺ -type portion 52 of the one end portion to the n ⁺ -type portion 52 of the other end, two-way with an n ⁺ 52 and the p-type portion 53 are repeated alternately structure A Zener diode D can be obtained. Of course, the bidirectional Zener diode D having such a structure can also be applied in the second embodiment and the third embodiment.
In the above-mentioned first embodiment, an example in which the surface electrode 8 includes a gate pad 9 formed along a corner portion of the semiconductor layer 2 has been described. However, instead of this, the surface electrode 8 having the structure shown in FIG. 14 may be adopted.

FIG. 14 is a plan view showing a modified example of the surface electrode. In FIG. 14, a configuration similar to the configuration described in the first embodiment described above is designated by the same reference numeral, and the description thereof will be omitted. FIG. 14 shows an example in which the semiconductor layer 2 is formed in the shape of a rectangular chip in a plan view.
In the surface electrode 8 according to this modification, the source pad 11 is formed in a rectangular shape in a plan view extending along the longitudinal direction of the semiconductor substrate 21. The source pad 11 is formed with a removal region 99 that extends from one end in the longitudinal direction toward the other end and has an open end at one end and a closed end at the other end. The closed end of the removal area 99 is a pad area 100 wider than the other sections of the removal area 99.

The gate pad 9 is arranged in the pad area 100 of the removal area 99. The gate pad 9 is surrounded by the source pad 11 except for the connection portion with the gate finger 10. The gate finger 10 extends from the gate pad 9 toward the open end of the removal region 99 of the source pad 11. The gate finger 10 is further routed from the open end of the removal region 99 to the outer region 7 (outer circumference of the source pad 11). The gate finger 10 may surround the entire circumference of the source pad 11.

Even with such a structure, the trench diode structure 45 straddling the gate pad 9 and the source pad 11 can be formed in the region directly below the gate pad 9. Of course, the surface electrode 8 having such a structure can also be applied to the second embodiment and the third embodiment.
In each of the above-described embodiments, an example in which the trench gate structure 27, the trench diode structure 45, and the electric field relaxation structure 61 have substantially the same configurations has been described. However, the trench gate structure 27, the trench diode structure 45, and the electric field relaxation structure 61 may have different structures.

For example, the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 may be formed at different depths by forming the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 in separate steps. ..
Further, by forming the first inner wall insulating film 29, the second inner wall insulating film 47, and the third inner wall insulating film 63 in separate steps, the first inner wall insulating film 29, the second inner wall insulating film 47, and the third inner wall insulating film 37 are formed. The inner wall insulating film 63 may be formed with different thicknesses.

Further, at least one of the first inner wall insulating film 29, the second inner wall insulating film 47, and the third inner wall insulating film 63 may be formed to have a uniform thickness.
Further, while the second inner wall insulating film 47 integrally includes the second side wall insulating film 48, the second bottom wall insulating film 49, and the second connection insulating film 50, the first inner wall insulating film 29 and the third inner wall insulating film are insulated. The film 63 may be formed to have a uniform thickness.

Further, the third inner wall insulating film 63 integrally includes the third side wall insulating film 66, the third bottom wall insulating film 67, and the third connection insulating film 68, while the first inner wall insulating film 29 has a uniform thickness. It may be formed of a sword.
Further, in each of the above-described embodiments, a structure in which the conductive type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be n-type and the n-type portion may be p-type.

In addition, various design changes can be made within the scope of the matters described in the claims. Examples of features extracted from this specification and drawings are shown below.
Item 1: A first conductive type semiconductor layer having a main surface, a diode trench formed on the main surface of the semiconductor layer, a pair of first conductive type portions formed in the diode trench, and the pair. A bidirectional Zener diode having at least one second conductive mold portion formed between the first conductive mold portions of the above, intervening between the bidirectional Zener diode and the bottom wall of the diode trench, and the diode trench. A semiconductor device including a bottom wall insulating film in which the ratio of the thickness to the depth of the diode is set to 0.08 or more and 0.35 or less.

In the semiconductor device according to Item 1, a bottom wall insulating film is interposed between the bottom wall of the diode trench and the bidirectional Zener diode. The ratio of the thickness of the bottom wall insulating film to the depth of the diode trench is set to 0.08 or more and 0.35 or less. The bottom wall insulating film forms an inversion suppression structure that suppresses the inversion of the conductive type of the second conductive type portion of the bidirectional Zener diode to the first conductive type.

As a result, even if a voltage drop occurs between the pair of first conductive mold portions, it is possible to prevent the conductive mold of the second conductive mold portion from reversing to the first conductive mold portion. Therefore, it is possible to provide a semiconductor device capable of suppressing an undesired increase in current.
Item 2: The reversal suppressing structure for suppressing the reversal of the conductive type of the second conductive type portion of the bidirectional Zener diode to the first conductive type is formed by the bottom wall insulating film. Semiconductor device.

Item 3: The semiconductor device according to Item 1 or 2, wherein the depth of the diode trench is 9000 Å or more and 12000 Å or less, and the thickness of the bottom wall insulating film is 1000 Å or more and 3000 Å or less.
Item 4: The semiconductor device according to any one of Items 1 to 3, further comprising a side wall insulating film formed along the side wall of the diode trench and having a thickness smaller than the thickness of the bottom wall insulating film. ..

Item 5: The semiconductor device according to Item 4, wherein the ratio of the thickness of the side wall insulating film to the thickness of the bottom wall insulating film is 0.16 or more and 0.6 or less.
<Reference invention>
As a problem different from the above-mentioned "problem to be solved by the invention", in recent years, there has been an increasing demand for transistors satisfying low on-resistance and low capacitance (high-speed switching) in, for example, the in-vehicle market and the industrial machine market. For example, measures are taken to reduce the effective area of each gate electrode and reduce the input capacitance Ciss (= Cgd + Cgs) by reducing the area of the active region of the transistor. However, such a reduction in the capacitance of the transistor, on the contrary, causes a decrease in the electrostatic breakdown resistance of the transistor.

As a countermeasure against electrostatic breakdown, it is common to incorporate a bidirectional Zener diode in the transistor as in Patent Document 1.
However, in the method of avalanche breakdown of a bidirectional Zener diode to allow noise current to escape as in Patent Document 1, for example, ^{a part of the p-} type region remains at a constant width without being depleted even after breakdown. Become. The remaining part of this p ^- type region becomes a series resistance when the noise current flows through the bidirectional Zener diode. Therefore, the noise current is not sufficiently absorbed, and the gate insulating film is likely to be destroyed.

On the other hand, it is possible to consider measures to improve the breaking resistance of the gate insulating film itself by thickening the gate insulating film, but it is difficult to accurately adjust the thickness of the gate insulating film according to the design value of the breaking resistance of the film. .. Further, since the thickness of the gate insulating film is closely related to the switching performance of the transistor, it is not preferable to change the thickness of the gate insulating film unnecessarily.
An object of the reference invention is to provide a semiconductor device capable of achieving a high electrostatic breakdown resistance while having a low on-resistance and a low capacity.

The semiconductor device according to the embodiment of the reference invention includes a semiconductor layer having a first conductive type source region, a second conductive type body region, and a first conductive type drain region, and the body region via a gate insulating film. It has a gate electrode facing the surface, a source electrode connected to the source region, and at least one second conductive mold portion between a pair of first conductive mold portions and the pair of first conductive mold portions at both ends. The pair of first conductive mold portions include the source electrode and the bidirectional Zener diode connected to the gate electrode, respectively, and the second conductive mold portion of the bidirectional Zener diode includes the source electrode and the bidirectional Zener diode. It has a width smaller than the width of the depleted layer extending from the pn junction between the first conductive mold portion and the second conductive mold portion when a predetermined voltage is applied between the gate electrode and the gate electrode.

According to this configuration, the width of the depletion layer generated when a predetermined voltage is applied between the gate and the source> the width of the second conductive mold portion of the bidirectional Zener diode. Therefore, for example, when a voltage due to electrostatic discharge is applied between the gate and the source, the first conductive mold portion of one end of the bidirectional Zener diode is punched through to the first of the other end of the bidirectional Zener diode. It can be made conductive with the conductive mold part. This makes it possible to reduce the series resistance when the current flows after the breakdown, as compared with the structure in which the bidirectional Zener diode yields and conducts the avalanche. As a result, even if a noise current enters the semiconductor device due to electrostatic discharge, the noise current can be satisfactorily released via the bidirectional Zener diode. As a result, a high electrostatic breakdown resistance can be realized, so that on-resistance and capacity can be reduced, for example, by miniaturizing each part of the semiconductor device.

Further, since it is not necessary to increase the thickness of the gate insulating film in order to improve the fracture resistance, the thickness of the gate insulating film can be designed by focusing on the switching performance of the transistor. Therefore, the influence on the switching performance of the transistor can be small.
In the semiconductor device according to the embodiment of the reference invention, the "predetermined voltage" may include, for example, a voltage equal to or higher than the "gate-source rated voltage Vgss" guaranteed for the semiconductor device in circulation. ..

The semiconductor device according to the embodiment of the reference invention may further include a gate trench formed in the semiconductor layer and an embedded insulating film embedded in the bottom of the gate trench. In that case, the source region, the body region, and the drain region are aligned in the depth direction of the gate trench along the side surface of the gate insulating film, and the gate insulating film is continuous with the embedded insulating film. It may be formed on the side surface of the gate trench. The semiconductor device may be arranged at the boundary between the gate insulating film and the embedded insulating film, and may include a thin film portion thinner than the gate insulating film.

As described above, since the semiconductor device according to the embodiment of the reference invention can realize a high electrostatic breakdown resistance, it can be satisfactorily applied to a semiconductor device having a structure in which a thin film portion is arranged in a gate trench. can.
In the semiconductor device according to the embodiment of the reference invention, the bidirectional Zener diode is composed of a polysilicon layer, and the first conductive mold portion and the second conductive mold portion are respectively formed of the polysilicon layer. It may include a first conductive type impurity region and a second conductive type impurity region selectively formed.

The withstand voltage (breakdown voltage) of the bidirectional Zener diode is defined by the width of the second conductive mold portion. Therefore, if the second conductive mold portion is an impurity region in the polysilicon layer as described above, the width of the second conductive mold portion is easily adjusted by the width of the mask when the impurities are injected into the polysilicon layer. Moreover, the width of the second conductive mold portion can be adjusted with high accuracy.
When the bidirectional Zener diode is composed of a polysilicon layer, specifically, the thin film portion has a thickness of 400 Å to 450 Å, and the second impurity region has a thickness of 2.0 × 10 ¹⁶ cm. ^{It may have an impurity concentration of -3 to} 6.0 × 10 ¹⁶ cm ^-3 and a width of 2.4 μm to 2.6 μm.

In the semiconductor device according to the embodiment of the reference invention, in the bidirectional Zener diode, the first conductive mold portion at one end is arranged in the center, and the remaining second conductive mold portion and the first conductive mold portion are formed. It may be arranged concentrically so as to surround the first conductive mold portion in the center.
When the semiconductor device according to the embodiment of the reference invention includes a gate pad connected to the gate electrode and exposed on the outermost surface of the semiconductor device, the bidirectional Zener diode is arranged in a region directly below the gate pad. It may have been done.

According to this configuration, by effectively utilizing the area directly under the gate pad, it is not necessary to secure the space for arranging the bidirectional Zener diode in the outer peripheral area of the chip, which contributes to the miniaturization of the semiconductor device. can.
In the semiconductor device according to the embodiment of the reference invention, the semiconductor layer may include a silicon substrate.

Hereinafter, embodiments of the reference invention will be described in detail with reference to the accompanying drawings.
FIG. 15 is a schematic plan view of the semiconductor device 101 according to the embodiment of the reference invention.
With reference to FIG. 15, the semiconductor device 101 includes a semiconductor substrate 102 as an example of the semiconductor layer of the reference invention, an electrode film 103, and a surface protective film 104. The surface protective film 104 partially covers the electrode film 103, and selectively exposes the source pad 110 and the gate pad 111, which will be described later. As the surface protective film 104, for example, silicon nitride (SiN) or the like can be used.

The semiconductor substrate 102 defines the outer shape of the semiconductor device 101, and has, for example, a rectangular chip shape in a plan view. The semiconductor substrate 102 may be, for example, a silicon substrate, or may be a wide bandgap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) that can be used for power devices.
The electrode film 103 is made of a conductive material such as an aluminum (Al) -based material (for example, AlCu or the like), and includes a source metal 105 and a gate metal 106.

The source metal 105 has a substantially rectangular outer shape in a plan view extending in the longitudinal direction of the semiconductor substrate 102. The source metal 105 is formed with a removal region 107 extending from one end in the longitudinal direction toward the other end, one end being an open end and the other end being a closed end. The closed end of the removal area 107 is a pad area 108 wider than the other sections of the removal area 107. Further, a part of the source metal 105 is exposed to the outermost surface of the semiconductor device 101 as the source pad 110 from the pad opening 109 of the surface protective film 104.

The gate metal 106 includes a gate pad 111 and a gate finger 112.
The gate pad 111 is arranged in the pad region 108 and is exposed to the outermost surface of the semiconductor device 101 from the pad opening 113 of the surface protective film 104. The gate pad 111 is surrounded by the source metal 105 except for the connection portion with the gate finger 112.
On the other hand, the gate finger 112 may be covered with the surface protective film 104 (shown by a solid line in FIG. 15 for clarity). The gate finger 112 extends from the gate pad 111 toward the open end of the removal region 107 of the source metal 105, is further routed from the open end to the peripheral edge of the semiconductor substrate 102, and surrounds the source metal 105. In this embodiment, the entire circumference of the source metal 105 is surrounded by the gate finger 112.

FIG. 16 is a diagram showing a cross section of the semiconductor device 101 at the XVI-XVI cutting line of FIG. FIG. 17 is a diagram showing a main part of the gate insulating film 115 of FIG.
With reference to FIG. 16, the semiconductor device 101 includes a semiconductor substrate 102, a gate trench 114, a gate insulating film 115, a gate electrode 116, a p ^- type body region 117, an n ⁺ -type source region 118, and n. ^{It includes a −} type drain region 119, a p ⁺ type body contact region 120, an interlayer insulating film 121, a source metal 105, and a drain electrode 122.

The semiconductor substrate 102 is, for example, on the n ⁺ -type silicon base substrate 123, n ^- epitaxial layer 124 made of -type silicon or an epitaxial substrate obtained by crystal growth. The impurity concentration of the n ⁺ type base substrate 123 is, for example, 2.0 × 10 ¹⁹ cm ^{-3 to} 7.0 × 10 ¹⁹ cm ^-3 , and ^{the impurity concentration of the n −} type epitaxial layer 124 is, for example, It may be 8.0 × 10 ¹⁵ cm ^{-3 to} 2.0 × 10 ¹⁶ cm ^-3.

The gate trench 114 is formed on the surface portion of the semiconductor substrate 102 in a predetermined pattern. The pattern of the gate trench 114 may be various patterns such as a stripe shape and a grid shape. The surface portion of the semiconductor substrate 102 is partitioned into a plurality of unit cells 125 according to the pattern of the gate trench 114. Further, the distance (cell pitch) between adjacent gate trenches 114 may be, for example, about 1.0 μm to 2.0 μm.

The gate insulating film 115 is formed on the inner surface of the gate trench 114, and will be described in more detail with reference to FIG.
With reference to FIG. 17, an embedded insulating film 126 is arranged inside the gate trench 114 in addition to the gate insulating film 115. Both the gate insulating film 115 and the embedded insulating film 126 may be made of an insulating material such as _{silicon oxide (SiO 2).} The embedded insulating film 126 is embedded from the deepest part of the gate trench 114 to a certain height, and the gate insulating film 115 is arranged on the side surface of the gate trench 114 so as to be connected to the embedded insulating film 126. _{The thickness t 1} of the embedded insulating film 126 in the depth direction of the gate trench 114 may be, for example, 1000 _{Å to 3000 Å, and the thickness t 2} of the gate insulating film 115 may be, for example, 500 Å to 600 Å.

The gate electrode 116 is embedded in a region surrounded by the gate insulating film 115 and the embedded insulating film 126. The gate electrode 116 may be made of a conductive material such as polysilicon.
Further, in this embodiment, the thin film portion 127 having a thickness t ₃ (for example, 400 Å to 450 Å) _{thinner than the thickness t 2} of the gate insulating film 115 at the boundary portion between the gate insulating film 115 and the embedded insulating film 126. Are provided integrally. That is, in the insulating film in the gate trench 114, the thin film portion 127 is formed in the portion in contact with the bottom of the gate electrode 116. The thin film portion 127 may be made of the same insulating material as the gate insulating film 115 and the embedded insulating film 126, such as silicon oxide (SiO _2).

With reference to FIG. 16 again, the p ^- type body region 117 is formed on the surface portion of the epitaxial layer 124 in each unit cell 125. The impurity concentration of the p ^- type body region 117 may be, for example, 1.0 × 10 ¹⁶ cm ^{-3 to} 3.5 × 10 ¹⁶ cm ^-3 .
The n ⁺ type source region 118 is formed on the surface portion ^{of the p − type body region 117 in each unit cell 125.} The impurity concentration of the n ⁺ type source region 118 may be, for example, 1.0 × 10 ¹⁹ cm ^{-3 to} 1.0 × 10 ²⁰ cm ^-3 .

The n ^{- type drain region 119 is an n-} type portion on the opposite side of the n ^{+ type source region 118 with respect to the p-} type body region 117 in the epitaxial layer 124, and is a region common to a plurality of unit cells 125. be. Further, n ^- -type drain region 119 is a region where the conductivity type of the epitaxial layer 124 is maintained. Therefore, the impurity concentration in the n ⁻ type drain region 119 may be, for example, 2.0 × 10 ¹⁶ cm ^{-3 to} 6.0 × 10 ¹⁶ cm ^-3 (same as the n ⁻ type epitaxial layer 124). .. The n ^- type drain region 119 may be referred to as ^{an n-type drift region.}

The p ⁺ type body contact region 120 is formed in each unit cell 125 so as ^{to penetrate the n +} type source region 118 ^{from the surface of the epitaxial layer 124 and contact the p −} type body region 117. The impurity concentration of the p ⁺ type body contact region 120 may be, for example, 1.0 × 10 ¹⁶ cm ^{-3 to} 3.5 × 10 ¹⁶ cm ^-3 .
The interlayer insulating film 121 is made of _{an insulating material such as silicon oxide (SiO 2} ) and is arranged on the semiconductor substrate 102. The interlayer insulating film 121 is formed with contact holes 128 that expose ^{the n +} type source region 118 and the p ^{+ type body contact region 120.} The source metal 105 is connected to the n ⁺ type source region 118 and the p ⁺ type body contact region 120 via the contact hole 128.

The drain electrode 122 is made of a conductive material such as an aluminum (Al) -based material (for example, AlCu or the like) and is formed on the back surface of the semiconductor substrate 102.
FIG. 18 is an enlarged view of the area surrounded by the broken line IV of FIG. FIG. 19 is a diagram showing a cross section of the XIX-XIX cutting line of FIG. In FIGS. 18 and 19, the same reference numerals may be given to the configurations shown in FIGS. 15 to 17 described above, and the description thereof may be omitted.

With reference to FIGS. 18 and 19, a bidirectional Zener diode 129 is arranged in the region directly below the gate pad 111. The bidirectional Zener diode 129 is formed on the semiconductor substrate 102 via an insulating film 130 (for example, silicon oxide). The bidirectional Zener diode 129 has a structure in which the n ^{+ mold portion 131 as an example of the first conductive mold portion of the reference invention and the p −} mold portion 132 as an example of the second conductive mold portion of the reference invention are alternately repeated. Both ends of the repeating structure are n ⁺ mold portions 131. In this embodiment, as shown in FIG. 18, in the bidirectional Zener diode 129, the n ⁺ type portion 131 at one end is arranged in the center of the inner region of the gate pad 111, and the remaining p ^- type portions 132 and n. ^{The +} mold portion 131 is arranged concentrically so as to surround the ^{central n + mold portion 131.}

Further, in this embodiment, the bidirectional Zener diode 129 is composed of a polysilicon layer. The n ⁺ type portion 131 and the p ^- type portion 132 are configured as n-type or p-type impurity regions selectively formed on the polysilicon layer. For example, the n ⁺ type portion 131 and the p ^- type portion 132 may have the same impurity concentration as ^{the n +} type source region 118 and the p ^{-type body region 117, respectively.}

The interlayer insulating film 121 covers the bidirectional Zener diode 129. The interlayer insulating film 121 is formed with a gate-side contact hole 133 that exposes ^{the n +} mold portion 131 at one end in the inner region of the gate pad 111.
The gate-side contact hole 133 is formed, for example, in a straight line along the peripheral edge of ^{the central n + mold portion 131.} In this embodiment, the central n ⁺ mold portion 131 is formed in a rectangular shape in a plan view, and a total of four gate-side contact holes 133 are formed on each peripheral edge of the ^{central n + mold portion 131.} ing.

^{The gate pad 111 is connected to the central n +} mold portion 131 via a contact plug 134 (for example, a conductive material such as tungsten (W)) embedded in each gate-side contact hole 133.
^{Further, the interlayer insulating film 121 exposes the n +} mold portion 131 at the other end directly below the source pad 110 behind the gate pad 111 (opposite the connection position of the gate finger 112 in the gate pad 111). A side contact hole 135 is formed.

The source-side contact hole 135 is formed, for example, in a straight line along the peripheral edge of one of ^{the outermost n + mold portions 131.} In this embodiment, the outermost n ⁺ mold portion 131 is formed in a square ring in a plan view, and the source side contact hole 135 is formed along one peripheral edge of ^{the outermost n + mold portion 131.} There is.
^{The source pad 110 is connected to the outermost n +} mold portion 131 via a contact plug 136 (for example, a conductive material such as tungsten (W)) embedded in the contact hole 135 on the source side.

Next, a method for manufacturing the semiconductor device 1 will be described. FIG. 20 is a diagram showing a flow of a manufacturing method of the semiconductor device 101. 21A to 21D are cross-sectional views for explaining a process related to the formation of the gate insulating film 115.
In order to manufacture the semiconductor device 101, for example, an epitaxial layer 124 made of ^{n −} type silicon is formed by epitaxial growth on a base substrate 123 of ^{n + type silicon (S1).}

The next step is the formation of the gate trench 114 and the gate insulating film 115. As shown in FIG. 21A, a gate trench 114 is formed in the epitaxial layer 124 by a method such as reactive ion etching (RIE) (S2).
Next, as shown in FIG. 21B, the insulating film 137 is deposited on the epitaxial layer 124 by, for example, the CVD method (S3). The deposition of the insulating film 137 continues until the gate trench 114 is backfilled and the surface of the epitaxial layer 124 is covered with an insulating material.

Next, as shown in FIG. 21C, a part of the insulating film 137 is removed by, for example, etch back (S4). As a result, the embedded insulating film 126 made of the insulating film 137 remaining at the bottom of the gate trench 114 is obtained.
Next, as shown in FIG. 21D, the side surface of the gate trench 114 is oxidized to form the gate insulating film 115 by, for example, thermal oxidation (S5).

Although a specific illustration is omitted from here again, after the gate insulating film 115 is formed, polysilicon, which is a material of the gate electrode 116, is deposited (S6) by, for example, a CVD method, and is unnecessary after the deposition, for example, by etchback. The portion is removed (S7). As a result, the gate electrode 116 embedded in the gate trench 114 is obtained.
Next, for example, by a CVD method, an insulating film 130 serving as a base for the bidirectional Zener diode 129 is formed on the epitaxial layer 124 (S8).

Next, for example, by the CVD method, polysilicon, which is a material of the bidirectional Zener diode 129, is deposited (S9), and after the deposition, unnecessary portions are removed by, for example, etch back (S10). As a result, a polysilicon layer for a diode is obtained on the insulating film 130.
Next, a mask having an opening selectively is applied to the region ^{where the n +} type source region 118 should be formed on the epitaxial layer 124, and the n-type impurities are injected through the mask. At this time, n-type impurities are also injected into the photodiode layer at the same time (S11). The injection into the polysilicon layer for a diode may be a full-scale injection without a mask.

Next, a mask having an opening selectively is applied to the region ^{where the p-} type body region 117 should be formed on the epitaxial layer 124, and the p-type impurities are injected through the mask. At this time, the p-type impurities are also injected into the polysilicon layer for the diode at the same time (S12). The injection into the polysilicon layer for a diode may be performed by masking the region where the ^{p-type portion 132 is not formed.}

^{Next, a mask having an opening selectively is applied to the region where the p +} type body contact region 120 should be formed on the epitaxial layer 124, and the p-type impurities are injected through the mask (S13).
After that, the impurities injected in S11 to S13 are diffused, so that the p ^- type body region 117, the n ⁺ type source region 118, the p ⁺ type body contact region 120, and the bidirectional Zener diode 129 are n ⁺ type. A portion 131 and a p ^- type portion 132 are formed.

Next, for example, by a CVD method, an interlayer insulating film 121 is formed on the epitaxial layer 124 (S14), and contact holes 128, 133, 135 are formed in the interlayer insulating film 121 (S15).
Next, after the contact plugs 134 and 136 are embedded in the gate-side contact hole 133 and the source-side contact hole 135, the source metal 105 and the gate metal 106 are formed on the interlayer insulating film 121 (S16).

Next, the drain electrode 122 is formed on the back surface of the semiconductor substrate 102 by, for example, a sputtering method. Through the above steps, the semiconductor device 1 is obtained.
The semiconductor device 101 can be used, for example, as a switching element. In this case, a predetermined voltage (voltage equal to or higher than the gate threshold voltage) is applied to the gate metal 106 with a drain voltage having a positive drain side applied between the source metal 105 and the drain electrode 122 (between the source and drain). do. As a result, ^{a channel is formed in the vicinity of the gate insulating film 115 in the p-} type body region 117 along the depth direction of the gate trench 114, and a current flows in the depth direction of the gate trench 114.

According to the semiconductor device 101, as shown in FIGS. 18 and 19, a bidirectional Zener diode 129 is connected between the gate metal 106 and the source metal 105 (between the gate and the source). Therefore, even if a noise current or the like caused by electrostatic discharge enters the semiconductor device 101, the noise current can be preferentially passed through the bidirectional Zener diode 129 to be released to the outside (ground potential).

That is, as shown in FIG. 22, when the breakdown withstand of the gate insulating film 115 (the gate insulating film 115 here is a concept including the thin film portion 127) is around 25 V, the bidirectional Zener diode 129 is built in. If a voltage of about 25 V is applied between the gate and the source in a non-existing state, the gate insulating film 115 is destroyed near 25 V and a leak current flows. This leakage current becomes more remarkable as the gate-source voltage Vgs increases, and increases almost proportionally from the voltage value corresponding to the breakdown withstand capacity.

On the other hand, as shown by the breakdown waveforms of the two diodes in FIG. 22, if a bidirectional Zener diode 129 that causes breakdown at a voltage lower than the breakdown withstand of the gate insulating film 115 is built-in, noise current or the like is present. The bidirectional Zener diode 129 is broken down before the gate insulating film 115, whereby the noise current is preferentially passed through the bidirectional Zener diode 129, and ESD protection of the semiconductor device 101 can be achieved. it is conceivable that.

However, in the diode of the first form of FIG. 22, since the waveform after breakdown is considerably gentler than the waveform of the gate insulating film 115, the gate-source voltage Vgs of about 40 V is defined as a boundary (diode waveform and gate insulation). A noise current flows into the gate insulating film 115 at the intersection A) with the film waveform, and the gate insulating film 115 is destroyed.
On the other hand, as in the diode of the second form of FIG. 22, if the waveform after breakdown is steeper than that of the first form and the slope is close to the slope of the waveform of the gate insulating film 115, it is relatively high. Even if the gate-source voltage Vgs is applied, the noise current can continue to flow preferentially to the bidirectional Zener diode 129, and the gate insulating film 115 can be prevented from being destroyed.

Next, the breakdown mechanism of the diode of the first form and the diode of the second form will be described in detail with reference to FIGS. 23 and 24.
First, FIG. 23 is a diagram for explaining the breakdown mechanism of the bidirectional Zener diode 129 according to the first embodiment, in which the bidirectional Zener diode 129 is broken down by avalanche breakdown (avalanche design). ..

According to FIG. 23, since the withstand voltage (breakdown voltage) of the bidirectional Zener diode 129 ^{is defined by the impurity concentrations of the n +} type portion 131 and the p ^- type portion 132, the gate-source corresponding to the breakdown voltage. when voltage Vgs is applied, and the n ⁺ -type portions 131 of the n ⁺ -type portion 131 and the gate side of the source side is turned on by an avalanche breakdown. Therefore, even after the breakdown, each p ^- type portion 132 is not filled with the depletion layer 138 (lower side of FIG. 23), and ^{a part of the p-} type portion 132 remains with a constant width. The ^{remaining portion of the p-} type portion 132 becomes a series resistance 139 when the noise current flows through the bidirectional Zener diode 129 from the source side to the gate side. Therefore, as shown in FIGS. 22 and 25, the noise current (vertical axis lgs in FIGS. 22 and 25) increases only moderately even after the breakdown, and the gate insulating film 115 is likely to be destroyed.

On the other hand, FIG. 24 is a diagram for explaining the breakdown mechanism of the bidirectional Zener diode 129 according to the second embodiment, in which the bidirectional Zener diode 129 is broken down by punch-through (punch). Through design).
According to FIG. 24, the withstand voltage (breakdown voltage) of the bidirectional Zener diode 129 is defined by the width of the ^{p-type unit 132.} Specifically, the width Wp of the p ^- type portion 132 is defined to be smaller than the width Wd of the depletion layer 138 that expands when a breakdown voltage is applied between the gate and the source, for example (Wp ≦ Wd). ). Therefore, the gate corresponds to the breakdown voltage of the bidirectional Zener diode 129 - when the source voltage Vgs is applied, conduction between the n ⁺ -type portions 131 of the n ⁺ -type portion 131 and the gate side of the source-side by the punch-through Can be made to. Therefore, after the breakdown, ^{the region of each p-} type portion 132 is filled with the depletion layer 138 (lower side of FIG. 24), so that the series resistance can be reduced as compared with the avalanche design of FIG. 23. As a result, as shown in FIGS. 22 and 25, the increase in the noise current after breakdown (vertical axis lgs in FIGS. 22 and 25) becomes steeper than that in the avalanche design of FIG. 23, and thus the noise current. Can be satisfactorily released to the ground potential via the bidirectional Zener diode 129.

FIG. 26 is a diagram for explaining how the breakdown voltage BVgss and electrostatic breakdown tolerance between the gate and the source change with respect to the design dimensions ^{of the p-type portion 132 of the bidirectional Zener diode 129.} be.
According to FIG. 26, the breakdown voltage BVgss between the gate and the source converges at about 27 V even if the width ^{of the p-mold portion 132 is larger than the design dimension of 2.6 μm.} On the other hand, the electrostatic breakdown resistance sharply decreases in the region of 2.6 μm or more. That, and the 2.6μm on the boundary, p ^- the width of the mold portion 132 is more regions, p ^- regardless of the breadth of the mold portion 132 p ^- Break by avalanche breakdown, which is defined by the concentration of mold portion 132 Down occurs, and as a result, the gate insulating film 115 is easily broken (electrostatic breakdown resistance is low).

On the other hand, in ^{the region where the width of the p-} mold portion 132 is 2.6 μm or less, the breakdown voltage BVgss between the gate and the source increases in proportion to the design dimension of the ^{p-mold portion 132. -} it can be confirmed that the breakdown by punch-through related to the width of the mold portion 132 has occurred. Therefore, in ^{the region where the width of the p-} type portion 132 is 2.6 μm or less, the noise current is satisfactorily absorbed according to the mechanism shown in FIG. 24, so that a high electrostatic breakdown resistance is maintained.

Therefore, based on FIG. 26, for example, if the "gate-source rated voltage Vgss" guaranteed for the semiconductor device 101 is 20 V, the gate-source voltage exceeding this rated voltage Vgss is applied to the gate insulating film 115. ^{Therefore, the design dimension of the p-} mold portion 132 is set to 2.5 μm (± 0.1 μm) in anticipation of a variation of 0.1 μm. Then, when the voltage exceeds 20 V, the bidirectional Zener diode 129 is broken down by punch-through to sufficiently release the noise current, while suppressing the current flowing through the gate insulating film 115. As a result, it is possible to maintain a high electrostatic breakdown resistance of about 30 V.

The above-mentioned preferable design dimensions are merely an example for demonstrating the effect of the semiconductor device 101, and vary depending on the impurity concentration of ^{the p-type portion 132 constituting the bidirectional Zener diode 1029.} For example, if ^{the impurity concentration of the p-} type portion 132 is in ^{the range of 2.0 × 10 16} cm ^{-3 to} 6.0 × 10 ¹⁶ cm ^-3 , the above width of 2.4 μm to 2.6 μm is preferable.
As described above, according to the semiconductor device 101, a high electrostatic breakdown resistance can be realized.

This can be further demonstrated by FIG. 27. FIG. 27 is a diagram showing that a sufficient electrostatic breakdown resistance can be realized even if the area of the active region of the semiconductor device 101 is reduced and miniaturized. In FIG. 27, the second form and the first form correspond to the second form and the first form shown in FIGS. 22 to 25 described above. On the other hand, in the conventional example, the embedded insulating film 126 and the thin film portion 127 are not formed in the gate trench 114, and the gate insulating film thicker than the thin film portion 127 is formed with a substantially uniform thickness. A semiconductor device having the same configuration as that of the first embodiment is shown.

That is, according to FIG. 27, since the semiconductor device of the second form has the thin film portion 127, the breaking resistance of the insulating film itself in the gate trench 114 is lower than that of the conventional example, but the semiconductor device. A high electrostatic breakdown resistance can be achieved as a whole.
Therefore, for example, the embedded insulating film 126, which is thicker than the gate insulating film 115, is adopted to reduce the capacitance between the gate and the drain, or each part of the semiconductor device 101 is miniaturized to reduce the on-resistance and the capacitance. Can be planned.

Further, since it is not necessary to increase the thickness of the gate insulating film 115 in order to improve the fracture resistance, the thickness of the gate insulating film 115 can be designed by focusing on the switching performance of the transistor. Therefore, the influence on the switching performance of the transistor can be small.
Although one embodiment of the reference invention has been described above, the reference invention can also be implemented in other embodiments.

For example, a configuration in which the conductive type of each semiconductor portion of the semiconductor device 101 is inverted may be adopted. That is, in the semiconductor device 101, the p-type portion may be n-type and the n-type portion may be p-type.

1: Semiconductor device 2: Semiconductor layer 27: Trench gate structure 28: Gate trench 29: First inner wall insulating film (gate insulating film)
30: Embedded gate electrode 34: p-type body region 35: n ⁺ type source region 46: Diode trench 47: Second inner wall insulating film (inner wall insulating film)
48: Second side wall insulating film (side wall insulating film)
49: Second bottom wall insulating film (bottom wall insulating film)
51: Upper surface of bidirectional Zener diode 52: n ⁺ type portion of bidirectional Zener diode 53: P-type portion of bidirectional Zener diode 54: Polysilicon body 55: p-type floating region 56: Inversion suppression structure 57: Side wall protective film 61: Electromagnetic relaxation structure 62: Electroelectric relaxation trench 63: Third inner wall insulating film (electrical relaxation inner wall insulating film)
64: Embedded conductor 95: Semiconductor device 96: Inversion suppression structure 97: Semiconductor device 98: Inversion suppression structure D: Bidirectional Zener diode Tr: Insulated gate type field effect transistor 101: Semiconductor device 102: Semiconductor substrate 105: Source metal 106 : Gate metal 111: Gate pad 114: Gate trench 115: Gate insulating film 116: Gate electrode 117: p ^- type body region 118: n ⁺ type source region 119: n ^- type drain region 126: Embedded insulating film 127: Thin film portion 129: Bidirectional Zener diode 131: n ⁺ mold part 132: p ^- mold part 138: poor layer

Claims (13)

A first conductive semiconductor layer having a main surface on which a diode trench is formed,
An inner wall insulating film formed along the inner wall of the diode trench,
A bidirectional Zener diode formed in the diode trench and having at least one second conductive mold portion formed between the pair of first conductive mold portions and the pair of first conductive mold portions.
A second conductive type floating region formed in a region along the bottom wall of the diode trench in the semiconductor layer,
A second conductive type body region formed on the surface layer of the main surface of the semiconductor layer, and
The first conductive type source region formed on the surface layer of the body region and
A first conductive type drain region including the semiconductor layer formed on the opposite side of the main surface with respect to the body region,
The gate trench formed on the main surface of the semiconductor layer and
A gate insulating film formed along the inner wall of the gate trench and
A gate electrode embedded in the gate trench with the gate insulating film interposed therebetween and facing the source region, the body region and the drain region with the gate insulating film interposed therebetween.
Including a source electrode connected to the source region
The inner wall insulating film is a side wall insulating film formed along the side wall of the diode trench, and a bottom formed along the bottom wall of the diode trench and having a thickness larger than the thickness of the side wall insulating film. Including wall insulating film,
The gate insulating film has a thickness larger than the thickness of the gate sidewall insulating film formed along the side wall of the gate trench and the gate sidewall insulating film formed along the bottom wall of the gate trench and having a thickness larger than the thickness of the gate sidewall insulating film. Includes gate bottom wall insulating film
The thickness of the bottom wall insulating film is substantially rather equal to the thickness of the gate bottom wall insulating film,
The bidirectional Zener diode is entirely formed on the bottom wall insulating film.
The bidirectional Zener is formed by the bottom wall insulating film interposed between the bottom wall of the diode trench and the bidirectional Zener diode, and the floating region facing the bidirectional Zener diode with the bottom wall insulating film interposed therebetween. A semiconductor device having an inversion suppressing structure for suppressing the inversion of the conductive type of the second conductive type portion of the diode to the first conductive type. The bidirectional Zener diode has an upper surface facing the opening of the diode trench.
The top surface of the bidirectional Zener diode, the are formed in the semiconductor layer of the main surface on the same plane, the semiconductor device according to claim 1. The semiconductor device according to claim 1 or 2 , wherein the bidirectional Zener diode is formed in the diode trench at a distance from the side wall insulating film. The bidirectional Zener diode is formed in the diode trench at a distance from the side wall of the diode trench.
The semiconductor device according to any one of claims 1 to 3 , wherein the distance between the side wall of the bidirectional Zener diode and the side wall of the diode trench is larger than the thickness of the bidirectional Zener diode. The semiconductor device according to claim 3 or 4 , further comprising an insulating side wall protective film that protects the side wall of the bidirectional Zener diode. The bidirectional Zener diode contains a polysilicon body, and the bidirectional Zener diode contains
The pair of first conductive mold portions include a first conductive mold impurity region selectively formed on the polysilicon body.
The semiconductor device according to any one of claims 1 to 5 , wherein the second conductive mold portion includes a second conductive type impurity region selectively formed on the polysilicon body. In the bidirectional Zener diode, one of the pair of first conductive mold portions is electrically connected to the gate electrode, and the other of the first conductive mold portions of the pair is electrically connected to the source electrode. The semiconductor device according to any one of claims 1 to 6 , which is connected to the semiconductor device. The gate trench has the same depth as the diode trench.
The gate insulating film has the same insulating material as the inner wall insulating film, and has the same insulating material.
The semiconductor device according to any one of claims 1 to 7 , wherein the gate electrode has the same conductive material as the bidirectional Zener diode. One of claims 1 to 8 , further comprising an electric field relaxation structure formed on the surface layer portion of the main surface of the semiconductor layer and relaxing the electric field in the peripheral region in the peripheral region along the peripheral edge of the diode trench. The semiconductor device described in the section. The semiconductor device according to claim 9 , wherein the plurality of electric field relaxation structures are formed at intervals in a direction away from the diode trench. The semiconductor device according to claim 9 or 10 , wherein the electric field relaxation structure is formed so as to surround the diode trench. An electric field relaxation trench is further formed on the main surface of the semiconductor layer.
The electric field relaxation structure is
The electric field relaxation inner wall insulating film formed along the inner wall of the electric field relaxation trench,
The semiconductor device according to any one of claims 9 to 11 , further comprising an embedded conductor embedded in the electric field relaxation trench with the electric field relaxation inner wall insulating film interposed therebetween. The electric field relaxation trench has the same depth as the diode trench.
The electric field relaxation inner wall insulating film has the same insulating material as the inner wall insulating film.
The semiconductor device according to claim 12 , wherein the embedded conductor has the same conductive material as the bidirectional Zener diode.

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